Merge branch 'next-i2c' of git://aeryn.fluff.org.uk/bjdooks/linux
* 'next-i2c' of git://aeryn.fluff.org.uk/bjdooks/linux: i2c: driver for the Synopsys DesignWare I2C controller
This commit is contained in:
Linus Torvalds
Коммит
7b58fc2184
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@ -326,6 +326,15 @@ config I2C_DAVINCI
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devices such as DaVinci NIC.
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For details please see http://www.ti.com/davinci
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config I2C_DESIGNWARE
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tristate "Synopsys DesignWare"
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help
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If you say yes to this option, support will be included for the
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Synopsys DesignWare I2C adapter. Only master mode is supported.
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This driver can also be built as a module. If so, the module
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will be called i2c-designware.
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config I2C_GPIO
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tristate "GPIO-based bitbanging I2C"
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depends on GENERIC_GPIO
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@ -30,6 +30,7 @@ obj-$(CONFIG_I2C_AU1550) += i2c-au1550.o
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obj-$(CONFIG_I2C_BLACKFIN_TWI) += i2c-bfin-twi.o
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obj-$(CONFIG_I2C_CPM) += i2c-cpm.o
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obj-$(CONFIG_I2C_DAVINCI) += i2c-davinci.o
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obj-$(CONFIG_I2C_DESIGNWARE) += i2c-designware.o
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obj-$(CONFIG_I2C_GPIO) += i2c-gpio.o
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obj-$(CONFIG_I2C_HIGHLANDER) += i2c-highlander.o
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obj-$(CONFIG_I2C_IBM_IIC) += i2c-ibm_iic.o
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@ -0,0 +1,624 @@
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/*
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* Synopsys Designware I2C adapter driver (master only).
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*
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* Based on the TI DAVINCI I2C adapter driver.
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*
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* Copyright (C) 2006 Texas Instruments.
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* Copyright (C) 2007 MontaVista Software Inc.
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* Copyright (C) 2009 Provigent Ltd.
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*
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* ----------------------------------------------------------------------------
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
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* ----------------------------------------------------------------------------
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*
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*/
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/delay.h>
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#include <linux/i2c.h>
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#include <linux/clk.h>
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#include <linux/errno.h>
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#include <linux/sched.h>
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#include <linux/err.h>
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#include <linux/interrupt.h>
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#include <linux/platform_device.h>
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#include <linux/io.h>
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/*
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* Registers offset
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*/
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#define DW_IC_CON 0x0
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#define DW_IC_TAR 0x4
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#define DW_IC_DATA_CMD 0x10
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#define DW_IC_SS_SCL_HCNT 0x14
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#define DW_IC_SS_SCL_LCNT 0x18
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#define DW_IC_FS_SCL_HCNT 0x1c
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#define DW_IC_FS_SCL_LCNT 0x20
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#define DW_IC_INTR_STAT 0x2c
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#define DW_IC_INTR_MASK 0x30
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#define DW_IC_CLR_INTR 0x40
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#define DW_IC_ENABLE 0x6c
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#define DW_IC_STATUS 0x70
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#define DW_IC_TXFLR 0x74
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#define DW_IC_RXFLR 0x78
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#define DW_IC_COMP_PARAM_1 0xf4
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#define DW_IC_TX_ABRT_SOURCE 0x80
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#define DW_IC_CON_MASTER 0x1
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#define DW_IC_CON_SPEED_STD 0x2
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#define DW_IC_CON_SPEED_FAST 0x4
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#define DW_IC_CON_10BITADDR_MASTER 0x10
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#define DW_IC_CON_RESTART_EN 0x20
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#define DW_IC_CON_SLAVE_DISABLE 0x40
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#define DW_IC_INTR_TX_EMPTY 0x10
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#define DW_IC_INTR_TX_ABRT 0x40
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#define DW_IC_INTR_STOP_DET 0x200
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#define DW_IC_STATUS_ACTIVITY 0x1
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#define DW_IC_ERR_TX_ABRT 0x1
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/*
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* status codes
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*/
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#define STATUS_IDLE 0x0
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#define STATUS_WRITE_IN_PROGRESS 0x1
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#define STATUS_READ_IN_PROGRESS 0x2
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#define TIMEOUT 20 /* ms */
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/*
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* hardware abort codes from the DW_IC_TX_ABRT_SOURCE register
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*
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* only expected abort codes are listed here
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* refer to the datasheet for the full list
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*/
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#define ABRT_7B_ADDR_NOACK 0
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#define ABRT_10ADDR1_NOACK 1
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#define ABRT_10ADDR2_NOACK 2
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#define ABRT_TXDATA_NOACK 3
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#define ABRT_GCALL_NOACK 4
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#define ABRT_GCALL_READ 5
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#define ABRT_SBYTE_ACKDET 7
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#define ABRT_SBYTE_NORSTRT 9
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#define ABRT_10B_RD_NORSTRT 10
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#define ARB_MASTER_DIS 11
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#define ARB_LOST 12
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static char *abort_sources[] = {
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[ABRT_7B_ADDR_NOACK] =
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"slave address not acknowledged (7bit mode)",
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[ABRT_10ADDR1_NOACK] =
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"first address byte not acknowledged (10bit mode)",
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[ABRT_10ADDR2_NOACK] =
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"second address byte not acknowledged (10bit mode)",
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[ABRT_TXDATA_NOACK] =
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"data not acknowledged",
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[ABRT_GCALL_NOACK] =
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"no acknowledgement for a general call",
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[ABRT_GCALL_READ] =
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"read after general call",
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[ABRT_SBYTE_ACKDET] =
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"start byte acknowledged",
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[ABRT_SBYTE_NORSTRT] =
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"trying to send start byte when restart is disabled",
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[ABRT_10B_RD_NORSTRT] =
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"trying to read when restart is disabled (10bit mode)",
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[ARB_MASTER_DIS] =
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"trying to use disabled adapter",
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[ARB_LOST] =
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"lost arbitration",
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};
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/**
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* struct dw_i2c_dev - private i2c-designware data
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* @dev: driver model device node
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* @base: IO registers pointer
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* @cmd_complete: tx completion indicator
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* @pump_msg: continue in progress transfers
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* @lock: protect this struct and IO registers
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* @clk: input reference clock
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* @cmd_err: run time hadware error code
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* @msgs: points to an array of messages currently being transfered
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* @msgs_num: the number of elements in msgs
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* @msg_write_idx: the element index of the current tx message in the msgs
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* array
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* @tx_buf_len: the length of the current tx buffer
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* @tx_buf: the current tx buffer
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* @msg_read_idx: the element index of the current rx message in the msgs
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* array
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* @rx_buf_len: the length of the current rx buffer
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* @rx_buf: the current rx buffer
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* @msg_err: error status of the current transfer
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* @status: i2c master status, one of STATUS_*
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* @abort_source: copy of the TX_ABRT_SOURCE register
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* @irq: interrupt number for the i2c master
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* @adapter: i2c subsystem adapter node
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* @tx_fifo_depth: depth of the hardware tx fifo
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* @rx_fifo_depth: depth of the hardware rx fifo
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*/
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struct dw_i2c_dev {
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struct device *dev;
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void __iomem *base;
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struct completion cmd_complete;
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struct tasklet_struct pump_msg;
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struct mutex lock;
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struct clk *clk;
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int cmd_err;
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struct i2c_msg *msgs;
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int msgs_num;
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int msg_write_idx;
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u16 tx_buf_len;
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u8 *tx_buf;
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int msg_read_idx;
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u16 rx_buf_len;
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u8 *rx_buf;
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int msg_err;
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unsigned int status;
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u16 abort_source;
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int irq;
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struct i2c_adapter adapter;
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unsigned int tx_fifo_depth;
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unsigned int rx_fifo_depth;
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};
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/**
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* i2c_dw_init() - initialize the designware i2c master hardware
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* @dev: device private data
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*
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* This functions configures and enables the I2C master.
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* This function is called during I2C init function, and in case of timeout at
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* run time.
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*/
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static void i2c_dw_init(struct dw_i2c_dev *dev)
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{
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u32 input_clock_khz = clk_get_rate(dev->clk) / 1000;
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u16 ic_con;
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/* Disable the adapter */
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writeb(0, dev->base + DW_IC_ENABLE);
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/* set standard and fast speed deviders for high/low periods */
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writew((input_clock_khz * 40 / 10000)+1, /* std speed high, 4us */
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dev->base + DW_IC_SS_SCL_HCNT);
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writew((input_clock_khz * 47 / 10000)+1, /* std speed low, 4.7us */
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dev->base + DW_IC_SS_SCL_LCNT);
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writew((input_clock_khz * 6 / 10000)+1, /* fast speed high, 0.6us */
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dev->base + DW_IC_FS_SCL_HCNT);
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writew((input_clock_khz * 13 / 10000)+1, /* fast speed low, 1.3us */
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dev->base + DW_IC_FS_SCL_LCNT);
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/* configure the i2c master */
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ic_con = DW_IC_CON_MASTER | DW_IC_CON_SLAVE_DISABLE |
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DW_IC_CON_RESTART_EN | DW_IC_CON_SPEED_FAST;
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writew(ic_con, dev->base + DW_IC_CON);
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}
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/*
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* Waiting for bus not busy
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*/
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static int i2c_dw_wait_bus_not_busy(struct dw_i2c_dev *dev)
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{
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int timeout = TIMEOUT;
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while (readb(dev->base + DW_IC_STATUS) & DW_IC_STATUS_ACTIVITY) {
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if (timeout <= 0) {
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dev_warn(dev->dev, "timeout waiting for bus ready\n");
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return -ETIMEDOUT;
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}
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timeout--;
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mdelay(1);
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}
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return 0;
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}
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/*
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* Initiate low level master read/write transaction.
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* This function is called from i2c_dw_xfer when starting a transfer.
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* This function is also called from dw_i2c_pump_msg to continue a transfer
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* that is longer than the size of the TX FIFO.
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*/
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static void
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i2c_dw_xfer_msg(struct i2c_adapter *adap)
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{
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struct dw_i2c_dev *dev = i2c_get_adapdata(adap);
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struct i2c_msg *msgs = dev->msgs;
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int num = dev->msgs_num;
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u16 ic_con, intr_mask;
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int tx_limit = dev->tx_fifo_depth - readb(dev->base + DW_IC_TXFLR);
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int rx_limit = dev->rx_fifo_depth - readb(dev->base + DW_IC_RXFLR);
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u16 addr = msgs[dev->msg_write_idx].addr;
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u16 buf_len = dev->tx_buf_len;
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||||
if (!(dev->status & STATUS_WRITE_IN_PROGRESS)) {
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/* Disable the adapter */
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writeb(0, dev->base + DW_IC_ENABLE);
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||||
/* set the slave (target) address */
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writew(msgs[dev->msg_write_idx].addr, dev->base + DW_IC_TAR);
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||||
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||||
/* if the slave address is ten bit address, enable 10BITADDR */
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ic_con = readw(dev->base + DW_IC_CON);
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||||
if (msgs[dev->msg_write_idx].flags & I2C_M_TEN)
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ic_con |= DW_IC_CON_10BITADDR_MASTER;
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||||
else
|
||||
ic_con &= ~DW_IC_CON_10BITADDR_MASTER;
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||||
writew(ic_con, dev->base + DW_IC_CON);
|
||||
|
||||
/* Enable the adapter */
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||||
writeb(1, dev->base + DW_IC_ENABLE);
|
||||
}
|
||||
|
||||
for (; dev->msg_write_idx < num; dev->msg_write_idx++) {
|
||||
/* if target address has changed, we need to
|
||||
* reprogram the target address in the i2c
|
||||
* adapter when we are done with this transfer
|
||||
*/
|
||||
if (msgs[dev->msg_write_idx].addr != addr)
|
||||
return;
|
||||
|
||||
if (msgs[dev->msg_write_idx].len == 0) {
|
||||
dev_err(dev->dev,
|
||||
"%s: invalid message length\n", __func__);
|
||||
dev->msg_err = -EINVAL;
|
||||
return;
|
||||
}
|
||||
|
||||
if (!(dev->status & STATUS_WRITE_IN_PROGRESS)) {
|
||||
/* new i2c_msg */
|
||||
dev->tx_buf = msgs[dev->msg_write_idx].buf;
|
||||
buf_len = msgs[dev->msg_write_idx].len;
|
||||
}
|
||||
|
||||
while (buf_len > 0 && tx_limit > 0 && rx_limit > 0) {
|
||||
if (msgs[dev->msg_write_idx].flags & I2C_M_RD) {
|
||||
writew(0x100, dev->base + DW_IC_DATA_CMD);
|
||||
rx_limit--;
|
||||
} else
|
||||
writew(*(dev->tx_buf++),
|
||||
dev->base + DW_IC_DATA_CMD);
|
||||
tx_limit--; buf_len--;
|
||||
}
|
||||
}
|
||||
|
||||
intr_mask = DW_IC_INTR_STOP_DET | DW_IC_INTR_TX_ABRT;
|
||||
if (buf_len > 0) { /* more bytes to be written */
|
||||
intr_mask |= DW_IC_INTR_TX_EMPTY;
|
||||
dev->status |= STATUS_WRITE_IN_PROGRESS;
|
||||
} else
|
||||
dev->status &= ~STATUS_WRITE_IN_PROGRESS;
|
||||
writew(intr_mask, dev->base + DW_IC_INTR_MASK);
|
||||
|
||||
dev->tx_buf_len = buf_len;
|
||||
}
|
||||
|
||||
static void
|
||||
i2c_dw_read(struct i2c_adapter *adap)
|
||||
{
|
||||
struct dw_i2c_dev *dev = i2c_get_adapdata(adap);
|
||||
struct i2c_msg *msgs = dev->msgs;
|
||||
int num = dev->msgs_num;
|
||||
u16 addr = msgs[dev->msg_read_idx].addr;
|
||||
int rx_valid = readw(dev->base + DW_IC_RXFLR);
|
||||
|
||||
for (; dev->msg_read_idx < num; dev->msg_read_idx++) {
|
||||
u16 len;
|
||||
u8 *buf;
|
||||
|
||||
if (!(msgs[dev->msg_read_idx].flags & I2C_M_RD))
|
||||
continue;
|
||||
|
||||
/* different i2c client, reprogram the i2c adapter */
|
||||
if (msgs[dev->msg_read_idx].addr != addr)
|
||||
return;
|
||||
|
||||
if (!(dev->status & STATUS_READ_IN_PROGRESS)) {
|
||||
len = msgs[dev->msg_read_idx].len;
|
||||
buf = msgs[dev->msg_read_idx].buf;
|
||||
} else {
|
||||
len = dev->rx_buf_len;
|
||||
buf = dev->rx_buf;
|
||||
}
|
||||
|
||||
for (; len > 0 && rx_valid > 0; len--, rx_valid--)
|
||||
*buf++ = readb(dev->base + DW_IC_DATA_CMD);
|
||||
|
||||
if (len > 0) {
|
||||
dev->status |= STATUS_READ_IN_PROGRESS;
|
||||
dev->rx_buf_len = len;
|
||||
dev->rx_buf = buf;
|
||||
return;
|
||||
} else
|
||||
dev->status &= ~STATUS_READ_IN_PROGRESS;
|
||||
}
|
||||
}
|
||||
|
||||
/*
|
||||
* Prepare controller for a transaction and call i2c_dw_xfer_msg
|
||||
*/
|
||||
static int
|
||||
i2c_dw_xfer(struct i2c_adapter *adap, struct i2c_msg msgs[], int num)
|
||||
{
|
||||
struct dw_i2c_dev *dev = i2c_get_adapdata(adap);
|
||||
int ret;
|
||||
|
||||
dev_dbg(dev->dev, "%s: msgs: %d\n", __func__, num);
|
||||
|
||||
mutex_lock(&dev->lock);
|
||||
|
||||
INIT_COMPLETION(dev->cmd_complete);
|
||||
dev->msgs = msgs;
|
||||
dev->msgs_num = num;
|
||||
dev->cmd_err = 0;
|
||||
dev->msg_write_idx = 0;
|
||||
dev->msg_read_idx = 0;
|
||||
dev->msg_err = 0;
|
||||
dev->status = STATUS_IDLE;
|
||||
|
||||
ret = i2c_dw_wait_bus_not_busy(dev);
|
||||
if (ret < 0)
|
||||
goto done;
|
||||
|
||||
/* start the transfers */
|
||||
i2c_dw_xfer_msg(adap);
|
||||
|
||||
/* wait for tx to complete */
|
||||
ret = wait_for_completion_interruptible_timeout(&dev->cmd_complete, HZ);
|
||||
if (ret == 0) {
|
||||
dev_err(dev->dev, "controller timed out\n");
|
||||
i2c_dw_init(dev);
|
||||
ret = -ETIMEDOUT;
|
||||
goto done;
|
||||
} else if (ret < 0)
|
||||
goto done;
|
||||
|
||||
if (dev->msg_err) {
|
||||
ret = dev->msg_err;
|
||||
goto done;
|
||||
}
|
||||
|
||||
/* no error */
|
||||
if (likely(!dev->cmd_err)) {
|
||||
/* read rx fifo, and disable the adapter */
|
||||
do {
|
||||
i2c_dw_read(adap);
|
||||
} while (dev->status & STATUS_READ_IN_PROGRESS);
|
||||
writeb(0, dev->base + DW_IC_ENABLE);
|
||||
ret = num;
|
||||
goto done;
|
||||
}
|
||||
|
||||
/* We have an error */
|
||||
if (dev->cmd_err == DW_IC_ERR_TX_ABRT) {
|
||||
unsigned long abort_source = dev->abort_source;
|
||||
int i;
|
||||
|
||||
for_each_bit(i, &abort_source, ARRAY_SIZE(abort_sources)) {
|
||||
dev_err(dev->dev, "%s: %s\n", __func__, abort_sources[i]);
|
||||
}
|
||||
}
|
||||
ret = -EIO;
|
||||
|
||||
done:
|
||||
mutex_unlock(&dev->lock);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
static u32 i2c_dw_func(struct i2c_adapter *adap)
|
||||
{
|
||||
return I2C_FUNC_I2C | I2C_FUNC_10BIT_ADDR;
|
||||
}
|
||||
|
||||
static void dw_i2c_pump_msg(unsigned long data)
|
||||
{
|
||||
struct dw_i2c_dev *dev = (struct dw_i2c_dev *) data;
|
||||
u16 intr_mask;
|
||||
|
||||
i2c_dw_read(&dev->adapter);
|
||||
i2c_dw_xfer_msg(&dev->adapter);
|
||||
|
||||
intr_mask = DW_IC_INTR_STOP_DET | DW_IC_INTR_TX_ABRT;
|
||||
if (dev->status & STATUS_WRITE_IN_PROGRESS)
|
||||
intr_mask |= DW_IC_INTR_TX_EMPTY;
|
||||
writew(intr_mask, dev->base + DW_IC_INTR_MASK);
|
||||
}
|
||||
|
||||
/*
|
||||
* Interrupt service routine. This gets called whenever an I2C interrupt
|
||||
* occurs.
|
||||
*/
|
||||
static irqreturn_t i2c_dw_isr(int this_irq, void *dev_id)
|
||||
{
|
||||
struct dw_i2c_dev *dev = dev_id;
|
||||
u16 stat;
|
||||
|
||||
stat = readw(dev->base + DW_IC_INTR_STAT);
|
||||
dev_dbg(dev->dev, "%s: stat=0x%x\n", __func__, stat);
|
||||
if (stat & DW_IC_INTR_TX_ABRT) {
|
||||
dev->abort_source = readw(dev->base + DW_IC_TX_ABRT_SOURCE);
|
||||
dev->cmd_err |= DW_IC_ERR_TX_ABRT;
|
||||
dev->status = STATUS_IDLE;
|
||||
} else if (stat & DW_IC_INTR_TX_EMPTY)
|
||||
tasklet_schedule(&dev->pump_msg);
|
||||
|
||||
readb(dev->base + DW_IC_CLR_INTR); /* clear interrupts */
|
||||
writew(0, dev->base + DW_IC_INTR_MASK); /* disable interrupts */
|
||||
if (stat & (DW_IC_INTR_TX_ABRT | DW_IC_INTR_STOP_DET))
|
||||
complete(&dev->cmd_complete);
|
||||
|
||||
return IRQ_HANDLED;
|
||||
}
|
||||
|
||||
static struct i2c_algorithm i2c_dw_algo = {
|
||||
.master_xfer = i2c_dw_xfer,
|
||||
.functionality = i2c_dw_func,
|
||||
};
|
||||
|
||||
static int __devinit dw_i2c_probe(struct platform_device *pdev)
|
||||
{
|
||||
struct dw_i2c_dev *dev;
|
||||
struct i2c_adapter *adap;
|
||||
struct resource *mem, *irq, *ioarea;
|
||||
int r;
|
||||
|
||||
/* NOTE: driver uses the static register mapping */
|
||||
mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
|
||||
if (!mem) {
|
||||
dev_err(&pdev->dev, "no mem resource?\n");
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
irq = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
|
||||
if (!irq) {
|
||||
dev_err(&pdev->dev, "no irq resource?\n");
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
ioarea = request_mem_region(mem->start, resource_size(mem),
|
||||
pdev->name);
|
||||
if (!ioarea) {
|
||||
dev_err(&pdev->dev, "I2C region already claimed\n");
|
||||
return -EBUSY;
|
||||
}
|
||||
|
||||
dev = kzalloc(sizeof(struct dw_i2c_dev), GFP_KERNEL);
|
||||
if (!dev) {
|
||||
r = -ENOMEM;
|
||||
goto err_release_region;
|
||||
}
|
||||
|
||||
init_completion(&dev->cmd_complete);
|
||||
tasklet_init(&dev->pump_msg, dw_i2c_pump_msg, (unsigned long) dev);
|
||||
mutex_init(&dev->lock);
|
||||
dev->dev = get_device(&pdev->dev);
|
||||
dev->irq = irq->start;
|
||||
platform_set_drvdata(pdev, dev);
|
||||
|
||||
dev->clk = clk_get(&pdev->dev, NULL);
|
||||
if (IS_ERR(dev->clk)) {
|
||||
r = -ENODEV;
|
||||
goto err_free_mem;
|
||||
}
|
||||
clk_enable(dev->clk);
|
||||
|
||||
dev->base = ioremap(mem->start, resource_size(mem));
|
||||
if (dev->base == NULL) {
|
||||
dev_err(&pdev->dev, "failure mapping io resources\n");
|
||||
r = -EBUSY;
|
||||
goto err_unuse_clocks;
|
||||
}
|
||||
{
|
||||
u32 param1 = readl(dev->base + DW_IC_COMP_PARAM_1);
|
||||
|
||||
dev->tx_fifo_depth = ((param1 >> 16) & 0xff) + 1;
|
||||
dev->rx_fifo_depth = ((param1 >> 8) & 0xff) + 1;
|
||||
}
|
||||
i2c_dw_init(dev);
|
||||
|
||||
writew(0, dev->base + DW_IC_INTR_MASK); /* disable IRQ */
|
||||
r = request_irq(dev->irq, i2c_dw_isr, 0, pdev->name, dev);
|
||||
if (r) {
|
||||
dev_err(&pdev->dev, "failure requesting irq %i\n", dev->irq);
|
||||
goto err_iounmap;
|
||||
}
|
||||
|
||||
adap = &dev->adapter;
|
||||
i2c_set_adapdata(adap, dev);
|
||||
adap->owner = THIS_MODULE;
|
||||
adap->class = I2C_CLASS_HWMON;
|
||||
strlcpy(adap->name, "Synopsys DesignWare I2C adapter",
|
||||
sizeof(adap->name));
|
||||
adap->algo = &i2c_dw_algo;
|
||||
adap->dev.parent = &pdev->dev;
|
||||
|
||||
adap->nr = pdev->id;
|
||||
r = i2c_add_numbered_adapter(adap);
|
||||
if (r) {
|
||||
dev_err(&pdev->dev, "failure adding adapter\n");
|
||||
goto err_free_irq;
|
||||
}
|
||||
|
||||
return 0;
|
||||
|
||||
err_free_irq:
|
||||
free_irq(dev->irq, dev);
|
||||
err_iounmap:
|
||||
iounmap(dev->base);
|
||||
err_unuse_clocks:
|
||||
clk_disable(dev->clk);
|
||||
clk_put(dev->clk);
|
||||
dev->clk = NULL;
|
||||
err_free_mem:
|
||||
platform_set_drvdata(pdev, NULL);
|
||||
put_device(&pdev->dev);
|
||||
kfree(dev);
|
||||
err_release_region:
|
||||
release_mem_region(mem->start, resource_size(mem));
|
||||
|
||||
return r;
|
||||
}
|
||||
|
||||
static int __devexit dw_i2c_remove(struct platform_device *pdev)
|
||||
{
|
||||
struct dw_i2c_dev *dev = platform_get_drvdata(pdev);
|
||||
struct resource *mem;
|
||||
|
||||
platform_set_drvdata(pdev, NULL);
|
||||
i2c_del_adapter(&dev->adapter);
|
||||
put_device(&pdev->dev);
|
||||
|
||||
clk_disable(dev->clk);
|
||||
clk_put(dev->clk);
|
||||
dev->clk = NULL;
|
||||
|
||||
writeb(0, dev->base + DW_IC_ENABLE);
|
||||
free_irq(dev->irq, dev);
|
||||
kfree(dev);
|
||||
|
||||
mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
|
||||
release_mem_region(mem->start, resource_size(mem));
|
||||
return 0;
|
||||
}
|
||||
|
||||
/* work with hotplug and coldplug */
|
||||
MODULE_ALIAS("platform:i2c_designware");
|
||||
|
||||
static struct platform_driver dw_i2c_driver = {
|
||||
.remove = __devexit_p(dw_i2c_remove),
|
||||
.driver = {
|
||||
.name = "i2c_designware",
|
||||
.owner = THIS_MODULE,
|
||||
},
|
||||
};
|
||||
|
||||
static int __init dw_i2c_init_driver(void)
|
||||
{
|
||||
return platform_driver_probe(&dw_i2c_driver, dw_i2c_probe);
|
||||
}
|
||||
module_init(dw_i2c_init_driver);
|
||||
|
||||
static void __exit dw_i2c_exit_driver(void)
|
||||
{
|
||||
platform_driver_unregister(&dw_i2c_driver);
|
||||
}
|
||||
module_exit(dw_i2c_exit_driver);
|
||||
|
||||
MODULE_AUTHOR("Baruch Siach <baruch@tkos.co.il>");
|
||||
MODULE_DESCRIPTION("Synopsys DesignWare I2C bus adapter");
|
||||
MODULE_LICENSE("GPL");
|
||||
Загрузка…
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