diff --git a/Documentation/devicetree/bindings/interrupt-controller/allwinner,sun4i-ic.txt b/Documentation/devicetree/bindings/interrupt-controller/allwinner,sun4i-ic.txt index 3d3b2b91e333..32cec4b26cd0 100644 --- a/Documentation/devicetree/bindings/interrupt-controller/allwinner,sun4i-ic.txt +++ b/Documentation/devicetree/bindings/interrupt-controller/allwinner,sun4i-ic.txt @@ -14,5 +14,5 @@ intc: interrupt-controller { compatible = "allwinner,sun4i-ic"; reg = <0x01c20400 0x400>; interrupt-controller; - #interrupt-cells = <2>; + #interrupt-cells = <1>; }; diff --git a/arch/arm/mach-sunxi/Kconfig b/arch/arm/mach-sunxi/Kconfig index c9e72c89066a..e3457b94b024 100644 --- a/arch/arm/mach-sunxi/Kconfig +++ b/arch/arm/mach-sunxi/Kconfig @@ -1,5 +1,6 @@ config ARCH_SUNXI bool "Allwinner A1X SOCs" if ARCH_MULTI_V7 + select ARCH_HAS_RESET_CONTROLLER select ARCH_REQUIRE_GPIOLIB select ARM_GIC select CLKSRC_MMIO diff --git a/arch/arm/mach-sunxi/Makefile b/arch/arm/mach-sunxi/Makefile index 93bebfc3ff9f..d9397202d6ec 100644 --- a/arch/arm/mach-sunxi/Makefile +++ b/arch/arm/mach-sunxi/Makefile @@ -1 +1,2 @@ obj-$(CONFIG_ARCH_SUNXI) += sunxi.o +obj-$(CONFIG_SMP) += platsmp.o headsmp.o diff --git a/arch/arm/mach-sunxi/common.h b/arch/arm/mach-sunxi/common.h new file mode 100644 index 000000000000..9e5ac4756cbb --- /dev/null +++ b/arch/arm/mach-sunxi/common.h @@ -0,0 +1,19 @@ +/* + * Core functions for Allwinner SoCs + * + * Copyright (C) 2013 Maxime Ripard + * + * Maxime Ripard + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +#ifndef __ARCH_SUNXI_COMMON_H_ +#define __ARCH_SUNXI_COMMON_H_ + +void sun6i_secondary_startup(void); +extern struct smp_operations sun6i_smp_ops; + +#endif /* __ARCH_SUNXI_COMMON_H_ */ diff --git a/arch/arm/mach-sunxi/headsmp.S b/arch/arm/mach-sunxi/headsmp.S new file mode 100644 index 000000000000..a10d494fb37b --- /dev/null +++ b/arch/arm/mach-sunxi/headsmp.S @@ -0,0 +1,9 @@ +#include +#include + + .section ".text.head", "ax" + +ENTRY(sun6i_secondary_startup) + msr cpsr_fsxc, #0xd3 + b secondary_startup +ENDPROC(sun6i_secondary_startup) diff --git a/arch/arm/mach-sunxi/platsmp.c b/arch/arm/mach-sunxi/platsmp.c new file mode 100644 index 000000000000..7b141d8342a1 --- /dev/null +++ b/arch/arm/mach-sunxi/platsmp.c @@ -0,0 +1,124 @@ +/* + * SMP support for Allwinner SoCs + * + * Copyright (C) 2013 Maxime Ripard + * + * Maxime Ripard + * + * Based on code + * Copyright (C) 2012-2013 Allwinner Ltd. + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +#include +#include +#include +#include +#include +#include +#include + +#include "common.h" + +#define CPUCFG_CPU_PWR_CLAMP_STATUS_REG(cpu) ((cpu) * 0x40 + 0x64) +#define CPUCFG_CPU_RST_CTRL_REG(cpu) (((cpu) + 1) * 0x40) +#define CPUCFG_CPU_CTRL_REG(cpu) (((cpu) + 1) * 0x40 + 0x04) +#define CPUCFG_CPU_STATUS_REG(cpu) (((cpu) + 1) * 0x40 + 0x08) +#define CPUCFG_GEN_CTRL_REG 0x184 +#define CPUCFG_PRIVATE0_REG 0x1a4 +#define CPUCFG_PRIVATE1_REG 0x1a8 +#define CPUCFG_DBG_CTL0_REG 0x1e0 +#define CPUCFG_DBG_CTL1_REG 0x1e4 + +#define PRCM_CPU_PWROFF_REG 0x100 +#define PRCM_CPU_PWR_CLAMP_REG(cpu) (((cpu) * 4) + 0x140) + +static void __iomem *cpucfg_membase; +static void __iomem *prcm_membase; + +static DEFINE_SPINLOCK(cpu_lock); + +static void __init sun6i_smp_prepare_cpus(unsigned int max_cpus) +{ + struct device_node *node; + + node = of_find_compatible_node(NULL, NULL, "allwinner,sun6i-a31-prcm"); + if (!node) { + pr_err("Missing A31 PRCM node in the device tree\n"); + return; + } + + prcm_membase = of_iomap(node, 0); + if (!prcm_membase) { + pr_err("Couldn't map A31 PRCM registers\n"); + return; + } + + node = of_find_compatible_node(NULL, NULL, + "allwinner,sun6i-a31-cpuconfig"); + if (!node) { + pr_err("Missing A31 CPU config node in the device tree\n"); + return; + } + + cpucfg_membase = of_iomap(node, 0); + if (!cpucfg_membase) + pr_err("Couldn't map A31 CPU config registers\n"); + +} + +static int sun6i_smp_boot_secondary(unsigned int cpu, + struct task_struct *idle) +{ + u32 reg; + int i; + + if (!(prcm_membase && cpucfg_membase)) + return -EFAULT; + + spin_lock(&cpu_lock); + + /* Set CPU boot address */ + writel(virt_to_phys(sun6i_secondary_startup), + cpucfg_membase + CPUCFG_PRIVATE0_REG); + + /* Assert the CPU core in reset */ + writel(0, cpucfg_membase + CPUCFG_CPU_RST_CTRL_REG(cpu)); + + /* Assert the L1 cache in reset */ + reg = readl(cpucfg_membase + CPUCFG_GEN_CTRL_REG); + writel(reg & ~BIT(cpu), cpucfg_membase + CPUCFG_GEN_CTRL_REG); + + /* Disable external debug access */ + reg = readl(cpucfg_membase + CPUCFG_DBG_CTL1_REG); + writel(reg & ~BIT(cpu), cpucfg_membase + CPUCFG_DBG_CTL1_REG); + + /* Power up the CPU */ + for (i = 0; i <= 8; i++) + writel(0xff >> i, prcm_membase + PRCM_CPU_PWR_CLAMP_REG(cpu)); + mdelay(10); + + /* Clear CPU power-off gating */ + reg = readl(prcm_membase + PRCM_CPU_PWROFF_REG); + writel(reg & ~BIT(cpu), prcm_membase + PRCM_CPU_PWROFF_REG); + mdelay(1); + + /* Deassert the CPU core reset */ + writel(3, cpucfg_membase + CPUCFG_CPU_RST_CTRL_REG(cpu)); + + /* Enable back the external debug accesses */ + reg = readl(cpucfg_membase + CPUCFG_DBG_CTL1_REG); + writel(reg | BIT(cpu), cpucfg_membase + CPUCFG_DBG_CTL1_REG); + + spin_unlock(&cpu_lock); + + return 0; +} + +struct smp_operations sun6i_smp_ops __initdata = { + .smp_prepare_cpus = sun6i_smp_prepare_cpus, + .smp_boot_secondary = sun6i_smp_boot_secondary, +}; diff --git a/arch/arm/mach-sunxi/sunxi.c b/arch/arm/mach-sunxi/sunxi.c index 61d3a387f01c..aeea6ceea725 100644 --- a/arch/arm/mach-sunxi/sunxi.c +++ b/arch/arm/mach-sunxi/sunxi.c @@ -10,6 +10,8 @@ * warranty of any kind, whether express or implied. */ +#include +#include #include #include #include @@ -23,6 +25,8 @@ #include #include +#include "common.h" + #define SUN4I_WATCHDOG_CTRL_REG 0x00 #define SUN4I_WATCHDOG_CTRL_RESTART BIT(0) #define SUN4I_WATCHDOG_MODE_REG 0x04 @@ -132,10 +136,20 @@ static const char * const sun6i_board_dt_compat[] = { NULL, }; +extern void __init sun6i_reset_init(void); +static void __init sun6i_timer_init(void) +{ + of_clk_init(NULL); + sun6i_reset_init(); + clocksource_of_init(); +} + DT_MACHINE_START(SUN6I_DT, "Allwinner sun6i (A31) Family") .init_machine = sunxi_dt_init, + .init_time = sun6i_timer_init, .dt_compat = sun6i_board_dt_compat, .restart = sun6i_restart, + .smp = smp_ops(sun6i_smp_ops), MACHINE_END static const char * const sun7i_board_dt_compat[] = {