staging: comedi: ni_stc.h: tidy up AO_Command_1_Register and bits
Rename the CamelCase. Use the BIT() macro to define the bits. Signed-off-by: H Hartley Sweeten <hsweeten@visionengravers.com> Reviewed-by: Ian Abbott <abbotti@mev.co.uk> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
This commit is contained in:
H Hartley Sweeten
Greg Kroah-Hartman
Родитель
4c4d715a7d
Коммит
7bfcc2d4cd
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@ -321,7 +321,7 @@ static const struct mio_regmap m_series_stc_write_regmap[] = {
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[NISTC_G0_CMD_REG] = { 0x10c, 2 },
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[NISTC_G1_CMD_REG] = { 0x10e, 2 },
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[NISTC_AI_CMD1_REG] = { 0x110, 2 },
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[AO_Command_1_Register] = { 0x112, 2 },
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[NISTC_AO_CMD1_REG] = { 0x112, 2 },
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/*
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* DIO_Output_Register maps to:
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* { NI_M_DIO_REG, 4 } and { NI_M_SCXI_SER_DO_REG, 1 }
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@ -2906,10 +2906,13 @@ static int ni_ao_inttrig(struct comedi_device *dev,
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ni_set_bits(dev, Interrupt_B_Enable_Register, interrupt_b_bits, 1);
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ni_stc_writew(dev, devpriv->ao_cmd1 |
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AO_UI_Arm | AO_UC_Arm | AO_BC_Arm |
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AO_DAC1_Update_Mode | AO_DAC0_Update_Mode,
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AO_Command_1_Register);
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ni_stc_writew(dev, NISTC_AO_CMD1_UI_ARM |
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NISTC_AO_CMD1_UC_ARM |
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NISTC_AO_CMD1_BC_ARM |
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NISTC_AO_CMD1_DAC1_UPDATE_MODE |
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NISTC_AO_CMD1_DAC0_UPDATE_MODE |
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devpriv->ao_cmd1,
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NISTC_AO_CMD1_REG);
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ni_stc_writew(dev, NISTC_AO_CMD2_START1_PULSE | devpriv->ao_cmd2,
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NISTC_AO_CMD2_REG);
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@ -2933,7 +2936,7 @@ static int ni_ao_cmd(struct comedi_device *dev, struct comedi_subdevice *s)
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ni_stc_writew(dev, AO_Configuration_Start, Joint_Reset_Register);
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ni_stc_writew(dev, AO_Disarm, AO_Command_1_Register);
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ni_stc_writew(dev, NISTC_AO_CMD1_DISARM, NISTC_AO_CMD1_REG);
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if (devpriv->is_6xxx) {
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ni_ao_win_outw(dev, CLEAR_WG, AO_Misc_611x);
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@ -2992,7 +2995,7 @@ static int ni_ao_cmd(struct comedi_device *dev, struct comedi_subdevice *s)
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ni_stc_writel(dev, 0xffffff, AO_BC_Load_A_Register);
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else
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ni_stc_writel(dev, 0, AO_BC_Load_A_Register);
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ni_stc_writew(dev, AO_BC_Load, AO_Command_1_Register);
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ni_stc_writew(dev, NISTC_AO_CMD1_BC_LOAD, NISTC_AO_CMD1_REG);
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devpriv->ao_mode2 &= ~AO_UC_Initial_Load_Source;
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ni_stc_writew(dev, devpriv->ao_mode2, AO_Mode_2_Register);
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switch (cmd->stop_src) {
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@ -3001,23 +3004,25 @@ static int ni_ao_cmd(struct comedi_device *dev, struct comedi_subdevice *s)
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/* this is how the NI example code does it for m-series boards, verified correct with 6259 */
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ni_stc_writel(dev, cmd->stop_arg - 1,
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AO_UC_Load_A_Register);
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ni_stc_writew(dev, AO_UC_Load, AO_Command_1_Register);
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ni_stc_writew(dev, NISTC_AO_CMD1_UC_LOAD,
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NISTC_AO_CMD1_REG);
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} else {
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ni_stc_writel(dev, cmd->stop_arg,
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AO_UC_Load_A_Register);
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ni_stc_writew(dev, AO_UC_Load, AO_Command_1_Register);
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ni_stc_writew(dev, NISTC_AO_CMD1_UC_LOAD,
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NISTC_AO_CMD1_REG);
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ni_stc_writel(dev, cmd->stop_arg - 1,
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AO_UC_Load_A_Register);
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}
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break;
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case TRIG_NONE:
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ni_stc_writel(dev, 0xffffff, AO_UC_Load_A_Register);
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ni_stc_writew(dev, AO_UC_Load, AO_Command_1_Register);
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ni_stc_writew(dev, NISTC_AO_CMD1_UC_LOAD, NISTC_AO_CMD1_REG);
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ni_stc_writel(dev, 0xffffff, AO_UC_Load_A_Register);
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break;
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default:
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ni_stc_writel(dev, 0, AO_UC_Load_A_Register);
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ni_stc_writew(dev, AO_UC_Load, AO_Command_1_Register);
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ni_stc_writew(dev, NISTC_AO_CMD1_UC_LOAD, NISTC_AO_CMD1_REG);
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ni_stc_writel(dev, cmd->stop_arg, AO_UC_Load_A_Register);
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}
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@ -3031,7 +3036,7 @@ static int ni_ao_cmd(struct comedi_device *dev, struct comedi_subdevice *s)
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ni_ns_to_timer(dev, cmd->scan_begin_arg,
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CMDF_ROUND_NEAREST);
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ni_stc_writel(dev, 1, AO_UI_Load_A_Register);
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ni_stc_writew(dev, AO_UI_Load, AO_Command_1_Register);
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ni_stc_writew(dev, NISTC_AO_CMD1_UI_LOAD, NISTC_AO_CMD1_REG);
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ni_stc_writel(dev, trigvar, AO_UI_Load_A_Register);
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break;
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case TRIG_EXT:
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@ -3072,8 +3077,9 @@ static int ni_ao_cmd(struct comedi_device *dev, struct comedi_subdevice *s)
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}
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ni_stc_writew(dev, devpriv->ao_mode1, AO_Mode_1_Register);
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ni_stc_writew(dev, AO_DAC0_Update_Mode | AO_DAC1_Update_Mode,
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AO_Command_1_Register);
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ni_stc_writew(dev, NISTC_AO_CMD1_DAC1_UPDATE_MODE |
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NISTC_AO_CMD1_DAC0_UPDATE_MODE,
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NISTC_AO_CMD1_REG);
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devpriv->ao_mode3 |= AO_Stop_On_Overrun_Error;
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ni_stc_writew(dev, devpriv->ao_mode3, AO_Mode_3_Register);
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@ -3207,7 +3213,7 @@ static int ni_ao_reset(struct comedi_device *dev, struct comedi_subdevice *s)
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ni_release_ao_mite_channel(dev);
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ni_stc_writew(dev, AO_Configuration_Start, Joint_Reset_Register);
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ni_stc_writew(dev, AO_Disarm, AO_Command_1_Register);
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ni_stc_writew(dev, NISTC_AO_CMD1_DISARM, NISTC_AO_CMD1_REG);
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ni_set_bits(dev, Interrupt_B_Enable_Register, ~0, 0);
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ni_stc_writew(dev, AO_BC_Source_Select, AO_Personal_Register);
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ni_stc_writew(dev, NISTC_INTB_ACK_AO_ALL, NISTC_INTB_ACK_REG);
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@ -3216,7 +3222,7 @@ static int ni_ao_reset(struct comedi_device *dev, struct comedi_subdevice *s)
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ni_stc_writew(dev, 0, AO_Output_Control_Register);
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ni_stc_writew(dev, 0, AO_Start_Select_Register);
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devpriv->ao_cmd1 = 0;
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ni_stc_writew(dev, devpriv->ao_cmd1, AO_Command_1_Register);
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ni_stc_writew(dev, devpriv->ao_cmd1, NISTC_AO_CMD1_REG);
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devpriv->ao_cmd2 = 0;
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ni_stc_writew(dev, devpriv->ao_cmd2, NISTC_AO_CMD2_REG);
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devpriv->ao_mode1 = 0;
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@ -146,6 +146,24 @@
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#define NISTC_AI_CMD1_SC_TC_PULSE BIT(1)
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#define NISTC_AI_CMD1_CONVERT_PULSE BIT(0)
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#define NISTC_AO_CMD1_REG 9
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#define NISTC_AO_CMD1_ATRIG_RESET BIT(15)
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#define NISTC_AO_CMD1_START_PULSE BIT(14)
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#define NISTC_AO_CMD1_DISARM BIT(13)
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#define NISTC_AO_CMD1_UI2_ARM_DISARM BIT(12)
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#define NISTC_AO_CMD1_UI2_LOAD BIT(11)
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#define NISTC_AO_CMD1_UI_ARM BIT(10)
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#define NISTC_AO_CMD1_UI_LOAD BIT(9)
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#define NISTC_AO_CMD1_UC_ARM BIT(8)
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#define NISTC_AO_CMD1_UC_LOAD BIT(7)
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#define NISTC_AO_CMD1_BC_ARM BIT(6)
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#define NISTC_AO_CMD1_BC_LOAD BIT(5)
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#define NISTC_AO_CMD1_DAC1_UPDATE_MODE BIT(4)
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#define NISTC_AO_CMD1_LDAC1_SRC_SEL BIT(3)
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#define NISTC_AO_CMD1_DAC0_UPDATE_MODE BIT(2)
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#define NISTC_AO_CMD1_LDAC0_SRC_SEL BIT(1)
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#define NISTC_AO_CMD1_UPDATE_PULSE BIT(0)
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#define AI_Status_1_Register 2
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#define Interrupt_A_St 0x8000
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#define AI_FIFO_Full_St 0x4000
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@ -188,24 +206,6 @@
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#define DIO_Parallel_Input_Register 7
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#define AO_Command_1_Register 9
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#define AO_Analog_Trigger_Reset _bit15
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#define AO_START_Pulse _bit14
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#define AO_Disarm _bit13
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#define AO_UI2_Arm_Disarm _bit12
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#define AO_UI2_Load _bit11
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#define AO_UI_Arm _bit10
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#define AO_UI_Load _bit9
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#define AO_UC_Arm _bit8
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#define AO_UC_Load _bit7
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#define AO_BC_Arm _bit6
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#define AO_BC_Load _bit5
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#define AO_DAC1_Update_Mode _bit4
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#define AO_LDAC1_Source_Select _bit3
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#define AO_DAC0_Update_Mode _bit2
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#define AO_LDAC0_Source_Select _bit1
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#define AO_UPDATE_Pulse _bit0
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#define DIO_Output_Register 10
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#define DIO_Parallel_Data_Out(a) ((a)&0xff)
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#define DIO_Parallel_Data_Mask 0xff
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