Merge branch 'linux-5.6' of git://github.com/skeggsb/linux into drm-fixes
Nothing major here, another TU1xx modesetting fix, and hooking up ACR/GR support on TU11x now that NVIDIA have made the firmware available. Signed-off-by: Dave Airlie <airlied@redhat.com> From: Ben Skeggs <skeggsb@gmail.com> Link: https://patchwork.freedesktop.org/patch/msgid/ <CACAvsv64yBq4KHJ8D-5HQ5eeotApJSMiD+V2ut4f3BonUggf0Q@mail.gmail.com
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Коммит
7c42545cad
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@ -458,6 +458,8 @@ nv50_wndw_atomic_check(struct drm_plane *plane, struct drm_plane_state *state)
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asyw->clr.ntfy = armw->ntfy.handle != 0;
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asyw->clr.sema = armw->sema.handle != 0;
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asyw->clr.xlut = armw->xlut.handle != 0;
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if (asyw->clr.xlut && asyw->visible)
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asyw->set.xlut = asyw->xlut.handle != 0;
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asyw->clr.csc = armw->csc.valid;
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if (wndw->func->image_clr)
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asyw->clr.image = armw->image.handle[0] != 0;
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@ -2579,6 +2579,7 @@ nv166_chipset = {
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static const struct nvkm_device_chip
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nv167_chipset = {
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.name = "TU117",
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.acr = tu102_acr_new,
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.bar = tu102_bar_new,
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.bios = nvkm_bios_new,
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.bus = gf100_bus_new,
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@ -2607,6 +2608,7 @@ nv167_chipset = {
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.disp = tu102_disp_new,
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.dma = gv100_dma_new,
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.fifo = tu102_fifo_new,
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.gr = tu102_gr_new,
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.nvdec[0] = gm107_nvdec_new,
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.nvenc[0] = gm107_nvenc_new,
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.sec2 = tu102_sec2_new,
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@ -2615,6 +2617,7 @@ nv167_chipset = {
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static const struct nvkm_device_chip
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nv168_chipset = {
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.name = "TU116",
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.acr = tu102_acr_new,
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.bar = tu102_bar_new,
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.bios = nvkm_bios_new,
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.bus = gf100_bus_new,
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@ -2643,6 +2646,7 @@ nv168_chipset = {
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.disp = tu102_disp_new,
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.dma = gv100_dma_new,
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.fifo = tu102_fifo_new,
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.gr = tu102_gr_new,
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.nvdec[0] = gm107_nvdec_new,
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.nvenc[0] = gm107_nvenc_new,
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.sec2 = tu102_sec2_new,
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@ -164,6 +164,32 @@ MODULE_FIRMWARE("nvidia/tu106/gr/sw_nonctx.bin");
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MODULE_FIRMWARE("nvidia/tu106/gr/sw_bundle_init.bin");
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MODULE_FIRMWARE("nvidia/tu106/gr/sw_method_init.bin");
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MODULE_FIRMWARE("nvidia/tu117/gr/fecs_bl.bin");
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MODULE_FIRMWARE("nvidia/tu117/gr/fecs_inst.bin");
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MODULE_FIRMWARE("nvidia/tu117/gr/fecs_data.bin");
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MODULE_FIRMWARE("nvidia/tu117/gr/fecs_sig.bin");
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MODULE_FIRMWARE("nvidia/tu117/gr/gpccs_bl.bin");
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MODULE_FIRMWARE("nvidia/tu117/gr/gpccs_inst.bin");
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MODULE_FIRMWARE("nvidia/tu117/gr/gpccs_data.bin");
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MODULE_FIRMWARE("nvidia/tu117/gr/gpccs_sig.bin");
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MODULE_FIRMWARE("nvidia/tu117/gr/sw_ctx.bin");
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MODULE_FIRMWARE("nvidia/tu117/gr/sw_nonctx.bin");
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MODULE_FIRMWARE("nvidia/tu117/gr/sw_bundle_init.bin");
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MODULE_FIRMWARE("nvidia/tu117/gr/sw_method_init.bin");
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MODULE_FIRMWARE("nvidia/tu116/gr/fecs_bl.bin");
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MODULE_FIRMWARE("nvidia/tu116/gr/fecs_inst.bin");
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MODULE_FIRMWARE("nvidia/tu116/gr/fecs_data.bin");
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MODULE_FIRMWARE("nvidia/tu116/gr/fecs_sig.bin");
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MODULE_FIRMWARE("nvidia/tu116/gr/gpccs_bl.bin");
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MODULE_FIRMWARE("nvidia/tu116/gr/gpccs_inst.bin");
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MODULE_FIRMWARE("nvidia/tu116/gr/gpccs_data.bin");
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MODULE_FIRMWARE("nvidia/tu116/gr/gpccs_sig.bin");
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MODULE_FIRMWARE("nvidia/tu116/gr/sw_ctx.bin");
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MODULE_FIRMWARE("nvidia/tu116/gr/sw_nonctx.bin");
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MODULE_FIRMWARE("nvidia/tu116/gr/sw_bundle_init.bin");
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MODULE_FIRMWARE("nvidia/tu116/gr/sw_method_init.bin");
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static const struct gf100_gr_fwif
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tu102_gr_fwif[] = {
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{ 0, gm200_gr_load, &tu102_gr, &gp108_gr_fecs_acr, &gp108_gr_gpccs_acr },
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@ -107,6 +107,12 @@ MODULE_FIRMWARE("nvidia/tu104/acr/ucode_unload.bin");
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MODULE_FIRMWARE("nvidia/tu106/acr/unload_bl.bin");
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MODULE_FIRMWARE("nvidia/tu106/acr/ucode_unload.bin");
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MODULE_FIRMWARE("nvidia/tu116/acr/unload_bl.bin");
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MODULE_FIRMWARE("nvidia/tu116/acr/ucode_unload.bin");
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MODULE_FIRMWARE("nvidia/tu117/acr/unload_bl.bin");
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MODULE_FIRMWARE("nvidia/tu117/acr/ucode_unload.bin");
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static const struct nvkm_acr_hsf_fwif
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tu102_acr_unload_fwif[] = {
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{ 0, nvkm_acr_hsfw_load, &gp108_acr_unload_0 },
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@ -130,6 +136,8 @@ tu102_acr_asb_0 = {
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MODULE_FIRMWARE("nvidia/tu102/acr/ucode_asb.bin");
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MODULE_FIRMWARE("nvidia/tu104/acr/ucode_asb.bin");
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MODULE_FIRMWARE("nvidia/tu106/acr/ucode_asb.bin");
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MODULE_FIRMWARE("nvidia/tu116/acr/ucode_asb.bin");
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MODULE_FIRMWARE("nvidia/tu117/acr/ucode_asb.bin");
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static const struct nvkm_acr_hsf_fwif
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tu102_acr_asb_fwif[] = {
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@ -154,6 +162,12 @@ MODULE_FIRMWARE("nvidia/tu104/acr/ucode_ahesasc.bin");
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MODULE_FIRMWARE("nvidia/tu106/acr/bl.bin");
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MODULE_FIRMWARE("nvidia/tu106/acr/ucode_ahesasc.bin");
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MODULE_FIRMWARE("nvidia/tu116/acr/bl.bin");
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MODULE_FIRMWARE("nvidia/tu116/acr/ucode_ahesasc.bin");
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MODULE_FIRMWARE("nvidia/tu117/acr/bl.bin");
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MODULE_FIRMWARE("nvidia/tu117/acr/ucode_ahesasc.bin");
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static const struct nvkm_acr_hsf_fwif
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tu102_acr_ahesasc_fwif[] = {
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{ 0, nvkm_acr_hsfw_load, &tu102_acr_ahesasc_0 },
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@ -51,3 +51,5 @@ MODULE_FIRMWARE("nvidia/gv100/nvdec/scrubber.bin");
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MODULE_FIRMWARE("nvidia/tu102/nvdec/scrubber.bin");
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MODULE_FIRMWARE("nvidia/tu104/nvdec/scrubber.bin");
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MODULE_FIRMWARE("nvidia/tu106/nvdec/scrubber.bin");
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MODULE_FIRMWARE("nvidia/tu116/nvdec/scrubber.bin");
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MODULE_FIRMWARE("nvidia/tu117/nvdec/scrubber.bin");
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