perf/x86: Add Intel Nehalem and Sandy Bridge-EP uncore support
The uncore subsystem in Sandy Bridge-EP consists of 8 components: Ubox, Cacheing Agent, Home Agent, Memory controller, Power Control, QPI Link Layer, R2PCIe, R3QPI. Signed-off-by: Zheng Yan <zheng.z.yan@intel.com> Signed-off-by: Peter Zijlstra <a.p.zijlstra@chello.nl> Cc: Linus Torvalds <torvalds@linux-foundation.org> Cc: Andrew Morton <akpm@linux-foundation.org> Cc: Thomas Gleixner <tglx@linutronix.de> Link: http://lkml.kernel.org/r/1339741902-8449-9-git-send-email-zheng.z.yan@intel.com Signed-off-by: Ingo Molnar <mingo@kernel.org>
This commit is contained in:
Yan, Zheng
Ingo Molnar
Родитель
14371cce03
Коммит
7c94ee2e09
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@ -21,6 +21,482 @@ DEFINE_UNCORE_FORMAT_ATTR(edge, edge, "config:18");
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DEFINE_UNCORE_FORMAT_ATTR(inv, inv, "config:23");
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DEFINE_UNCORE_FORMAT_ATTR(cmask5, cmask, "config:24-28");
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DEFINE_UNCORE_FORMAT_ATTR(cmask8, cmask, "config:24-31");
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DEFINE_UNCORE_FORMAT_ATTR(thresh8, thresh, "config:24-31");
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DEFINE_UNCORE_FORMAT_ATTR(thresh5, thresh, "config:24-28");
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DEFINE_UNCORE_FORMAT_ATTR(occ_sel, occ_sel, "config:14-15");
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DEFINE_UNCORE_FORMAT_ATTR(occ_invert, occ_invert, "config:30");
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DEFINE_UNCORE_FORMAT_ATTR(occ_edge, occ_edge, "config:14-51");
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/* Sandy Bridge-EP uncore support */
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static void snbep_uncore_pci_disable_box(struct intel_uncore_box *box)
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{
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struct pci_dev *pdev = box->pci_dev;
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int box_ctl = uncore_pci_box_ctl(box);
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u32 config;
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pci_read_config_dword(pdev, box_ctl, &config);
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config |= SNBEP_PMON_BOX_CTL_FRZ;
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pci_write_config_dword(pdev, box_ctl, config);
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}
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static void snbep_uncore_pci_enable_box(struct intel_uncore_box *box)
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{
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struct pci_dev *pdev = box->pci_dev;
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int box_ctl = uncore_pci_box_ctl(box);
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u32 config;
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pci_read_config_dword(pdev, box_ctl, &config);
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config &= ~SNBEP_PMON_BOX_CTL_FRZ;
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pci_write_config_dword(pdev, box_ctl, config);
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}
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static void snbep_uncore_pci_enable_event(struct intel_uncore_box *box,
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struct perf_event *event)
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{
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struct pci_dev *pdev = box->pci_dev;
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struct hw_perf_event *hwc = &event->hw;
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pci_write_config_dword(pdev, hwc->config_base, hwc->config |
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SNBEP_PMON_CTL_EN);
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}
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static void snbep_uncore_pci_disable_event(struct intel_uncore_box *box,
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struct perf_event *event)
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{
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struct pci_dev *pdev = box->pci_dev;
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struct hw_perf_event *hwc = &event->hw;
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pci_write_config_dword(pdev, hwc->config_base, hwc->config);
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}
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static u64 snbep_uncore_pci_read_counter(struct intel_uncore_box *box,
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struct perf_event *event)
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{
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struct pci_dev *pdev = box->pci_dev;
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struct hw_perf_event *hwc = &event->hw;
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u64 count;
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pci_read_config_dword(pdev, hwc->event_base, (u32 *)&count);
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pci_read_config_dword(pdev, hwc->event_base + 4, (u32 *)&count + 1);
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return count;
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}
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static void snbep_uncore_pci_init_box(struct intel_uncore_box *box)
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{
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struct pci_dev *pdev = box->pci_dev;
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pci_write_config_dword(pdev, SNBEP_PCI_PMON_BOX_CTL,
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SNBEP_PMON_BOX_CTL_INT);
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}
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static void snbep_uncore_msr_disable_box(struct intel_uncore_box *box)
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{
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u64 config;
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unsigned msr;
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msr = uncore_msr_box_ctl(box);
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if (msr) {
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rdmsrl(msr, config);
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config |= SNBEP_PMON_BOX_CTL_FRZ;
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wrmsrl(msr, config);
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return;
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}
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}
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static void snbep_uncore_msr_enable_box(struct intel_uncore_box *box)
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{
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u64 config;
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unsigned msr;
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msr = uncore_msr_box_ctl(box);
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if (msr) {
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rdmsrl(msr, config);
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config &= ~SNBEP_PMON_BOX_CTL_FRZ;
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wrmsrl(msr, config);
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return;
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}
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}
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static void snbep_uncore_msr_enable_event(struct intel_uncore_box *box,
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struct perf_event *event)
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{
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struct hw_perf_event *hwc = &event->hw;
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wrmsrl(hwc->config_base, hwc->config | SNBEP_PMON_CTL_EN);
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}
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static void snbep_uncore_msr_disable_event(struct intel_uncore_box *box,
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struct perf_event *event)
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{
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struct hw_perf_event *hwc = &event->hw;
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wrmsrl(hwc->config_base, hwc->config);
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}
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static u64 snbep_uncore_msr_read_counter(struct intel_uncore_box *box,
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struct perf_event *event)
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{
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struct hw_perf_event *hwc = &event->hw;
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u64 count;
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rdmsrl(hwc->event_base, count);
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return count;
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}
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static void snbep_uncore_msr_init_box(struct intel_uncore_box *box)
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{
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unsigned msr = uncore_msr_box_ctl(box);
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if (msr)
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wrmsrl(msr, SNBEP_PMON_BOX_CTL_INT);
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}
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static struct attribute *snbep_uncore_formats_attr[] = {
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&format_attr_event.attr,
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&format_attr_umask.attr,
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&format_attr_edge.attr,
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&format_attr_inv.attr,
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&format_attr_thresh8.attr,
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NULL,
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};
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static struct attribute *snbep_uncore_ubox_formats_attr[] = {
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&format_attr_event.attr,
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&format_attr_umask.attr,
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&format_attr_edge.attr,
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&format_attr_inv.attr,
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&format_attr_thresh5.attr,
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NULL,
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};
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static struct attribute *snbep_uncore_pcu_formats_attr[] = {
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&format_attr_event.attr,
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&format_attr_occ_sel.attr,
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&format_attr_edge.attr,
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&format_attr_inv.attr,
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&format_attr_thresh5.attr,
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&format_attr_occ_invert.attr,
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&format_attr_occ_edge.attr,
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NULL,
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};
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static struct uncore_event_desc snbep_uncore_imc_events[] = {
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INTEL_UNCORE_EVENT_DESC(CLOCKTICKS, "config=0xffff"),
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/* read */
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INTEL_UNCORE_EVENT_DESC(CAS_COUNT_RD, "event=0x4,umask=0x3"),
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/* write */
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INTEL_UNCORE_EVENT_DESC(CAS_COUNT_WR, "event=0x4,umask=0xc"),
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{ /* end: all zeroes */ },
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};
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static struct uncore_event_desc snbep_uncore_qpi_events[] = {
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INTEL_UNCORE_EVENT_DESC(CLOCKTICKS, "event=0x14"),
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/* outgoing data+nondata flits */
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INTEL_UNCORE_EVENT_DESC(TxL_FLITS_ACTIVE, "event=0x0,umask=0x6"),
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/* DRS data received */
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INTEL_UNCORE_EVENT_DESC(DRS_DATA, "event=0x2,umask=0x8"),
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/* NCB data received */
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INTEL_UNCORE_EVENT_DESC(NCB_DATA, "event=0x3,umask=0x4"),
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{ /* end: all zeroes */ },
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};
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static struct attribute_group snbep_uncore_format_group = {
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.name = "format",
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.attrs = snbep_uncore_formats_attr,
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};
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static struct attribute_group snbep_uncore_ubox_format_group = {
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.name = "format",
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.attrs = snbep_uncore_ubox_formats_attr,
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};
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static struct attribute_group snbep_uncore_pcu_format_group = {
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.name = "format",
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.attrs = snbep_uncore_pcu_formats_attr,
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};
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static struct intel_uncore_ops snbep_uncore_msr_ops = {
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.init_box = snbep_uncore_msr_init_box,
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.disable_box = snbep_uncore_msr_disable_box,
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.enable_box = snbep_uncore_msr_enable_box,
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.disable_event = snbep_uncore_msr_disable_event,
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.enable_event = snbep_uncore_msr_enable_event,
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.read_counter = snbep_uncore_msr_read_counter,
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};
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static struct intel_uncore_ops snbep_uncore_pci_ops = {
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.init_box = snbep_uncore_pci_init_box,
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.disable_box = snbep_uncore_pci_disable_box,
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.enable_box = snbep_uncore_pci_enable_box,
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.disable_event = snbep_uncore_pci_disable_event,
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.enable_event = snbep_uncore_pci_enable_event,
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.read_counter = snbep_uncore_pci_read_counter,
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};
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static struct event_constraint snbep_uncore_cbox_constraints[] = {
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UNCORE_EVENT_CONSTRAINT(0x01, 0x1),
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UNCORE_EVENT_CONSTRAINT(0x02, 0x3),
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UNCORE_EVENT_CONSTRAINT(0x04, 0x3),
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UNCORE_EVENT_CONSTRAINT(0x05, 0x3),
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UNCORE_EVENT_CONSTRAINT(0x07, 0x3),
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UNCORE_EVENT_CONSTRAINT(0x11, 0x1),
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UNCORE_EVENT_CONSTRAINT(0x12, 0x3),
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UNCORE_EVENT_CONSTRAINT(0x13, 0x3),
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UNCORE_EVENT_CONSTRAINT(0x1b, 0xc),
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UNCORE_EVENT_CONSTRAINT(0x1c, 0xc),
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UNCORE_EVENT_CONSTRAINT(0x1d, 0xc),
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UNCORE_EVENT_CONSTRAINT(0x1e, 0xc),
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UNCORE_EVENT_CONSTRAINT(0x1f, 0xe),
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UNCORE_EVENT_CONSTRAINT(0x21, 0x3),
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UNCORE_EVENT_CONSTRAINT(0x23, 0x3),
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UNCORE_EVENT_CONSTRAINT(0x31, 0x3),
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UNCORE_EVENT_CONSTRAINT(0x32, 0x3),
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UNCORE_EVENT_CONSTRAINT(0x33, 0x3),
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UNCORE_EVENT_CONSTRAINT(0x34, 0x3),
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UNCORE_EVENT_CONSTRAINT(0x35, 0x3),
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UNCORE_EVENT_CONSTRAINT(0x36, 0x1),
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UNCORE_EVENT_CONSTRAINT(0x37, 0x3),
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UNCORE_EVENT_CONSTRAINT(0x38, 0x3),
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UNCORE_EVENT_CONSTRAINT(0x39, 0x3),
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UNCORE_EVENT_CONSTRAINT(0x3b, 0x1),
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EVENT_CONSTRAINT_END
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};
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static struct event_constraint snbep_uncore_r2pcie_constraints[] = {
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UNCORE_EVENT_CONSTRAINT(0x10, 0x3),
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UNCORE_EVENT_CONSTRAINT(0x11, 0x3),
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UNCORE_EVENT_CONSTRAINT(0x12, 0x1),
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UNCORE_EVENT_CONSTRAINT(0x23, 0x3),
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UNCORE_EVENT_CONSTRAINT(0x24, 0x3),
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UNCORE_EVENT_CONSTRAINT(0x25, 0x3),
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UNCORE_EVENT_CONSTRAINT(0x26, 0x3),
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UNCORE_EVENT_CONSTRAINT(0x32, 0x3),
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UNCORE_EVENT_CONSTRAINT(0x33, 0x3),
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UNCORE_EVENT_CONSTRAINT(0x34, 0x3),
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EVENT_CONSTRAINT_END
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};
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static struct event_constraint snbep_uncore_r3qpi_constraints[] = {
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UNCORE_EVENT_CONSTRAINT(0x10, 0x3),
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UNCORE_EVENT_CONSTRAINT(0x11, 0x3),
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UNCORE_EVENT_CONSTRAINT(0x12, 0x3),
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UNCORE_EVENT_CONSTRAINT(0x13, 0x1),
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UNCORE_EVENT_CONSTRAINT(0x20, 0x3),
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UNCORE_EVENT_CONSTRAINT(0x21, 0x3),
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UNCORE_EVENT_CONSTRAINT(0x22, 0x3),
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UNCORE_EVENT_CONSTRAINT(0x23, 0x3),
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UNCORE_EVENT_CONSTRAINT(0x24, 0x3),
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UNCORE_EVENT_CONSTRAINT(0x25, 0x3),
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UNCORE_EVENT_CONSTRAINT(0x26, 0x3),
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UNCORE_EVENT_CONSTRAINT(0x30, 0x3),
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UNCORE_EVENT_CONSTRAINT(0x31, 0x3),
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UNCORE_EVENT_CONSTRAINT(0x32, 0x3),
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UNCORE_EVENT_CONSTRAINT(0x33, 0x3),
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UNCORE_EVENT_CONSTRAINT(0x34, 0x3),
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UNCORE_EVENT_CONSTRAINT(0x36, 0x3),
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UNCORE_EVENT_CONSTRAINT(0x37, 0x3),
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EVENT_CONSTRAINT_END
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};
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static struct intel_uncore_type snbep_uncore_ubox = {
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.name = "ubox",
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.num_counters = 2,
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.num_boxes = 1,
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.perf_ctr_bits = 44,
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.fixed_ctr_bits = 48,
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.perf_ctr = SNBEP_U_MSR_PMON_CTR0,
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.event_ctl = SNBEP_U_MSR_PMON_CTL0,
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.event_mask = SNBEP_U_MSR_PMON_RAW_EVENT_MASK,
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.fixed_ctr = SNBEP_U_MSR_PMON_UCLK_FIXED_CTR,
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.fixed_ctl = SNBEP_U_MSR_PMON_UCLK_FIXED_CTL,
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.ops = &snbep_uncore_msr_ops,
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.format_group = &snbep_uncore_ubox_format_group,
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};
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static struct intel_uncore_type snbep_uncore_cbox = {
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.name = "cbox",
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.num_counters = 4,
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.num_boxes = 8,
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.perf_ctr_bits = 44,
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.event_ctl = SNBEP_C0_MSR_PMON_CTL0,
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.perf_ctr = SNBEP_C0_MSR_PMON_CTR0,
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.event_mask = SNBEP_PMON_RAW_EVENT_MASK,
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.box_ctl = SNBEP_C0_MSR_PMON_BOX_CTL,
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.msr_offset = SNBEP_CBO_MSR_OFFSET,
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.constraints = snbep_uncore_cbox_constraints,
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.ops = &snbep_uncore_msr_ops,
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.format_group = &snbep_uncore_format_group,
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};
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static struct intel_uncore_type snbep_uncore_pcu = {
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.name = "pcu",
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.num_counters = 4,
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.num_boxes = 1,
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.perf_ctr_bits = 48,
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.perf_ctr = SNBEP_PCU_MSR_PMON_CTR0,
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.event_ctl = SNBEP_PCU_MSR_PMON_CTL0,
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.event_mask = SNBEP_PCU_MSR_PMON_RAW_EVENT_MASK,
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.box_ctl = SNBEP_PCU_MSR_PMON_BOX_CTL,
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.ops = &snbep_uncore_msr_ops,
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.format_group = &snbep_uncore_pcu_format_group,
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};
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static struct intel_uncore_type *snbep_msr_uncores[] = {
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&snbep_uncore_ubox,
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&snbep_uncore_cbox,
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&snbep_uncore_pcu,
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NULL,
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};
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#define SNBEP_UNCORE_PCI_COMMON_INIT() \
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.perf_ctr = SNBEP_PCI_PMON_CTR0, \
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.event_ctl = SNBEP_PCI_PMON_CTL0, \
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.event_mask = SNBEP_PMON_RAW_EVENT_MASK, \
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.box_ctl = SNBEP_PCI_PMON_BOX_CTL, \
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.ops = &snbep_uncore_pci_ops, \
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.format_group = &snbep_uncore_format_group
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static struct intel_uncore_type snbep_uncore_ha = {
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.name = "ha",
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.num_counters = 4,
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.num_boxes = 1,
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.perf_ctr_bits = 48,
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SNBEP_UNCORE_PCI_COMMON_INIT(),
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};
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static struct intel_uncore_type snbep_uncore_imc = {
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.name = "imc",
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.num_counters = 4,
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.num_boxes = 4,
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.perf_ctr_bits = 48,
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.fixed_ctr_bits = 48,
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.fixed_ctr = SNBEP_MC_CHy_PCI_PMON_FIXED_CTR,
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.fixed_ctl = SNBEP_MC_CHy_PCI_PMON_FIXED_CTL,
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.event_descs = snbep_uncore_imc_events,
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SNBEP_UNCORE_PCI_COMMON_INIT(),
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};
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static struct intel_uncore_type snbep_uncore_qpi = {
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.name = "qpi",
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.num_counters = 4,
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.num_boxes = 2,
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.perf_ctr_bits = 48,
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.event_descs = snbep_uncore_qpi_events,
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SNBEP_UNCORE_PCI_COMMON_INIT(),
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};
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static struct intel_uncore_type snbep_uncore_r2pcie = {
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.name = "r2pcie",
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.num_counters = 4,
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.num_boxes = 1,
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.perf_ctr_bits = 44,
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.constraints = snbep_uncore_r2pcie_constraints,
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SNBEP_UNCORE_PCI_COMMON_INIT(),
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};
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static struct intel_uncore_type snbep_uncore_r3qpi = {
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.name = "r3qpi",
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.num_counters = 3,
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.num_boxes = 2,
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.perf_ctr_bits = 44,
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.constraints = snbep_uncore_r3qpi_constraints,
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SNBEP_UNCORE_PCI_COMMON_INIT(),
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};
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static struct intel_uncore_type *snbep_pci_uncores[] = {
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&snbep_uncore_ha,
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&snbep_uncore_imc,
|
||||
&snbep_uncore_qpi,
|
||||
&snbep_uncore_r2pcie,
|
||||
&snbep_uncore_r3qpi,
|
||||
NULL,
|
||||
};
|
||||
|
||||
static DEFINE_PCI_DEVICE_TABLE(snbep_uncore_pci_ids) = {
|
||||
{ /* Home Agent */
|
||||
PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_UNC_HA),
|
||||
.driver_data = (unsigned long)&snbep_uncore_ha,
|
||||
},
|
||||
{ /* MC Channel 0 */
|
||||
PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_UNC_IMC0),
|
||||
.driver_data = (unsigned long)&snbep_uncore_imc,
|
||||
},
|
||||
{ /* MC Channel 1 */
|
||||
PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_UNC_IMC1),
|
||||
.driver_data = (unsigned long)&snbep_uncore_imc,
|
||||
},
|
||||
{ /* MC Channel 2 */
|
||||
PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_UNC_IMC2),
|
||||
.driver_data = (unsigned long)&snbep_uncore_imc,
|
||||
},
|
||||
{ /* MC Channel 3 */
|
||||
PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_UNC_IMC3),
|
||||
.driver_data = (unsigned long)&snbep_uncore_imc,
|
||||
},
|
||||
{ /* QPI Port 0 */
|
||||
PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_UNC_QPI0),
|
||||
.driver_data = (unsigned long)&snbep_uncore_qpi,
|
||||
},
|
||||
{ /* QPI Port 1 */
|
||||
PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_UNC_QPI1),
|
||||
.driver_data = (unsigned long)&snbep_uncore_qpi,
|
||||
},
|
||||
{ /* P2PCIe */
|
||||
PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_UNC_R2PCIE),
|
||||
.driver_data = (unsigned long)&snbep_uncore_r2pcie,
|
||||
},
|
||||
{ /* R3QPI Link 0 */
|
||||
PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_UNC_R3QPI0),
|
||||
.driver_data = (unsigned long)&snbep_uncore_r3qpi,
|
||||
},
|
||||
{ /* R3QPI Link 1 */
|
||||
PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_UNC_R3QPI1),
|
||||
.driver_data = (unsigned long)&snbep_uncore_r3qpi,
|
||||
},
|
||||
{ /* end: all zeroes */ }
|
||||
};
|
||||
|
||||
static struct pci_driver snbep_uncore_pci_driver = {
|
||||
.name = "snbep_uncore",
|
||||
.id_table = snbep_uncore_pci_ids,
|
||||
};
|
||||
|
||||
/*
|
||||
* build pci bus to socket mapping
|
||||
*/
|
||||
static void snbep_pci2phy_map_init(void)
|
||||
{
|
||||
struct pci_dev *ubox_dev = NULL;
|
||||
int i, bus, nodeid;
|
||||
u32 config;
|
||||
|
||||
while (1) {
|
||||
/* find the UBOX device */
|
||||
ubox_dev = pci_get_device(PCI_VENDOR_ID_INTEL,
|
||||
PCI_DEVICE_ID_INTEL_JAKETOWN_UBOX,
|
||||
ubox_dev);
|
||||
if (!ubox_dev)
|
||||
break;
|
||||
bus = ubox_dev->bus->number;
|
||||
/* get the Node ID of the local register */
|
||||
pci_read_config_dword(ubox_dev, 0x40, &config);
|
||||
nodeid = config;
|
||||
/* get the Node ID mapping */
|
||||
pci_read_config_dword(ubox_dev, 0x54, &config);
|
||||
/*
|
||||
* every three bits in the Node ID mapping register maps
|
||||
* to a particular node.
|
||||
*/
|
||||
for (i = 0; i < 8; i++) {
|
||||
if (nodeid == ((config >> (3 * i)) & 0x7)) {
|
||||
pcibus_to_physid[bus] = i;
|
||||
break;
|
||||
}
|
||||
}
|
||||
};
|
||||
return;
|
||||
}
|
||||
/* end of Sandy Bridge-EP uncore support */
|
||||
|
||||
|
||||
/* Sandy Bridge uncore support */
|
||||
static void snb_uncore_msr_enable_event(struct intel_uncore_box *box,
|
||||
|
|
@ -894,6 +1370,11 @@ static int __init uncore_pci_init(void)
|
|||
int ret;
|
||||
|
||||
switch (boot_cpu_data.x86_model) {
|
||||
case 45: /* Sandy Bridge-EP */
|
||||
pci_uncores = snbep_pci_uncores;
|
||||
uncore_pci_driver = &snbep_uncore_pci_driver;
|
||||
snbep_pci2phy_map_init();
|
||||
break;
|
||||
default:
|
||||
return 0;
|
||||
}
|
||||
|
|
@ -1155,6 +1636,9 @@ static int __init uncore_cpu_init(void)
|
|||
case 42: /* Sandy Bridge */
|
||||
msr_uncores = snb_msr_uncores;
|
||||
break;
|
||||
case 45: /* Sandy Birdge-EP */
|
||||
msr_uncores = snbep_msr_uncores;
|
||||
break;
|
||||
default:
|
||||
return 0;
|
||||
}
|
||||
|
|
|
|||
|
|
@ -65,6 +65,92 @@
|
|||
#define NHM_UNC_PERFEVTSEL0 0x3c0
|
||||
#define NHM_UNC_UNCORE_PMC0 0x3b0
|
||||
|
||||
/* SNB-EP Box level control */
|
||||
#define SNBEP_PMON_BOX_CTL_RST_CTRL (1 << 0)
|
||||
#define SNBEP_PMON_BOX_CTL_RST_CTRS (1 << 1)
|
||||
#define SNBEP_PMON_BOX_CTL_FRZ (1 << 8)
|
||||
#define SNBEP_PMON_BOX_CTL_FRZ_EN (1 << 16)
|
||||
#define SNBEP_PMON_BOX_CTL_INT (SNBEP_PMON_BOX_CTL_RST_CTRL | \
|
||||
SNBEP_PMON_BOX_CTL_RST_CTRS | \
|
||||
SNBEP_PMON_BOX_CTL_FRZ_EN)
|
||||
/* SNB-EP event control */
|
||||
#define SNBEP_PMON_CTL_EV_SEL_MASK 0x000000ff
|
||||
#define SNBEP_PMON_CTL_UMASK_MASK 0x0000ff00
|
||||
#define SNBEP_PMON_CTL_RST (1 << 17)
|
||||
#define SNBEP_PMON_CTL_EDGE_DET (1 << 18)
|
||||
#define SNBEP_PMON_CTL_EV_SEL_EXT (1 << 21) /* only for QPI */
|
||||
#define SNBEP_PMON_CTL_EN (1 << 22)
|
||||
#define SNBEP_PMON_CTL_INVERT (1 << 23)
|
||||
#define SNBEP_PMON_CTL_TRESH_MASK 0xff000000
|
||||
#define SNBEP_PMON_RAW_EVENT_MASK (SNBEP_PMON_CTL_EV_SEL_MASK | \
|
||||
SNBEP_PMON_CTL_UMASK_MASK | \
|
||||
SNBEP_PMON_CTL_EDGE_DET | \
|
||||
SNBEP_PMON_CTL_INVERT | \
|
||||
SNBEP_PMON_CTL_TRESH_MASK)
|
||||
|
||||
/* SNB-EP Ubox event control */
|
||||
#define SNBEP_U_MSR_PMON_CTL_TRESH_MASK 0x1f000000
|
||||
#define SNBEP_U_MSR_PMON_RAW_EVENT_MASK \
|
||||
(SNBEP_PMON_CTL_EV_SEL_MASK | \
|
||||
SNBEP_PMON_CTL_UMASK_MASK | \
|
||||
SNBEP_PMON_CTL_EDGE_DET | \
|
||||
SNBEP_PMON_CTL_INVERT | \
|
||||
SNBEP_U_MSR_PMON_CTL_TRESH_MASK)
|
||||
|
||||
/* SNB-EP PCU event control */
|
||||
#define SNBEP_PCU_MSR_PMON_CTL_OCC_SEL_MASK 0x0000c000
|
||||
#define SNBEP_PCU_MSR_PMON_CTL_TRESH_MASK 0x1f000000
|
||||
#define SNBEP_PCU_MSR_PMON_CTL_OCC_INVERT (1 << 30)
|
||||
#define SNBEP_PCU_MSR_PMON_CTL_OCC_EDGE_DET (1 << 31)
|
||||
#define SNBEP_PCU_MSR_PMON_RAW_EVENT_MASK \
|
||||
(SNBEP_PMON_CTL_EV_SEL_MASK | \
|
||||
SNBEP_PCU_MSR_PMON_CTL_OCC_SEL_MASK | \
|
||||
SNBEP_PMON_CTL_EDGE_DET | \
|
||||
SNBEP_PMON_CTL_INVERT | \
|
||||
SNBEP_PCU_MSR_PMON_CTL_TRESH_MASK | \
|
||||
SNBEP_PCU_MSR_PMON_CTL_OCC_INVERT | \
|
||||
SNBEP_PCU_MSR_PMON_CTL_OCC_EDGE_DET)
|
||||
|
||||
/* SNB-EP pci control register */
|
||||
#define SNBEP_PCI_PMON_BOX_CTL 0xf4
|
||||
#define SNBEP_PCI_PMON_CTL0 0xd8
|
||||
/* SNB-EP pci counter register */
|
||||
#define SNBEP_PCI_PMON_CTR0 0xa0
|
||||
|
||||
/* SNB-EP home agent register */
|
||||
#define SNBEP_HA_PCI_PMON_BOX_ADDRMATCH0 0x40
|
||||
#define SNBEP_HA_PCI_PMON_BOX_ADDRMATCH1 0x44
|
||||
#define SNBEP_HA_PCI_PMON_BOX_OPCODEMATCH 0x48
|
||||
/* SNB-EP memory controller register */
|
||||
#define SNBEP_MC_CHy_PCI_PMON_FIXED_CTL 0xf0
|
||||
#define SNBEP_MC_CHy_PCI_PMON_FIXED_CTR 0xd0
|
||||
/* SNB-EP QPI register */
|
||||
#define SNBEP_Q_Py_PCI_PMON_PKT_MATCH0 0x228
|
||||
#define SNBEP_Q_Py_PCI_PMON_PKT_MATCH1 0x22c
|
||||
#define SNBEP_Q_Py_PCI_PMON_PKT_MASK0 0x238
|
||||
#define SNBEP_Q_Py_PCI_PMON_PKT_MASK1 0x23c
|
||||
|
||||
/* SNB-EP Ubox register */
|
||||
#define SNBEP_U_MSR_PMON_CTR0 0xc16
|
||||
#define SNBEP_U_MSR_PMON_CTL0 0xc10
|
||||
|
||||
#define SNBEP_U_MSR_PMON_UCLK_FIXED_CTL 0xc08
|
||||
#define SNBEP_U_MSR_PMON_UCLK_FIXED_CTR 0xc09
|
||||
|
||||
/* SNB-EP Cbo register */
|
||||
#define SNBEP_C0_MSR_PMON_CTR0 0xd16
|
||||
#define SNBEP_C0_MSR_PMON_CTL0 0xd10
|
||||
#define SNBEP_C0_MSR_PMON_BOX_FILTER 0xd14
|
||||
#define SNBEP_C0_MSR_PMON_BOX_CTL 0xd04
|
||||
#define SNBEP_CBO_MSR_OFFSET 0x20
|
||||
|
||||
/* SNB-EP PCU register */
|
||||
#define SNBEP_PCU_MSR_PMON_CTR0 0xc36
|
||||
#define SNBEP_PCU_MSR_PMON_CTL0 0xc30
|
||||
#define SNBEP_PCU_MSR_PMON_BOX_FILTER 0xc34
|
||||
#define SNBEP_PCU_MSR_PMON_BOX_CTL 0xc24
|
||||
#define SNBEP_PCU_MSR_CORE_C3_CTR 0x3fc
|
||||
#define SNBEP_PCU_MSR_CORE_C6_CTR 0x3fd
|
||||
|
||||
struct intel_uncore_ops;
|
||||
struct intel_uncore_pmu;
|
||||
|
|
|
|||
|
|
@ -2755,6 +2755,17 @@
|
|||
#define PCI_DEVICE_ID_INTEL_IOAT_SNB7 0x3c27
|
||||
#define PCI_DEVICE_ID_INTEL_IOAT_SNB8 0x3c2e
|
||||
#define PCI_DEVICE_ID_INTEL_IOAT_SNB9 0x3c2f
|
||||
#define PCI_DEVICE_ID_INTEL_UNC_HA 0x3c46
|
||||
#define PCI_DEVICE_ID_INTEL_UNC_IMC0 0x3cb0
|
||||
#define PCI_DEVICE_ID_INTEL_UNC_IMC1 0x3cb1
|
||||
#define PCI_DEVICE_ID_INTEL_UNC_IMC2 0x3cb4
|
||||
#define PCI_DEVICE_ID_INTEL_UNC_IMC3 0x3cb5
|
||||
#define PCI_DEVICE_ID_INTEL_UNC_QPI0 0x3c41
|
||||
#define PCI_DEVICE_ID_INTEL_UNC_QPI1 0x3c42
|
||||
#define PCI_DEVICE_ID_INTEL_UNC_R2PCIE 0x3c43
|
||||
#define PCI_DEVICE_ID_INTEL_UNC_R3QPI0 0x3c44
|
||||
#define PCI_DEVICE_ID_INTEL_UNC_R3QPI1 0x3c45
|
||||
#define PCI_DEVICE_ID_INTEL_JAKETOWN_UBOX 0x3ce0
|
||||
#define PCI_DEVICE_ID_INTEL_IOAT_SNB 0x402f
|
||||
#define PCI_DEVICE_ID_INTEL_5100_16 0x65f0
|
||||
#define PCI_DEVICE_ID_INTEL_5100_21 0x65f5
|
||||
|
|
|
|||
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