thermal: exynos: Support thermal tripping
TMU urgently sends active-high signal (thermal trip) to PMU, and thermal tripping by hardware logic. Thermal tripping means that PMU cuts off the whole power of SoC by controlling external voltage regulator. Acked-by: Kukjin Kim <kgene.kim@samsung.com> Acked-by: Jonghwa Lee <jonghwa3.lee@samsung.com> Acked-by: Eduardo Valentin <eduardo.valentin@ti.com> Signed-off-by: Jonghwan Choi <jhbird.choi@samsung.com> Signed-off-by: Amit Daniel Kachhap <amit.daniel@samsung.com> Signed-off-by: Eduardo Valentin <eduardo.valentin@ti.com>
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@ -117,7 +117,7 @@ static int exynos_tmu_initialize(struct platform_device *pdev)
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struct exynos_tmu_data *data = platform_get_drvdata(pdev);
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struct exynos_tmu_platform_data *pdata = data->pdata;
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const struct exynos_tmu_registers *reg = pdata->registers;
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unsigned int status, trim_info;
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unsigned int status, trim_info = 0, con;
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unsigned int rising_threshold = 0, falling_threshold = 0;
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int ret = 0, threshold_code, i, trigger_levs = 0;
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@ -144,10 +144,26 @@ static int exynos_tmu_initialize(struct platform_device *pdev)
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(data->temp_error2 != 0))
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data->temp_error1 = pdata->efuse_value;
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/* Count trigger levels to be enabled */
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for (i = 0; i < MAX_THRESHOLD_LEVS; i++)
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if (pdata->trigger_levels[i])
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if (pdata->max_trigger_level > MAX_THRESHOLD_LEVS) {
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dev_err(&pdev->dev, "Invalid max trigger level\n");
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goto out;
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}
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for (i = 0; i < pdata->max_trigger_level; i++) {
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if (!pdata->trigger_levels[i])
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continue;
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if ((pdata->trigger_type[i] == HW_TRIP) &&
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(!pdata->trigger_levels[pdata->max_trigger_level - 1])) {
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dev_err(&pdev->dev, "Invalid hw trigger level\n");
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ret = -EINVAL;
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goto out;
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}
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/* Count trigger levels except the HW trip*/
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if (!(pdata->trigger_type[i] == HW_TRIP))
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trigger_levs++;
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}
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if (data->soc == SOC_ARCH_EXYNOS4210) {
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/* Write temperature code for threshold */
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@ -165,7 +181,8 @@ static int exynos_tmu_initialize(struct platform_device *pdev)
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writel(reg->inten_rise_mask, data->base + reg->tmu_intclear);
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} else if (data->soc == SOC_ARCH_EXYNOS) {
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/* Write temperature code for rising and falling threshold */
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for (i = 0; i < trigger_levs; i++) {
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for (i = 0;
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i < trigger_levs && i < EXYNOS_MAX_TRIGGER_PER_REG; i++) {
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threshold_code = temp_to_code(data,
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pdata->trigger_levels[i]);
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if (threshold_code < 0) {
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@ -191,6 +208,24 @@ static int exynos_tmu_initialize(struct platform_device *pdev)
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writel((reg->inten_rise_mask << reg->inten_rise_shift) |
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(reg->inten_fall_mask << reg->inten_fall_shift),
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data->base + reg->tmu_intclear);
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/* if last threshold limit is also present */
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i = pdata->max_trigger_level - 1;
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if (pdata->trigger_levels[i] &&
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(pdata->trigger_type[i] == HW_TRIP)) {
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threshold_code = temp_to_code(data,
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pdata->trigger_levels[i]);
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if (threshold_code < 0) {
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ret = threshold_code;
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goto out;
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}
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rising_threshold |= threshold_code << 8 * i;
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writel(rising_threshold,
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data->base + reg->threshold_th0);
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con = readl(data->base + reg->tmu_ctrl);
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con |= (1 << reg->therm_trip_en_shift);
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writel(con, data->base + reg->tmu_ctrl);
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}
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}
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out:
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clk_disable(data->clk);
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@ -123,6 +123,7 @@ struct exynos_tmu_platform_data const exynos5250_default_tmu_data = {
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.trigger_levels[0] = 85,
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.trigger_levels[1] = 103,
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.trigger_levels[2] = 110,
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.trigger_levels[3] = 120,
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.trigger_enable[0] = true,
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.trigger_enable[1] = true,
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.trigger_enable[2] = true,
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@ -130,6 +131,7 @@ struct exynos_tmu_platform_data const exynos5250_default_tmu_data = {
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.trigger_type[0] = THROTTLE_ACTIVE,
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.trigger_type[1] = THROTTLE_ACTIVE,
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.trigger_type[2] = SW_TRIP,
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.trigger_type[3] = HW_TRIP,
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.max_trigger_level = 4,
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.gain = 8,
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.reference_voltage = 16,
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@ -91,6 +91,8 @@
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#define EXYNOS_EMUL_DATA_MASK 0xFF
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#define EXYNOS_EMUL_ENABLE 0x1
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#define EXYNOS_MAX_TRIGGER_PER_REG 4
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#if defined(CONFIG_CPU_EXYNOS4210)
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extern struct exynos_tmu_platform_data const exynos4210_default_tmu_data;
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#define EXYNOS4210_TMU_DRV_DATA (&exynos4210_default_tmu_data)
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