mmc: jz4740: add dma infrastructure for data transfers
Until now the MMC driver for JZ4740 SoC was relying on PIO mode only for data transfers. This patch allows the use of DMA for data trasnfers in addition to PIO mode by relying on DMA Engine. DMA tranfers performance might be further improved by taking advantage of the asynchronous request capability of the MMC framework. Signed-off-by: Apelete Seketeli <apelete@seketeli.net> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
This commit is contained in:
Apelete Seketeli
Ulf Hansson
Родитель
f629ba2c04
Коммит
7ca27a6f80
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@ -30,7 +30,9 @@
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#include <asm/mach-jz4740/gpio.h>
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#include <asm/cacheflush.h>
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#include <linux/dma-mapping.h>
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#include <linux/dmaengine.h>
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#include <asm/mach-jz4740/dma.h>
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#include <asm/mach-jz4740/jz4740_mmc.h>
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#define JZ_REG_MMC_STRPCL 0x00
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@ -122,6 +124,7 @@ struct jz4740_mmc_host {
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int card_detect_irq;
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void __iomem *base;
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struct resource *mem_res;
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struct mmc_request *req;
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struct mmc_command *cmd;
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@ -136,8 +139,138 @@ struct jz4740_mmc_host {
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struct timer_list timeout_timer;
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struct sg_mapping_iter miter;
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enum jz4740_mmc_state state;
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/* DMA support */
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struct dma_chan *dma_rx;
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struct dma_chan *dma_tx;
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bool use_dma;
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int sg_len;
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/* The DMA trigger level is 8 words, that is to say, the DMA read
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* trigger is when data words in MSC_RXFIFO is >= 8 and the DMA write
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* trigger is when data words in MSC_TXFIFO is < 8.
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*/
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#define JZ4740_MMC_FIFO_HALF_SIZE 8
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};
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/*----------------------------------------------------------------------------*/
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/* DMA infrastructure */
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static void jz4740_mmc_release_dma_channels(struct jz4740_mmc_host *host)
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{
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if (!host->use_dma)
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return;
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dma_release_channel(host->dma_tx);
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dma_release_channel(host->dma_rx);
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}
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static int jz4740_mmc_acquire_dma_channels(struct jz4740_mmc_host *host)
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{
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dma_cap_mask_t mask;
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dma_cap_zero(mask);
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dma_cap_set(DMA_SLAVE, mask);
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host->dma_tx = dma_request_channel(mask, NULL, host);
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if (!host->dma_tx) {
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dev_err(mmc_dev(host->mmc), "Failed to get dma_tx channel\n");
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return -ENODEV;
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}
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host->dma_rx = dma_request_channel(mask, NULL, host);
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if (!host->dma_rx) {
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dev_err(mmc_dev(host->mmc), "Failed to get dma_rx channel\n");
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goto free_master_write;
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}
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return 0;
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free_master_write:
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dma_release_channel(host->dma_tx);
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return -ENODEV;
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}
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static inline int jz4740_mmc_get_dma_dir(struct mmc_data *data)
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{
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return (data->flags & MMC_DATA_READ) ? DMA_FROM_DEVICE : DMA_TO_DEVICE;
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}
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static void jz4740_mmc_dma_unmap(struct jz4740_mmc_host *host,
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struct mmc_data *data)
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{
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struct dma_chan *chan;
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enum dma_data_direction dir = jz4740_mmc_get_dma_dir(data);
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if (dir == DMA_TO_DEVICE)
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chan = host->dma_tx;
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else
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chan = host->dma_rx;
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dma_unmap_sg(chan->device->dev, data->sg, data->sg_len, dir);
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}
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static int jz4740_mmc_start_dma_transfer(struct jz4740_mmc_host *host,
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struct mmc_data *data)
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{
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struct dma_chan *chan;
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struct dma_async_tx_descriptor *desc;
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struct dma_slave_config conf = {
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.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES,
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.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES,
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.src_maxburst = JZ4740_MMC_FIFO_HALF_SIZE,
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.dst_maxburst = JZ4740_MMC_FIFO_HALF_SIZE,
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};
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enum dma_data_direction dir = jz4740_mmc_get_dma_dir(data);
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if (dir == DMA_TO_DEVICE) {
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conf.direction = DMA_MEM_TO_DEV;
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conf.dst_addr = host->mem_res->start + JZ_REG_MMC_TXFIFO;
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conf.slave_id = JZ4740_DMA_TYPE_MMC_TRANSMIT;
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chan = host->dma_tx;
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} else {
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conf.direction = DMA_DEV_TO_MEM;
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conf.src_addr = host->mem_res->start + JZ_REG_MMC_RXFIFO;
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conf.slave_id = JZ4740_DMA_TYPE_MMC_RECEIVE;
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chan = host->dma_rx;
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}
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host->sg_len = dma_map_sg(chan->device->dev,
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data->sg,
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data->sg_len,
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dir);
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if (host->sg_len == 0) {
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dev_err(mmc_dev(host->mmc),
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"Failed to map scatterlist for DMA operation\n");
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return -EINVAL;
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}
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dmaengine_slave_config(chan, &conf);
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desc = dmaengine_prep_slave_sg(chan,
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data->sg,
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host->sg_len,
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conf.direction,
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DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
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if (!desc) {
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dev_err(mmc_dev(host->mmc),
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"Failed to allocate DMA %s descriptor",
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conf.direction == DMA_MEM_TO_DEV ? "TX" : "RX");
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goto dma_unmap;
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}
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dmaengine_submit(desc);
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dma_async_issue_pending(chan);
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return 0;
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dma_unmap:
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jz4740_mmc_dma_unmap(host, data);
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return -ENOMEM;
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}
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/*----------------------------------------------------------------------------*/
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static void jz4740_mmc_set_irq_enabled(struct jz4740_mmc_host *host,
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unsigned int irq, bool enabled)
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{
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@ -442,6 +575,8 @@ static void jz4740_mmc_send_command(struct jz4740_mmc_host *host,
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cmdat |= JZ_MMC_CMDAT_WRITE;
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if (cmd->data->flags & MMC_DATA_STREAM)
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cmdat |= JZ_MMC_CMDAT_STREAM;
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if (host->use_dma)
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cmdat |= JZ_MMC_CMDAT_DMA_EN;
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writew(cmd->data->blksz, host->base + JZ_REG_MMC_BLKLEN);
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writew(cmd->data->blocks, host->base + JZ_REG_MMC_NOB);
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@ -474,6 +609,7 @@ static irqreturn_t jz_mmc_irq_worker(int irq, void *devid)
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struct jz4740_mmc_host *host = (struct jz4740_mmc_host *)devid;
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struct mmc_command *cmd = host->req->cmd;
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struct mmc_request *req = host->req;
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struct mmc_data *data = cmd->data;
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bool timeout = false;
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if (cmd->error)
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@ -484,23 +620,32 @@ static irqreturn_t jz_mmc_irq_worker(int irq, void *devid)
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if (cmd->flags & MMC_RSP_PRESENT)
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jz4740_mmc_read_response(host, cmd);
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if (!cmd->data)
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if (!data)
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break;
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jz_mmc_prepare_data_transfer(host);
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case JZ4740_MMC_STATE_TRANSFER_DATA:
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if (cmd->data->flags & MMC_DATA_READ)
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timeout = jz4740_mmc_read_data(host, cmd->data);
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if (host->use_dma) {
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/* Use DMA if enabled, data transfer direction was
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* defined before in jz_mmc_prepare_data_transfer().
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*/
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timeout = jz4740_mmc_start_dma_transfer(host, data);
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data->bytes_xfered = data->blocks * data->blksz;
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} else if (data->flags & MMC_DATA_READ)
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/* If DMA is not enabled, rely on data flags
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* to establish data transfer direction.
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*/
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timeout = jz4740_mmc_read_data(host, data);
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else
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timeout = jz4740_mmc_write_data(host, cmd->data);
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timeout = jz4740_mmc_write_data(host, data);
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if (unlikely(timeout)) {
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host->state = JZ4740_MMC_STATE_TRANSFER_DATA;
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break;
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}
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jz4740_mmc_transfer_check_state(host, cmd->data);
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jz4740_mmc_transfer_check_state(host, data);
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timeout = jz4740_mmc_poll_irq(host, JZ_MMC_IRQ_DATA_TRAN_DONE);
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if (unlikely(timeout)) {
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@ -757,7 +902,6 @@ static int jz4740_mmc_probe(struct platform_device* pdev)
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struct mmc_host *mmc;
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struct jz4740_mmc_host *host;
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struct jz4740_mmc_platform_data *pdata;
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struct resource *res;
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pdata = pdev->dev.platform_data;
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@ -784,10 +928,11 @@ static int jz4740_mmc_probe(struct platform_device* pdev)
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goto err_free_host;
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}
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res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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host->base = devm_ioremap_resource(&pdev->dev, res);
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host->mem_res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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host->base = devm_ioremap_resource(&pdev->dev, host->mem_res);
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if (IS_ERR(host->base)) {
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ret = PTR_ERR(host->base);
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dev_err(&pdev->dev, "Failed to ioremap base memory\n");
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goto err_free_host;
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}
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@ -834,6 +979,10 @@ static int jz4740_mmc_probe(struct platform_device* pdev)
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/* It is not important when it times out, it just needs to timeout. */
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set_timer_slack(&host->timeout_timer, HZ);
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host->use_dma = true;
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if (host->use_dma && jz4740_mmc_acquire_dma_channels(host) != 0)
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host->use_dma = false;
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platform_set_drvdata(pdev, host);
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ret = mmc_add_host(mmc);
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@ -843,6 +992,10 @@ static int jz4740_mmc_probe(struct platform_device* pdev)
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}
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dev_info(&pdev->dev, "JZ SD/MMC card driver registered\n");
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dev_info(&pdev->dev, "Using %s, %d-bit mode\n",
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host->use_dma ? "DMA" : "PIO",
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(mmc->caps & MMC_CAP_4_BIT_DATA) ? 4 : 1);
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return 0;
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err_free_irq:
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@ -850,6 +1003,8 @@ err_free_irq:
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err_free_gpios:
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jz4740_mmc_free_gpios(pdev);
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err_gpio_bulk_free:
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if (host->use_dma)
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jz4740_mmc_release_dma_channels(host);
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jz_gpio_bulk_free(jz4740_mmc_pins, jz4740_mmc_num_pins(host));
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err_free_host:
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mmc_free_host(mmc);
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@ -872,6 +1027,9 @@ static int jz4740_mmc_remove(struct platform_device *pdev)
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jz4740_mmc_free_gpios(pdev);
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jz_gpio_bulk_free(jz4740_mmc_pins, jz4740_mmc_num_pins(host));
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if (host->use_dma)
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jz4740_mmc_release_dma_channels(host);
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mmc_free_host(host->mmc);
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return 0;
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