ASoC: Intel: Remove SST-legacy specific constants
As sound/soc/intel/haswell and /baytrail are no more, all SST-legacy specific constants and registers are redundant so remove them. Signed-off-by: Cezary Rojewski <cezary.rojewski@intel.com> Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Acked-by: Liam Girdwood <liam.r.girdwood@intel.com> Link: https://lore.kernel.org/r/20201006064907.16277-11-cezary.rojewski@intel.com Signed-off-by: Mark Brown <broonie@kernel.org>
This commit is contained in:
Cezary Rojewski
Mark Brown
Родитель
b4e6080718
Коммит
7d07f9c1ba
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@ -15,9 +15,6 @@
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#include "../skylake/skl-sst-dsp.h"
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/* do we need to remove or keep */
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#define DSP_DRAM_ADDR_OFFSET 0x400000
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/*
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* DSP Operations exported by platform Audio DSP driver.
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*/
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@ -12,158 +12,15 @@
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#include <linux/types.h>
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#include <linux/interrupt.h>
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/* SST Device IDs */
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#define SST_DEV_ID_LYNX_POINT 0x33C8
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#define SST_DEV_ID_WILDCAT_POINT 0x3438
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#define SST_DEV_ID_BYT 0x0F28
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/* Supported SST DMA Devices */
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#define SST_DMA_TYPE_DW 1
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/* autosuspend delay 5s*/
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#define SST_RUNTIME_SUSPEND_DELAY (5 * 1000)
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/* SST Shim register map
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* The register naming can differ between products. Some products also
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* contain extra functionality.
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*/
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#define SST_CSR 0x00
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#define SST_PISR 0x08
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#define SST_PIMR 0x10
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#define SST_ISRX 0x18
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#define SST_ISRD 0x20
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#define SST_IMRX 0x28
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#define SST_IMRD 0x30
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#define SST_IPCX 0x38 /* IPC IA -> SST */
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#define SST_IPCD 0x40 /* IPC SST -> IA */
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#define SST_ISRSC 0x48
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#define SST_ISRLPESC 0x50
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#define SST_IMRSC 0x58
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#define SST_IMRLPESC 0x60
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#define SST_IPCSC 0x68
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#define SST_IPCLPESC 0x70
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#define SST_CLKCTL 0x78
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#define SST_CSR2 0x80
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#define SST_LTRC 0xE0
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#define SST_HMDC 0xE8
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#define SST_SHIM_BEGIN SST_CSR
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#define SST_SHIM_END SST_HDMC
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#define SST_DBGO 0xF0
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#define SST_SHIM_SIZE 0x100
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#define SST_PWMCTRL 0x1000
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/* SST Shim Register bits
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* The register bit naming can differ between products. Some products also
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* contain extra functionality.
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*/
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/* CSR / CS */
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#define SST_CSR_RST (0x1 << 1)
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#define SST_CSR_SBCS0 (0x1 << 2)
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#define SST_CSR_SBCS1 (0x1 << 3)
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#define SST_CSR_DCS(x) (x << 4)
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#define SST_CSR_DCS_MASK (0x7 << 4)
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#define SST_CSR_STALL (0x1 << 10)
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#define SST_CSR_S0IOCS (0x1 << 21)
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#define SST_CSR_S1IOCS (0x1 << 23)
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#define SST_CSR_LPCS (0x1 << 31)
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#define SST_CSR_24MHZ_LPCS (SST_CSR_SBCS0 | SST_CSR_SBCS1 | SST_CSR_LPCS)
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#define SST_CSR_24MHZ_NO_LPCS (SST_CSR_SBCS0 | SST_CSR_SBCS1)
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#define SST_BYT_CSR_RST (0x1 << 0)
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#define SST_BYT_CSR_VECTOR_SEL (0x1 << 1)
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#define SST_BYT_CSR_STALL (0x1 << 2)
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#define SST_BYT_CSR_PWAITMODE (0x1 << 3)
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/* ISRX / ISC */
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#define SST_ISRX_BUSY (0x1 << 1)
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#define SST_ISRX_DONE (0x1 << 0)
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#define SST_BYT_ISRX_REQUEST (0x1 << 1)
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/* ISRD / ISD */
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#define SST_ISRD_BUSY (0x1 << 1)
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#define SST_ISRD_DONE (0x1 << 0)
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/* IMRX / IMC */
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#define SST_IMRX_BUSY (0x1 << 1)
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#define SST_IMRX_DONE (0x1 << 0)
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#define SST_BYT_IMRX_REQUEST (0x1 << 1)
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/* IMRD / IMD */
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#define SST_IMRD_DONE (0x1 << 0)
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#define SST_IMRD_BUSY (0x1 << 1)
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#define SST_IMRD_SSP0 (0x1 << 16)
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#define SST_IMRD_DMAC0 (0x1 << 21)
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#define SST_IMRD_DMAC1 (0x1 << 22)
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#define SST_IMRD_DMAC (SST_IMRD_DMAC0 | SST_IMRD_DMAC1)
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/* IPCX / IPCC */
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#define SST_IPCX_DONE (0x1 << 30)
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#define SST_IPCX_BUSY (0x1 << 31)
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#define SST_BYT_IPCX_DONE ((u64)0x1 << 62)
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#define SST_BYT_IPCX_BUSY ((u64)0x1 << 63)
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/* IPCD */
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#define SST_IPCD_DONE (0x1 << 30)
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#define SST_IPCD_BUSY (0x1 << 31)
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#define SST_BYT_IPCD_DONE ((u64)0x1 << 62)
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#define SST_BYT_IPCD_BUSY ((u64)0x1 << 63)
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/* CLKCTL */
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#define SST_CLKCTL_SMOS(x) (x << 24)
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#define SST_CLKCTL_MASK (3 << 24)
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#define SST_CLKCTL_DCPLCG (1 << 18)
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#define SST_CLKCTL_SCOE1 (1 << 17)
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#define SST_CLKCTL_SCOE0 (1 << 16)
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/* CSR2 / CS2 */
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#define SST_CSR2_SDFD_SSP0 (1 << 1)
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#define SST_CSR2_SDFD_SSP1 (1 << 2)
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/* LTRC */
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#define SST_LTRC_VAL(x) (x << 0)
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/* HMDC */
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#define SST_HMDC_HDDA0(x) (x << 0)
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#define SST_HMDC_HDDA1(x) (x << 7)
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#define SST_HMDC_HDDA_E0_CH0 1
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#define SST_HMDC_HDDA_E0_CH1 2
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#define SST_HMDC_HDDA_E0_CH2 4
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#define SST_HMDC_HDDA_E0_CH3 8
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#define SST_HMDC_HDDA_E1_CH0 SST_HMDC_HDDA1(SST_HMDC_HDDA_E0_CH0)
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#define SST_HMDC_HDDA_E1_CH1 SST_HMDC_HDDA1(SST_HMDC_HDDA_E0_CH1)
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#define SST_HMDC_HDDA_E1_CH2 SST_HMDC_HDDA1(SST_HMDC_HDDA_E0_CH2)
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#define SST_HMDC_HDDA_E1_CH3 SST_HMDC_HDDA1(SST_HMDC_HDDA_E0_CH3)
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#define SST_HMDC_HDDA_E0_ALLCH (SST_HMDC_HDDA_E0_CH0 | SST_HMDC_HDDA_E0_CH1 | \
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SST_HMDC_HDDA_E0_CH2 | SST_HMDC_HDDA_E0_CH3)
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#define SST_HMDC_HDDA_E1_ALLCH (SST_HMDC_HDDA_E1_CH0 | SST_HMDC_HDDA_E1_CH1 | \
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SST_HMDC_HDDA_E1_CH2 | SST_HMDC_HDDA_E1_CH3)
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/* SST Vendor Defined Registers and bits */
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#define SST_VDRTCTL0 0xa0
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#define SST_VDRTCTL1 0xa4
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#define SST_VDRTCTL2 0xa8
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#define SST_VDRTCTL3 0xaC
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/* VDRTCTL0 */
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#define SST_VDRTCL0_D3PGD (1 << 0)
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#define SST_VDRTCL0_D3SRAMPGD (1 << 1)
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#define SST_VDRTCL0_DSRAMPGE_SHIFT 12
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#define SST_VDRTCL0_DSRAMPGE_MASK (0xfffff << SST_VDRTCL0_DSRAMPGE_SHIFT)
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#define SST_VDRTCL0_ISRAMPGE_SHIFT 2
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#define SST_VDRTCL0_ISRAMPGE_MASK (0x3ff << SST_VDRTCL0_ISRAMPGE_SHIFT)
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/* VDRTCTL2 */
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#define SST_VDRTCL2_DCLCGE (1 << 1)
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#define SST_VDRTCL2_DTCGE (1 << 10)
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#define SST_VDRTCL2_APLLSE_MASK (1 << 31)
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/* PMCS */
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#define SST_PMCS 0x84
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#define SST_PMCS_PS_MASK 0x3
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struct sst_dsp;
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@ -15,8 +15,6 @@
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#include <linux/workqueue.h>
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#include <linux/sched.h>
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#define IPC_MAX_MAILBOX_BYTES 256
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struct sst_ipc_message {
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u64 header;
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void *data;
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