ARM: gic: irq_data conversion.
Signed-off-by: Lennert Buytenhek <buytenh@secretlab.ca> Acked-by: Abhijeet Dharmapurikar <adharmap@codeaurora.org>
This commit is contained in:
Lennert Buytenhek
Родитель
4a87bac4c9
Коммит
7d1f4288ac
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@ -50,57 +50,56 @@ struct gic_chip_data {
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static struct gic_chip_data gic_data[MAX_GIC_NR] __read_mostly;
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static inline void __iomem *gic_dist_base(unsigned int irq)
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static inline void __iomem *gic_dist_base(struct irq_data *d)
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{
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struct gic_chip_data *gic_data = get_irq_chip_data(irq);
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struct gic_chip_data *gic_data = irq_data_get_irq_chip_data(d);
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return gic_data->dist_base;
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}
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static inline void __iomem *gic_cpu_base(unsigned int irq)
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static inline void __iomem *gic_cpu_base(struct irq_data *d)
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{
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struct gic_chip_data *gic_data = get_irq_chip_data(irq);
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struct gic_chip_data *gic_data = irq_data_get_irq_chip_data(d);
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return gic_data->cpu_base;
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}
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static inline unsigned int gic_irq(unsigned int irq)
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static inline unsigned int gic_irq(struct irq_data *d)
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{
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struct gic_chip_data *gic_data = get_irq_chip_data(irq);
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return irq - gic_data->irq_offset;
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struct gic_chip_data *gic_data = irq_data_get_irq_chip_data(d);
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return d->irq - gic_data->irq_offset;
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}
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/*
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* Routines to acknowledge, disable and enable interrupts
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*/
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static void gic_ack_irq(unsigned int irq)
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static void gic_ack_irq(struct irq_data *d)
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{
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spin_lock(&irq_controller_lock);
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writel(gic_irq(irq), gic_cpu_base(irq) + GIC_CPU_EOI);
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writel(gic_irq(d), gic_cpu_base(d) + GIC_CPU_EOI);
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spin_unlock(&irq_controller_lock);
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}
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static void gic_mask_irq(unsigned int irq)
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static void gic_mask_irq(struct irq_data *d)
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{
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u32 mask = 1 << (irq % 32);
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u32 mask = 1 << (d->irq % 32);
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spin_lock(&irq_controller_lock);
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writel(mask, gic_dist_base(irq) + GIC_DIST_ENABLE_CLEAR + (gic_irq(irq) / 32) * 4);
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writel(mask, gic_dist_base(d) + GIC_DIST_ENABLE_CLEAR + (gic_irq(d) / 32) * 4);
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spin_unlock(&irq_controller_lock);
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}
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static void gic_unmask_irq(unsigned int irq)
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static void gic_unmask_irq(struct irq_data *d)
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{
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u32 mask = 1 << (irq % 32);
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u32 mask = 1 << (d->irq % 32);
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spin_lock(&irq_controller_lock);
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writel(mask, gic_dist_base(irq) + GIC_DIST_ENABLE_SET + (gic_irq(irq) / 32) * 4);
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writel(mask, gic_dist_base(d) + GIC_DIST_ENABLE_SET + (gic_irq(d) / 32) * 4);
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spin_unlock(&irq_controller_lock);
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}
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static int gic_set_type(unsigned int irq, unsigned int type)
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static int gic_set_type(struct irq_data *d, unsigned int type)
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{
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void __iomem *base = gic_dist_base(irq);
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unsigned int gicirq = gic_irq(irq);
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void __iomem *base = gic_dist_base(d);
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unsigned int gicirq = gic_irq(d);
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u32 enablemask = 1 << (gicirq % 32);
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u32 enableoff = (gicirq / 32) * 4;
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u32 confmask = 0x2 << ((gicirq % 16) * 2);
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@ -143,21 +142,22 @@ static int gic_set_type(unsigned int irq, unsigned int type)
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}
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#ifdef CONFIG_SMP
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static int gic_set_cpu(unsigned int irq, const struct cpumask *mask_val)
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static int
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gic_set_cpu(struct irq_data *d, const struct cpumask *mask_val, bool force)
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{
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void __iomem *reg = gic_dist_base(irq) + GIC_DIST_TARGET + (gic_irq(irq) & ~3);
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unsigned int shift = (irq % 4) * 8;
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void __iomem *reg = gic_dist_base(d) + GIC_DIST_TARGET + (gic_irq(d) & ~3);
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unsigned int shift = (d->irq % 4) * 8;
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unsigned int cpu = cpumask_first(mask_val);
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u32 val;
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struct irq_desc *desc;
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spin_lock(&irq_controller_lock);
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desc = irq_to_desc(irq);
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desc = irq_to_desc(d->irq);
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if (desc == NULL) {
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spin_unlock(&irq_controller_lock);
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return -EINVAL;
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}
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desc->node = cpu;
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d->node = cpu;
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val = readl(reg) & ~(0xff << shift);
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val |= 1 << (cpu + shift);
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writel(val, reg);
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@ -175,7 +175,7 @@ static void gic_handle_cascade_irq(unsigned int irq, struct irq_desc *desc)
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unsigned long status;
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/* primary controller ack'ing */
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chip->ack(irq);
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chip->irq_ack(&desc->irq_data);
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spin_lock(&irq_controller_lock);
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status = readl(chip_data->cpu_base + GIC_CPU_INTACK);
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@ -193,17 +193,17 @@ static void gic_handle_cascade_irq(unsigned int irq, struct irq_desc *desc)
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out:
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/* primary controller unmasking */
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chip->unmask(irq);
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chip->irq_unmask(&desc->irq_data);
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}
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static struct irq_chip gic_chip = {
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.name = "GIC",
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.ack = gic_ack_irq,
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.mask = gic_mask_irq,
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.unmask = gic_unmask_irq,
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.set_type = gic_set_type,
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.name = "GIC",
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.irq_ack = gic_ack_irq,
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.irq_mask = gic_mask_irq,
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.irq_unmask = gic_unmask_irq,
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.irq_set_type = gic_set_type,
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#ifdef CONFIG_SMP
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.set_affinity = gic_set_cpu,
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.irq_set_affinity = gic_set_cpu,
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#endif
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};
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@ -337,7 +337,7 @@ void __cpuinit gic_enable_ppi(unsigned int irq)
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local_irq_save(flags);
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irq_to_desc(irq)->status |= IRQ_NOPROBE;
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gic_unmask_irq(irq);
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gic_unmask_irq(irq_get_irq_data(irq));
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local_irq_restore(flags);
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}
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