Merge remote-tracking branch 'asoc/topic/pcm512x' into asoc-next
This commit is contained in:
Mark Brown
Коммит
7d590e4623
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@ -5,7 +5,8 @@ on the board).
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Required properties:
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- compatible : One of "ti,pcm5121" or "ti,pcm5122"
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- compatible : One of "ti,pcm5121", "ti,pcm5122", "ti,pcm5141" or
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"ti,pcm5142"
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- reg : the I2C address of the device for I2C, the chip select
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number for SPI.
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@ -16,9 +17,16 @@ Required properties:
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Optional properties:
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- clocks : A clock specifier for the clock connected as SCLK. If this
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is absent the device will be configured to clock from BCLK.
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is absent the device will be configured to clock from BCLK. If pll-in
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and pll-out are specified in addition to a clock, the device is
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configured to accept clock input on a specified gpio pin.
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Example:
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- pll-in, pll-out : gpio pins used to connect the pll using <1>
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through <6>. The device will be configured for clock input on the
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given pll-in pin and PLL output on the given pll-out pin. An
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external connection from the pll-out pin to the SCLK pin is assumed.
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Examples:
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pcm5122: pcm5122@4c {
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compatible = "ti,pcm5122";
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@ -28,3 +36,17 @@ Example:
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DVDD-supply = <®_1v8>;
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CPVDD-supply = <®_3v3>;
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};
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pcm5142: pcm5142@4c {
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compatible = "ti,pcm5142";
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reg = <0x4c>;
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AVDD-supply = <®_3v3_analog>;
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DVDD-supply = <®_1v8>;
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CPVDD-supply = <®_3v3>;
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clocks = <&sck>;
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pll-in = <3>;
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pll-out = <6>;
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};
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@ -275,6 +275,12 @@ struct snd_pcm_hw_constraint_list {
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unsigned int mask;
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};
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struct snd_pcm_hw_constraint_ranges {
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unsigned int count;
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const struct snd_interval *ranges;
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unsigned int mask;
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};
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struct snd_pcm_hwptr_log;
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struct snd_pcm_runtime {
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@ -910,6 +916,8 @@ void snd_interval_mulkdiv(const struct snd_interval *a, unsigned int k,
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const struct snd_interval *b, struct snd_interval *c);
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int snd_interval_list(struct snd_interval *i, unsigned int count,
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const unsigned int *list, unsigned int mask);
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int snd_interval_ranges(struct snd_interval *i, unsigned int count,
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const struct snd_interval *list, unsigned int mask);
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int snd_interval_ratnum(struct snd_interval *i,
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unsigned int rats_count, struct snd_ratnum *rats,
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unsigned int *nump, unsigned int *denp);
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@ -934,6 +942,10 @@ int snd_pcm_hw_constraint_list(struct snd_pcm_runtime *runtime,
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unsigned int cond,
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snd_pcm_hw_param_t var,
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const struct snd_pcm_hw_constraint_list *l);
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int snd_pcm_hw_constraint_ranges(struct snd_pcm_runtime *runtime,
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unsigned int cond,
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snd_pcm_hw_param_t var,
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const struct snd_pcm_hw_constraint_ranges *r);
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int snd_pcm_hw_constraint_ratnums(struct snd_pcm_runtime *runtime,
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unsigned int cond,
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snd_pcm_hw_param_t var,
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@ -1015,6 +1015,60 @@ int snd_interval_list(struct snd_interval *i, unsigned int count,
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EXPORT_SYMBOL(snd_interval_list);
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/**
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* snd_interval_ranges - refine the interval value from the list of ranges
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* @i: the interval value to refine
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* @count: the number of elements in the list of ranges
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* @ranges: the ranges list
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* @mask: the bit-mask to evaluate
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*
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* Refines the interval value from the list of ranges.
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* When mask is non-zero, only the elements corresponding to bit 1 are
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* evaluated.
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*
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* Return: Positive if the value is changed, zero if it's not changed, or a
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* negative error code.
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*/
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int snd_interval_ranges(struct snd_interval *i, unsigned int count,
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const struct snd_interval *ranges, unsigned int mask)
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{
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unsigned int k;
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struct snd_interval range_union;
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struct snd_interval range;
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if (!count) {
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snd_interval_none(i);
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return -EINVAL;
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}
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snd_interval_any(&range_union);
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range_union.min = UINT_MAX;
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range_union.max = 0;
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for (k = 0; k < count; k++) {
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if (mask && !(mask & (1 << k)))
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continue;
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snd_interval_copy(&range, &ranges[k]);
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if (snd_interval_refine(&range, i) < 0)
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continue;
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if (snd_interval_empty(&range))
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continue;
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if (range.min < range_union.min) {
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range_union.min = range.min;
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range_union.openmin = 1;
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}
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if (range.min == range_union.min && !range.openmin)
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range_union.openmin = 0;
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if (range.max > range_union.max) {
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range_union.max = range.max;
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range_union.openmax = 1;
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}
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if (range.max == range_union.max && !range.openmax)
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range_union.openmax = 0;
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}
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return snd_interval_refine(i, &range_union);
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}
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EXPORT_SYMBOL(snd_interval_ranges);
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static int snd_interval_step(struct snd_interval *i, unsigned int step)
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{
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unsigned int n;
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@ -1221,6 +1275,37 @@ int snd_pcm_hw_constraint_list(struct snd_pcm_runtime *runtime,
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EXPORT_SYMBOL(snd_pcm_hw_constraint_list);
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static int snd_pcm_hw_rule_ranges(struct snd_pcm_hw_params *params,
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struct snd_pcm_hw_rule *rule)
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{
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struct snd_pcm_hw_constraint_ranges *r = rule->private;
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return snd_interval_ranges(hw_param_interval(params, rule->var),
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r->count, r->ranges, r->mask);
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}
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/**
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* snd_pcm_hw_constraint_ranges - apply list of range constraints to a parameter
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* @runtime: PCM runtime instance
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* @cond: condition bits
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* @var: hw_params variable to apply the list of range constraints
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* @r: ranges
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*
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* Apply the list of range constraints to an interval parameter.
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*
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* Return: Zero if successful, or a negative error code on failure.
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*/
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int snd_pcm_hw_constraint_ranges(struct snd_pcm_runtime *runtime,
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unsigned int cond,
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snd_pcm_hw_param_t var,
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const struct snd_pcm_hw_constraint_ranges *r)
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{
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return snd_pcm_hw_rule_add(runtime, cond, var,
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snd_pcm_hw_rule_ranges, (void *)r,
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var, -1);
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}
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EXPORT_SYMBOL(snd_pcm_hw_constraint_ranges);
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static int snd_pcm_hw_rule_ratnums(struct snd_pcm_hw_params *params,
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struct snd_pcm_hw_rule *rule)
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{
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@ -46,6 +46,8 @@ static int pcm512x_i2c_remove(struct i2c_client *i2c)
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static const struct i2c_device_id pcm512x_i2c_id[] = {
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{ "pcm5121", },
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{ "pcm5122", },
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{ "pcm5141", },
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{ "pcm5142", },
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{ }
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};
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MODULE_DEVICE_TABLE(i2c, pcm512x_i2c_id);
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@ -53,6 +55,8 @@ MODULE_DEVICE_TABLE(i2c, pcm512x_i2c_id);
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static const struct of_device_id pcm512x_of_match[] = {
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{ .compatible = "ti,pcm5121", },
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{ .compatible = "ti,pcm5122", },
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{ .compatible = "ti,pcm5141", },
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{ .compatible = "ti,pcm5142", },
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{ }
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};
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MODULE_DEVICE_TABLE(of, pcm512x_of_match);
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@ -43,6 +43,8 @@ static int pcm512x_spi_remove(struct spi_device *spi)
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static const struct spi_device_id pcm512x_spi_id[] = {
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{ "pcm5121", },
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{ "pcm5122", },
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{ "pcm5141", },
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{ "pcm5142", },
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{ },
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};
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MODULE_DEVICE_TABLE(spi, pcm512x_spi_id);
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@ -50,6 +52,8 @@ MODULE_DEVICE_TABLE(spi, pcm512x_spi_id);
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static const struct of_device_id pcm512x_of_match[] = {
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{ .compatible = "ti,pcm5121", },
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{ .compatible = "ti,pcm5122", },
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{ .compatible = "ti,pcm5141", },
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{ .compatible = "ti,pcm5142", },
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{ }
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};
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MODULE_DEVICE_TABLE(of, pcm512x_of_match);
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Разница между файлами не показана из-за своего большого размера
Загрузить разницу
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@ -37,6 +37,10 @@
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#define PCM512x_DSP_GPIO_INPUT (PCM512x_PAGE_BASE(0) + 10)
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#define PCM512x_MASTER_MODE (PCM512x_PAGE_BASE(0) + 12)
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#define PCM512x_PLL_REF (PCM512x_PAGE_BASE(0) + 13)
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#define PCM512x_DAC_REF (PCM512x_PAGE_BASE(0) + 14)
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#define PCM512x_GPIO_DACIN (PCM512x_PAGE_BASE(0) + 16)
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#define PCM512x_GPIO_PLLIN (PCM512x_PAGE_BASE(0) + 18)
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#define PCM512x_SYNCHRONIZE (PCM512x_PAGE_BASE(0) + 19)
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#define PCM512x_PLL_COEFF_0 (PCM512x_PAGE_BASE(0) + 20)
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#define PCM512x_PLL_COEFF_1 (PCM512x_PAGE_BASE(0) + 21)
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#define PCM512x_PLL_COEFF_2 (PCM512x_PAGE_BASE(0) + 22)
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@ -77,6 +81,7 @@
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#define PCM512x_RATE_DET_2 (PCM512x_PAGE_BASE(0) + 92)
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#define PCM512x_RATE_DET_3 (PCM512x_PAGE_BASE(0) + 93)
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#define PCM512x_RATE_DET_4 (PCM512x_PAGE_BASE(0) + 94)
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#define PCM512x_CLOCK_STATUS (PCM512x_PAGE_BASE(0) + 95)
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#define PCM512x_ANALOG_MUTE_DET (PCM512x_PAGE_BASE(0) + 108)
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#define PCM512x_GPIN (PCM512x_PAGE_BASE(0) + 119)
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#define PCM512x_DIGITAL_MUTE_DET (PCM512x_PAGE_BASE(0) + 120)
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@ -91,7 +96,10 @@
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#define PCM512x_CRAM_CTRL (PCM512x_PAGE_BASE(44) + 1)
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#define PCM512x_MAX_REGISTER (PCM512x_PAGE_BASE(44) + 1)
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#define PCM512x_FLEX_A (PCM512x_PAGE_BASE(253) + 63)
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#define PCM512x_FLEX_B (PCM512x_PAGE_BASE(253) + 64)
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#define PCM512x_MAX_REGISTER (PCM512x_PAGE_BASE(253) + 64)
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/* Page 0, Register 1 - reset */
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#define PCM512x_RSTR (1 << 0)
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@ -108,8 +116,8 @@
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#define PCM512x_RQML_SHIFT 4
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/* Page 0, Register 4 - PLL */
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#define PCM512x_PLCE (1 << 0)
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#define PCM512x_RLCE_SHIFT 0
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#define PCM512x_PLLE (1 << 0)
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#define PCM512x_PLLE_SHIFT 0
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#define PCM512x_PLCK (1 << 4)
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#define PCM512x_PLCK_SHIFT 4
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@ -119,8 +127,66 @@
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#define PCM512x_DEMP (1 << 4)
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#define PCM512x_DEMP_SHIFT 4
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/* Page 0, Register 8 - GPIO output enable */
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#define PCM512x_G1OE (1 << 0)
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#define PCM512x_G2OE (1 << 1)
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#define PCM512x_G3OE (1 << 2)
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#define PCM512x_G4OE (1 << 3)
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#define PCM512x_G5OE (1 << 4)
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#define PCM512x_G6OE (1 << 5)
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/* Page 0, Register 9 - BCK, LRCLK configuration */
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#define PCM512x_LRKO (1 << 0)
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#define PCM512x_LRKO_SHIFT 0
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#define PCM512x_BCKO (1 << 4)
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#define PCM512x_BCKO_SHIFT 4
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#define PCM512x_BCKP (1 << 5)
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#define PCM512x_BCKP_SHIFT 5
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|
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/* Page 0, Register 12 - Master mode BCK, LRCLK reset */
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#define PCM512x_RLRK (1 << 0)
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#define PCM512x_RLRK_SHIFT 0
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#define PCM512x_RBCK (1 << 1)
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#define PCM512x_RBCK_SHIFT 1
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|
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/* Page 0, Register 13 - PLL reference */
|
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#define PCM512x_SREF (1 << 4)
|
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#define PCM512x_SREF (7 << 4)
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#define PCM512x_SREF_SHIFT 4
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#define PCM512x_SREF_SCK (0 << 4)
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#define PCM512x_SREF_BCK (1 << 4)
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#define PCM512x_SREF_GPIO (3 << 4)
|
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|
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/* Page 0, Register 14 - DAC reference */
|
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#define PCM512x_SDAC (7 << 4)
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#define PCM512x_SDAC_SHIFT 4
|
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#define PCM512x_SDAC_MCK (0 << 4)
|
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#define PCM512x_SDAC_PLL (1 << 4)
|
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#define PCM512x_SDAC_SCK (3 << 4)
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#define PCM512x_SDAC_BCK (4 << 4)
|
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#define PCM512x_SDAC_GPIO (5 << 4)
|
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|
||||
/* Page 0, Register 16, 18 - GPIO source for DAC, PLL */
|
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#define PCM512x_GREF (7 << 0)
|
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#define PCM512x_GREF_SHIFT 0
|
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#define PCM512x_GREF_GPIO1 (0 << 0)
|
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#define PCM512x_GREF_GPIO2 (1 << 0)
|
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#define PCM512x_GREF_GPIO3 (2 << 0)
|
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#define PCM512x_GREF_GPIO4 (3 << 0)
|
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#define PCM512x_GREF_GPIO5 (4 << 0)
|
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#define PCM512x_GREF_GPIO6 (5 << 0)
|
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|
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/* Page 0, Register 19 - synchronize */
|
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#define PCM512x_RQSY (1 << 0)
|
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#define PCM512x_RQSY_RESUME (0 << 0)
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#define PCM512x_RQSY_HALT (1 << 0)
|
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|
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/* Page 0, Register 34 - fs speed mode */
|
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#define PCM512x_FSSP (3 << 0)
|
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#define PCM512x_FSSP_SHIFT 0
|
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#define PCM512x_FSSP_48KHZ (0 << 0)
|
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#define PCM512x_FSSP_96KHZ (1 << 0)
|
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#define PCM512x_FSSP_192KHZ (2 << 0)
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#define PCM512x_FSSP_384KHZ (3 << 0)
|
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|
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/* Page 0, Register 37 - Error detection */
|
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#define PCM512x_IPLK (1 << 0)
|
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|
|
@ -131,6 +197,20 @@
|
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#define PCM512x_IDBK (1 << 5)
|
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#define PCM512x_IDFS (1 << 6)
|
||||
|
||||
/* Page 0, Register 40 - I2S configuration */
|
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#define PCM512x_ALEN (3 << 0)
|
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#define PCM512x_ALEN_SHIFT 0
|
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#define PCM512x_ALEN_16 (0 << 0)
|
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#define PCM512x_ALEN_20 (1 << 0)
|
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#define PCM512x_ALEN_24 (2 << 0)
|
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#define PCM512x_ALEN_32 (3 << 0)
|
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#define PCM512x_AFMT (3 << 4)
|
||||
#define PCM512x_AFMT_SHIFT 4
|
||||
#define PCM512x_AFMT_I2S (0 << 4)
|
||||
#define PCM512x_AFMT_DSP (1 << 4)
|
||||
#define PCM512x_AFMT_RTJ (2 << 4)
|
||||
#define PCM512x_AFMT_LTJ (3 << 4)
|
||||
|
||||
/* Page 0, Register 42 - DAC routing */
|
||||
#define PCM512x_AUPR_SHIFT 0
|
||||
#define PCM512x_AUPL_SHIFT 4
|
||||
|
|
@ -152,7 +232,26 @@
|
|||
/* Page 0, Register 65 - Digital mute enables */
|
||||
#define PCM512x_ACTL_SHIFT 2
|
||||
#define PCM512x_AMLE_SHIFT 1
|
||||
#define PCM512x_AMLR_SHIFT 0
|
||||
#define PCM512x_AMRE_SHIFT 0
|
||||
|
||||
/* Page 0, Register 80-85, GPIO output selection */
|
||||
#define PCM512x_GxSL (31 << 0)
|
||||
#define PCM512x_GxSL_SHIFT 0
|
||||
#define PCM512x_GxSL_OFF (0 << 0)
|
||||
#define PCM512x_GxSL_DSP (1 << 0)
|
||||
#define PCM512x_GxSL_REG (2 << 0)
|
||||
#define PCM512x_GxSL_AMUTB (3 << 0)
|
||||
#define PCM512x_GxSL_AMUTL (4 << 0)
|
||||
#define PCM512x_GxSL_AMUTR (5 << 0)
|
||||
#define PCM512x_GxSL_CLKI (6 << 0)
|
||||
#define PCM512x_GxSL_SDOUT (7 << 0)
|
||||
#define PCM512x_GxSL_ANMUL (8 << 0)
|
||||
#define PCM512x_GxSL_ANMUR (9 << 0)
|
||||
#define PCM512x_GxSL_PLLLK (10 << 0)
|
||||
#define PCM512x_GxSL_CPCLK (11 << 0)
|
||||
#define PCM512x_GxSL_UV0_7 (14 << 0)
|
||||
#define PCM512x_GxSL_UV0_3 (15 << 0)
|
||||
#define PCM512x_GxSL_PLLCK (16 << 0)
|
||||
|
||||
/* Page 1, Register 2 - analog volume control */
|
||||
#define PCM512x_RAGN_SHIFT 0
|
||||
|
|
|
|||
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