KVM: LAPIC: extract start_sw_period() to handle periodic/oneshot mode
Extract start_sw_period() to handle periodic/oneshot mode, it will be used by later patch. Cc: Paolo Bonzini <pbonzini@redhat.com> Cc: Radim Krčmář <rkrcmar@redhat.com> Cc: Yunhong Jiang <yunhong.jiang@intel.com> Signed-off-by: Wanpeng Li <wanpeng.li@hotmail.com> Signed-off-by: Radim Krčmář <rkrcmar@redhat.com>
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@ -1347,6 +1347,50 @@ static void start_sw_tscdeadline(struct kvm_lapic *apic)
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local_irq_restore(flags);
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}
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static void start_sw_period(struct kvm_lapic *apic)
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{
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ktime_t now;
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/* lapic timer in oneshot or periodic mode */
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now = apic->lapic_timer.timer.base->get_time();
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apic->lapic_timer.period = (u64)kvm_lapic_get_reg(apic, APIC_TMICT)
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* APIC_BUS_CYCLE_NS * apic->divide_count;
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if (!apic->lapic_timer.period)
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return;
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/*
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* Do not allow the guest to program periodic timers with small
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* interval, since the hrtimers are not throttled by the host
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* scheduler.
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*/
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if (apic_lvtt_period(apic)) {
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s64 min_period = min_timer_period_us * 1000LL;
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if (apic->lapic_timer.period < min_period) {
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pr_info_ratelimited(
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"kvm: vcpu %i: requested %lld ns "
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"lapic timer period limited to %lld ns\n",
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apic->vcpu->vcpu_id,
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apic->lapic_timer.period, min_period);
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apic->lapic_timer.period = min_period;
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}
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}
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hrtimer_start(&apic->lapic_timer.timer,
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ktime_add_ns(now, apic->lapic_timer.period),
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HRTIMER_MODE_ABS_PINNED);
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apic_debug("%s: bus cycle is %" PRId64 "ns, now 0x%016"
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PRIx64 ", "
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"timer initial count 0x%x, period %lldns, "
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"expire @ 0x%016" PRIx64 ".\n", __func__,
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APIC_BUS_CYCLE_NS, ktime_to_ns(now),
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kvm_lapic_get_reg(apic, APIC_TMICT),
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apic->lapic_timer.period,
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ktime_to_ns(ktime_add_ns(now,
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apic->lapic_timer.period)));
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}
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bool kvm_lapic_hv_timer_in_use(struct kvm_vcpu *vcpu)
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{
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if (!lapic_in_kernel(vcpu))
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@ -1424,50 +1468,11 @@ EXPORT_SYMBOL_GPL(kvm_lapic_switch_to_sw_timer);
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static void start_apic_timer(struct kvm_lapic *apic)
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{
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ktime_t now;
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atomic_set(&apic->lapic_timer.pending, 0);
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if (apic_lvtt_period(apic) || apic_lvtt_oneshot(apic)) {
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/* lapic timer in oneshot or periodic mode */
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now = apic->lapic_timer.timer.base->get_time();
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apic->lapic_timer.period = (u64)kvm_lapic_get_reg(apic, APIC_TMICT)
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* APIC_BUS_CYCLE_NS * apic->divide_count;
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if (!apic->lapic_timer.period)
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return;
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/*
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* Do not allow the guest to program periodic timers with small
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* interval, since the hrtimers are not throttled by the host
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* scheduler.
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*/
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if (apic_lvtt_period(apic)) {
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s64 min_period = min_timer_period_us * 1000LL;
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if (apic->lapic_timer.period < min_period) {
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pr_info_ratelimited(
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"kvm: vcpu %i: requested %lld ns "
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"lapic timer period limited to %lld ns\n",
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apic->vcpu->vcpu_id,
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apic->lapic_timer.period, min_period);
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apic->lapic_timer.period = min_period;
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}
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}
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hrtimer_start(&apic->lapic_timer.timer,
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ktime_add_ns(now, apic->lapic_timer.period),
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HRTIMER_MODE_ABS_PINNED);
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apic_debug("%s: bus cycle is %" PRId64 "ns, now 0x%016"
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PRIx64 ", "
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"timer initial count 0x%x, period %lldns, "
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"expire @ 0x%016" PRIx64 ".\n", __func__,
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APIC_BUS_CYCLE_NS, ktime_to_ns(now),
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kvm_lapic_get_reg(apic, APIC_TMICT),
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apic->lapic_timer.period,
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ktime_to_ns(ktime_add_ns(now,
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apic->lapic_timer.period)));
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} else if (apic_lvtt_tscdeadline(apic)) {
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if (apic_lvtt_period(apic) || apic_lvtt_oneshot(apic))
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start_sw_period(apic);
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else if (apic_lvtt_tscdeadline(apic)) {
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if (!(kvm_x86_ops->set_hv_timer && start_hv_tscdeadline(apic)))
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start_sw_tscdeadline(apic);
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}
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