mrf24j40: replace magic numbers
This patch replaces some magic numbers with defines for register bits, mask and shifts. Signed-off-by: Alexander Aring <alex.aring@gmail.com> Signed-off-by: Marcel Holtmann <marcel@holtmann.org>
This commit is contained in:
Alexander Aring
Marcel Holtmann
Родитель
afaf7fdedb
Коммит
7d840545e5
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@ -26,6 +26,11 @@
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/* MRF24J40 Short Address Registers */
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#define REG_RXMCR 0x00 /* Receive MAC control */
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#define BIT_PROMI BIT(0)
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#define BIT_ERRPKT BIT(1)
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#define BIT_NOACKRSP BIT(5)
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#define BIT_PANCOORD BIT(3)
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#define REG_PANIDL 0x01 /* PAN ID (low) */
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#define REG_PANIDH 0x02 /* PAN ID (high) */
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#define REG_SADRL 0x03 /* Short address (low) */
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@ -41,6 +46,11 @@
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#define REG_RXFLUSH 0x0D
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#define REG_ORDER 0x10
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#define REG_TXMCR 0x11 /* Transmit MAC control */
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#define TXMCR_MIN_BE_SHIFT 3
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#define TXMCR_MIN_BE_MASK 0x18
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#define TXMCR_CSMA_RETRIES_SHIFT 0
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#define TXMCR_CSMA_RETRIES_MASK 0x07
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#define REG_ACKTMOUT 0x12
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#define REG_ESLOTG1 0x13
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#define REG_SYMTICKL 0x14
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@ -50,6 +60,9 @@
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#define REG_PACON2 0x18 /* Power Amplifier Control */
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#define REG_TXBCON0 0x1A
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#define REG_TXNCON 0x1B /* Transmit Normal FIFO Control */
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#define BIT_TXNTRIG BIT(0)
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#define BIT_TXNACKREQ BIT(2)
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#define REG_TXG1CON 0x1C
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#define REG_TXG2CON 0x1D
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#define REG_ESLOTG23 0x1E
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@ -70,15 +83,28 @@
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#define REG_TXSTBL 0x2E /* TX Stabilization */
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#define REG_RXSR 0x30
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#define REG_INTSTAT 0x31 /* Interrupt Status */
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#define BIT_TXNIF BIT(0)
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#define BIT_RXIF BIT(3)
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#define REG_INTCON 0x32 /* Interrupt Control */
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#define BIT_TXNIE BIT(0)
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#define BIT_RXIE BIT(3)
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#define REG_GPIO 0x33 /* GPIO */
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#define REG_TRISGPIO 0x34 /* GPIO direction */
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#define REG_SLPACK 0x35
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#define REG_RFCTL 0x36 /* RF Control Mode Register */
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#define BIT_RFRST BIT(2)
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#define REG_SECCR2 0x37
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#define REG_BBREG0 0x38
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#define REG_BBREG1 0x39 /* Baseband Registers */
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#define BIT_RXDECINV BIT(2)
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#define REG_BBREG2 0x3A /* */
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#define BBREG2_CCA_MODE_SHIFT 6
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#define BBREG2_CCA_MODE_MASK 0xc0
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#define REG_BBREG3 0x3B
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#define REG_BBREG4 0x3C
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#define REG_BBREG6 0x3E /* */
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@ -86,9 +112,32 @@
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/* MRF24J40 Long Address Registers */
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#define REG_RFCON0 0x200 /* RF Control Registers */
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#define RFCON0_CH_SHIFT 4
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#define RFCON0_CH_MASK 0xf0
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#define RFOPT_RECOMMEND 3
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#define REG_RFCON1 0x201
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#define REG_RFCON2 0x202
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#define REG_RFCON3 0x203
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#define TXPWRL_MASK 0xc0
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#define TXPWRL_SHIFT 6
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#define TXPWRL_30 0x3
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#define TXPWRL_20 0x2
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#define TXPWRL_10 0x1
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#define TXPWRL_0 0x0
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#define TXPWRS_MASK 0x38
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#define TXPWRS_SHIFT 3
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#define TXPWRS_6_3 0x7
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#define TXPWRS_4_9 0x6
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#define TXPWRS_3_7 0x5
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#define TXPWRS_2_8 0x4
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#define TXPWRS_1_9 0x3
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#define TXPWRS_1_2 0x2
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#define TXPWRS_0_5 0x1
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#define TXPWRS_0 0x0
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#define REG_RFCON5 0x205
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#define REG_RFCON6 0x206
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#define REG_RFCON7 0x207
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@ -99,6 +148,8 @@
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#define REG_RFSTATE 0x20F
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#define REG_RSSI 0x210
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#define REG_SLPCON0 0x211 /* Sleep Clock Control Registers */
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#define BIT_INTEDGE BIT(1)
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#define REG_SLPCON1 0x220
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#define REG_WAKETIMEL 0x222 /* Wake-up Time Match Value Low */
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#define REG_WAKETIMEH 0x223 /* Wake-up Time Match Value High */
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@ -493,11 +544,11 @@ static void write_tx_buf_complete(void *context)
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{
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struct mrf24j40 *devrec = context;
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__le16 fc = ieee802154_get_fc_from_skb(devrec->tx_skb);
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u8 val = 0x01;
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u8 val = BIT_TXNTRIG;
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int ret;
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if (ieee802154_is_ackreq(fc))
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val |= 0x04;
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val |= BIT_TXNACKREQ;
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devrec->tx_post_msg.complete = NULL;
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devrec->tx_post_buf[0] = MRF24J40_WRITESHORT(REG_TXNCON);
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@ -564,7 +615,7 @@ static int mrf24j40_start(struct ieee802154_hw *hw)
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/* Clear TXNIE and RXIE. Enable interrupts */
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return regmap_update_bits(devrec->regmap_short, REG_INTCON,
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0x01 | 0x08, 0x00);
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BIT_TXNIE | BIT_RXIE, 0);
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}
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static void mrf24j40_stop(struct ieee802154_hw *hw)
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@ -574,8 +625,8 @@ static void mrf24j40_stop(struct ieee802154_hw *hw)
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dev_dbg(printdev(devrec), "stop\n");
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/* Set TXNIE and RXIE. Disable Interrupts */
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regmap_update_bits(devrec->regmap_short, REG_INTCON, 0x01 | 0x08,
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0x01 | 0x08);
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regmap_update_bits(devrec->regmap_short, REG_INTCON,
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BIT_TXNIE | BIT_TXNIE, BIT_TXNIE | BIT_TXNIE);
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}
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static int mrf24j40_set_channel(struct ieee802154_hw *hw, u8 page, u8 channel)
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@ -591,17 +642,19 @@ static int mrf24j40_set_channel(struct ieee802154_hw *hw, u8 page, u8 channel)
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WARN_ON(channel > MRF24J40_CHAN_MAX);
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/* Set Channel TODO */
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val = (channel-11) << 4 | 0x03;
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ret = regmap_update_bits(devrec->regmap_long, REG_RFCON0, 0xf0, val);
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val = (channel - 11) << RFCON0_CH_SHIFT | RFOPT_RECOMMEND;
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ret = regmap_update_bits(devrec->regmap_long, REG_RFCON0,
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RFCON0_CH_MASK, val);
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if (ret)
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return ret;
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/* RF Reset */
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ret = regmap_update_bits(devrec->regmap_short, REG_RFCTL, 0x04, 0x04);
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ret = regmap_update_bits(devrec->regmap_short, REG_RFCTL, BIT_RFRST,
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BIT_RFRST);
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if (ret)
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return ret;
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ret = regmap_update_bits(devrec->regmap_short, REG_RFCTL, 0x04, 0x00);
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ret = regmap_update_bits(devrec->regmap_short, REG_RFCTL, BIT_RFRST, 0);
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if (!ret)
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udelay(SET_CHANNEL_DELAY_US); /* per datasheet */
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@ -664,11 +717,11 @@ static int mrf24j40_filter(struct ieee802154_hw *hw,
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int ret;
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if (filt->pan_coord)
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val = 0x8;
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val = BIT_PANCOORD;
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else
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val = 0x0;
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ret = regmap_update_bits(devrec->regmap_short, REG_RXMCR, 0x8,
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val);
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val = 0;
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ret = regmap_update_bits(devrec->regmap_short, REG_RXMCR,
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BIT_PANCOORD, val);
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if (ret)
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return ret;
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@ -772,7 +825,7 @@ static int mrf24j40_handle_rx(struct mrf24j40 *devrec)
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devrec->rx_msg.complete = mrf24j40_handle_rx_read_len;
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devrec->rx_trx.len = 2;
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devrec->rx_buf[0] = MRF24J40_WRITESHORT(REG_BBREG1);
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devrec->rx_buf[1] = 0x04; /* SET RXDECINV */
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devrec->rx_buf[1] = BIT_RXDECINV; /* SET RXDECINV */
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return spi_async(devrec->spi, &devrec->rx_msg);
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}
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@ -785,11 +838,13 @@ mrf24j40_csma_params(struct ieee802154_hw *hw, u8 min_be, u8 max_be,
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u8 val;
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/* min_be */
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val = min_be << 3;
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val = min_be << TXMCR_MIN_BE_SHIFT;
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/* csma backoffs */
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val |= retries;
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val |= retries << TXMCR_CSMA_RETRIES_SHIFT;
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return regmap_update_bits(devrec->regmap_short, REG_TXMCR, 0x1f, val);
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return regmap_update_bits(devrec->regmap_short, REG_TXMCR,
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TXMCR_MIN_BE_MASK | TXMCR_CSMA_RETRIES_MASK,
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val);
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}
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static int mrf24j40_set_cca_mode(struct ieee802154_hw *hw,
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@ -819,8 +874,9 @@ static int mrf24j40_set_cca_mode(struct ieee802154_hw *hw,
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return -EINVAL;
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}
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return regmap_update_bits(devrec->regmap_short, REG_BBREG2, 0xc0,
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val << 6);
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return regmap_update_bits(devrec->regmap_short, REG_BBREG2,
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BBREG2_CCA_MODE_MASK,
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val << BBREG2_CCA_MODE_SHIFT);
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}
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/* array for representing ed levels */
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@ -878,16 +934,16 @@ static int mrf24j40_set_txpower(struct ieee802154_hw *hw, s32 mbm)
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u8 val;
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if (0 >= mbm && mbm > -1000) {
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val = 0;
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val = TXPWRL_0 << TXPWRL_SHIFT;
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small_scale = mbm;
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} else if (-1000 >= mbm && mbm > -2000) {
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val = 0x40;
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val = TXPWRL_10 << TXPWRL_SHIFT;
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small_scale = mbm + 1000;
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} else if (-2000 >= mbm && mbm > -3000) {
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val = 0x80;
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val = TXPWRL_20 << TXPWRL_SHIFT;
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small_scale = mbm + 2000;
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} else if (-3000 >= mbm && mbm > -4000) {
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val = 0xc0;
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val = TXPWRL_30 << TXPWRL_SHIFT;
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small_scale = mbm + 3000;
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} else {
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return -EINVAL;
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@ -895,33 +951,35 @@ static int mrf24j40_set_txpower(struct ieee802154_hw *hw, s32 mbm)
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switch (small_scale) {
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case 0:
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val |= (TXPWRS_0 << TXPWRS_SHIFT);
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break;
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case -50:
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val |= 0x08;
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val |= (TXPWRS_0_5 << TXPWRS_SHIFT);
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break;
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case -120:
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val |= 0x10;
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val |= (TXPWRS_1_2 << TXPWRS_SHIFT);
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break;
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case -190:
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val |= 0x18;
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val |= (TXPWRS_1_9 << TXPWRS_SHIFT);
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break;
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case -280:
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val |= 0x20;
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val |= (TXPWRS_2_8 << TXPWRS_SHIFT);
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break;
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case -370:
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val |= 0x28;
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val |= (TXPWRS_3_7 << TXPWRS_SHIFT);
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break;
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case -490:
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val |= 0x30;
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val |= (TXPWRS_4_9 << TXPWRS_SHIFT);
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break;
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case -630:
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val |= 0x38;
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val |= (TXPWRS_6_3 << TXPWRS_SHIFT);
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break;
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default:
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return -EINVAL;
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}
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return regmap_update_bits(devrec->regmap_long, REG_RFCON3, 0xf8, val);
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return regmap_update_bits(devrec->regmap_long, REG_RFCON3,
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TXPWRL_MASK | TXPWRS_MASK, val);
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}
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static int mrf24j40_set_promiscuous_mode(struct ieee802154_hw *hw, bool on)
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@ -931,12 +989,14 @@ static int mrf24j40_set_promiscuous_mode(struct ieee802154_hw *hw, bool on)
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if (on) {
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/* set PROMI, ERRPKT and NOACKRSP */
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ret = regmap_update_bits(devrec->regmap_short, REG_RXMCR, 0x23,
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0x23);
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ret = regmap_update_bits(devrec->regmap_short, REG_RXMCR,
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BIT_PROMI | BIT_ERRPKT | BIT_NOACKRSP,
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BIT_PROMI | BIT_ERRPKT | BIT_NOACKRSP);
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} else {
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/* clear PROMI, ERRPKT and NOACKRSP */
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ret = regmap_update_bits(devrec->regmap_short, REG_RXMCR, 0x23,
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0x00);
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ret = regmap_update_bits(devrec->regmap_short, REG_RXMCR,
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BIT_PROMI | BIT_ERRPKT | BIT_NOACKRSP,
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0);
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}
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return ret;
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@ -965,11 +1025,11 @@ static void mrf24j40_intstat_complete(void *context)
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enable_irq(devrec->spi->irq);
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/* Check for TX complete */
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if (intstat & 0x1)
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if (intstat & BIT_TXNIF)
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ieee802154_xmit_complete(devrec->hw, devrec->tx_skb, false);
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/* Check for Rx */
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if (intstat & 0x8)
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if (intstat & BIT_RXIF)
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mrf24j40_handle_rx(devrec);
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}
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@ -1095,7 +1155,7 @@ static int mrf24j40_hw_init(struct mrf24j40 *devrec)
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case IRQ_TYPE_LEVEL_HIGH:
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/* set interrupt polarity to rising */
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ret = regmap_update_bits(devrec->regmap_long, REG_SLPCON0,
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0x02, 0x02);
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BIT_INTEDGE, BIT_INTEDGE);
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if (ret)
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goto err_ret;
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break;
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