ARM: 6185/1: AT91: PM: dual ram controller support
This rework allows to address tow memory controllers. AT91SAM9263 and AT91SAM9G45 family have tow SDRAM or DDR/SDRAM controllers. Power management should take care of this. This patch modify the way RAM IP header files are implemented to allow access to registers of both controllers ; it also adds some macros. We also modify the power management files to use those modified header files. Slow clock (assembly) and regular power management functions are synchronized for setting of RAM self-refresh procedure: (lpr & ~AT91_DDRSDRC_LPCB) | AT91_DDRSDRC_LPCB_SELF_REFRESH Note that AT91RM9200 is not impacted by this modification. Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com> Acked-by: Andrew Victor <linux@maxim.org.za> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
This commit is contained in:
Nicolas Ferre
Russell King
Родитель
5f9f0a412f
Коммит
7dca3343fc
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@ -84,7 +84,7 @@
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*/
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#define AT91_ECC (0xffffe200 - AT91_BASE_SYS)
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#define AT91_BCRAMC (0xffffe400 - AT91_BASE_SYS)
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#define AT91_DDRSDRC (0xffffe600 - AT91_BASE_SYS)
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#define AT91_DDRSDRC0 (0xffffe600 - AT91_BASE_SYS)
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#define AT91_SMC (0xffffe800 - AT91_BASE_SYS)
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#define AT91_MATRIX (0xffffea00 - AT91_BASE_SYS)
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#define AT91_CCFG (0xffffeb10 - AT91_BASE_SYS)
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@ -15,7 +15,7 @@
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#ifndef AT91CAP9_DDRSDR_H
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#define AT91CAP9_DDRSDR_H
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#define AT91_DDRSDRC_MR (AT91_DDRSDRC + 0x00) /* Mode Register */
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#define AT91_DDRSDRC_MR 0x00 /* Mode Register */
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#define AT91_DDRSDRC_MODE (0xf << 0) /* Command Mode */
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#define AT91_DDRSDRC_MODE_NORMAL 0
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#define AT91_DDRSDRC_MODE_NOP 1
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@ -25,10 +25,10 @@
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#define AT91_DDRSDRC_MODE_EXT_LMR 5
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#define AT91_DDRSDRC_MODE_DEEP 6
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#define AT91_DDRSDRC_RTR (AT91_DDRSDRC + 0x04) /* Refresh Timer Register */
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#define AT91_DDRSDRC_RTR 0x04 /* Refresh Timer Register */
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#define AT91_DDRSDRC_COUNT (0xfff << 0) /* Refresh Timer Counter */
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#define AT91_DDRSDRC_CR (AT91_DDRSDRC + 0x08) /* Configuration Register */
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#define AT91_DDRSDRC_CR 0x08 /* Configuration Register */
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#define AT91_DDRSDRC_NC (3 << 0) /* Number of Column Bits */
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#define AT91_DDRSDRC_NC_SDR8 (0 << 0)
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#define AT91_DDRSDRC_NC_SDR9 (1 << 0)
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@ -49,7 +49,7 @@
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#define AT91_DDRSDRC_DLL (1 << 7) /* Reset DLL */
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#define AT91_DDRSDRC_DICDS (1 << 8) /* Output impedance control */
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#define AT91_DDRSDRC_T0PR (AT91_DDRSDRC + 0x0C) /* Timing 0 Register */
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#define AT91_DDRSDRC_T0PR 0x0C /* Timing 0 Register */
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#define AT91_DDRSDRC_TRAS (0xf << 0) /* Active to Precharge delay */
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#define AT91_DDRSDRC_TRCD (0xf << 4) /* Row to Column delay */
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#define AT91_DDRSDRC_TWR (0xf << 8) /* Write recovery delay */
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@ -59,13 +59,13 @@
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#define AT91_DDRSDRC_TWTR (1 << 24) /* Internal Write to Read delay */
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#define AT91_DDRSDRC_TMRD (0xf << 28) /* Load mode to active/refresh delay */
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#define AT91_DDRSDRC_T1PR (AT91_DDRSDRC + 0x10) /* Timing 1 Register */
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#define AT91_DDRSDRC_T1PR 0x10 /* Timing 1 Register */
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#define AT91_DDRSDRC_TRFC (0x1f << 0) /* Row Cycle Delay */
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#define AT91_DDRSDRC_TXSNR (0xff << 8) /* Exit self-refresh to non-read */
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#define AT91_DDRSDRC_TXSRD (0xff << 16) /* Exit self-refresh to read */
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#define AT91_DDRSDRC_TXP (0xf << 24) /* Exit power-down delay */
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#define AT91_DDRSDRC_LPR (AT91_DDRSDRC + 0x18) /* Low Power Register */
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#define AT91_DDRSDRC_LPR 0x18 /* Low Power Register */
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#define AT91_DDRSDRC_LPCB (3 << 0) /* Low-power Configurations */
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#define AT91_DDRSDRC_LPCB_DISABLE 0
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#define AT91_DDRSDRC_LPCB_SELF_REFRESH 1
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@ -80,14 +80,14 @@
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#define AT91_DDRSDRC_TIMEOUT_64_CLK_CYCLES (1 << 12)
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#define AT91_DDRSDRC_TIMEOUT_128_CLK_CYCLES (2 << 12)
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#define AT91_DDRSDRC_MDR (AT91_DDRSDRC + 0x1C) /* Memory Device Register */
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#define AT91_DDRSDRC_MDR 0x1C /* Memory Device Register */
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#define AT91_DDRSDRC_MD (3 << 0) /* Memory Device Type */
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#define AT91_DDRSDRC_MD_SDR 0
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#define AT91_DDRSDRC_MD_LOW_POWER_SDR 1
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#define AT91_DDRSDRC_MD_DDR 2
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#define AT91_DDRSDRC_MD_LOW_POWER_DDR 3
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#define AT91_DDRSDRC_DLLR (AT91_DDRSDRC + 0x20) /* DLL Information Register */
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#define AT91_DDRSDRC_DLLR 0x20 /* DLL Information Register */
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#define AT91_DDRSDRC_MDINC (1 << 0) /* Master Delay increment */
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#define AT91_DDRSDRC_MDDEC (1 << 1) /* Master Delay decrement */
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#define AT91_DDRSDRC_MDOVF (1 << 2) /* Master Delay Overflow */
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@ -98,5 +98,11 @@
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#define AT91_DDRSDRC_SDVAL (0xff << 16) /* Slave Delay value */
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#define AT91_DDRSDRC_SDCVAL (0xff << 24) /* Slave Delay Correction value */
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/* Register access macros */
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#define at91_ramc_read(num, reg) \
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at91_sys_read(AT91_DDRSDRC##num + reg)
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#define at91_ramc_write(num, reg, value) \
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at91_sys_write(AT91_DDRSDRC##num + reg, value)
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#endif
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@ -84,7 +84,7 @@
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* System Peripherals (offset from AT91_BASE_SYS)
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*/
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#define AT91_ECC (0xffffe800 - AT91_BASE_SYS)
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#define AT91_SDRAMC (0xffffea00 - AT91_BASE_SYS)
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#define AT91_SDRAMC0 (0xffffea00 - AT91_BASE_SYS)
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#define AT91_SMC (0xffffec00 - AT91_BASE_SYS)
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#define AT91_MATRIX (0xffffee00 - AT91_BASE_SYS)
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#define AT91_CCFG (0xffffef10 - AT91_BASE_SYS)
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@ -68,7 +68,7 @@
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/*
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* System Peripherals (offset from AT91_BASE_SYS)
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*/
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#define AT91_SDRAMC (0xffffea00 - AT91_BASE_SYS)
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#define AT91_SDRAMC0 (0xffffea00 - AT91_BASE_SYS)
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#define AT91_SMC (0xffffec00 - AT91_BASE_SYS)
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#define AT91_MATRIX (0xffffee00 - AT91_BASE_SYS)
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#define AT91_AIC (0xfffff000 - AT91_BASE_SYS)
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@ -0,0 +1,130 @@
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/*
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* Header file for the Atmel DDR/SDR SDRAM Controller
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*
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* Copyright (C) 2010 Atmel Corporation
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* Nicolas Ferre <nicolas.ferre@atmel.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*/
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#ifndef AT91SAM9_DDRSDR_H
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#define AT91SAM9_DDRSDR_H
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#define AT91_DDRSDRC_MR 0x00 /* Mode Register */
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#define AT91_DDRSDRC_MODE (0x7 << 0) /* Command Mode */
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#define AT91_DDRSDRC_MODE_NORMAL 0
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#define AT91_DDRSDRC_MODE_NOP 1
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#define AT91_DDRSDRC_MODE_PRECHARGE 2
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#define AT91_DDRSDRC_MODE_LMR 3
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#define AT91_DDRSDRC_MODE_REFRESH 4
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#define AT91_DDRSDRC_MODE_EXT_LMR 5
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#define AT91_DDRSDRC_MODE_DEEP 6
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#define AT91_DDRSDRC_RTR 0x04 /* Refresh Timer Register */
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#define AT91_DDRSDRC_COUNT (0xfff << 0) /* Refresh Timer Counter */
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#define AT91_DDRSDRC_CR 0x08 /* Configuration Register */
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#define AT91_DDRSDRC_NC (3 << 0) /* Number of Column Bits */
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#define AT91_DDRSDRC_NC_SDR8 (0 << 0)
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#define AT91_DDRSDRC_NC_SDR9 (1 << 0)
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#define AT91_DDRSDRC_NC_SDR10 (2 << 0)
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#define AT91_DDRSDRC_NC_SDR11 (3 << 0)
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#define AT91_DDRSDRC_NC_DDR9 (0 << 0)
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#define AT91_DDRSDRC_NC_DDR10 (1 << 0)
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#define AT91_DDRSDRC_NC_DDR11 (2 << 0)
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#define AT91_DDRSDRC_NC_DDR12 (3 << 0)
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#define AT91_DDRSDRC_NR (3 << 2) /* Number of Row Bits */
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#define AT91_DDRSDRC_NR_11 (0 << 2)
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#define AT91_DDRSDRC_NR_12 (1 << 2)
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#define AT91_DDRSDRC_NR_13 (2 << 2)
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#define AT91_DDRSDRC_NR_14 (3 << 2)
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#define AT91_DDRSDRC_CAS (7 << 4) /* CAS Latency */
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#define AT91_DDRSDRC_CAS_2 (2 << 4)
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#define AT91_DDRSDRC_CAS_3 (3 << 4)
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#define AT91_DDRSDRC_CAS_25 (6 << 4)
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#define AT91_DDRSDRC_RST_DLL (1 << 7) /* Reset DLL */
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#define AT91_DDRSDRC_DICDS (1 << 8) /* Output impedance control */
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#define AT91_DDRSDRC_DIS_DLL (1 << 9) /* Disable DLL */
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#define AT91_DDRSDRC_OCD (1 << 12) /* Off-Chip Driver */
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#define AT91_DDRSDRC_DQMS (1 << 16) /* Mask Data is Shared */
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#define AT91_DDRSDRC_ACTBST (1 << 18) /* Active Bank X to Burst Stop Read Access Bank Y */
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#define AT91_DDRSDRC_T0PR 0x0C /* Timing 0 Register */
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#define AT91_DDRSDRC_TRAS (0xf << 0) /* Active to Precharge delay */
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#define AT91_DDRSDRC_TRCD (0xf << 4) /* Row to Column delay */
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#define AT91_DDRSDRC_TWR (0xf << 8) /* Write recovery delay */
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#define AT91_DDRSDRC_TRC (0xf << 12) /* Row cycle delay */
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#define AT91_DDRSDRC_TRP (0xf << 16) /* Row precharge delay */
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#define AT91_DDRSDRC_TRRD (0xf << 20) /* Active BankA to BankB */
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#define AT91_DDRSDRC_TWTR (0x7 << 24) /* Internal Write to Read delay */
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#define AT91_DDRSDRC_RED_WRRD (0x1 << 27) /* Reduce Write to Read Delay */
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#define AT91_DDRSDRC_TMRD (0xf << 28) /* Load mode to active/refresh delay */
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#define AT91_DDRSDRC_T1PR 0x10 /* Timing 1 Register */
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#define AT91_DDRSDRC_TRFC (0x1f << 0) /* Row Cycle Delay */
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#define AT91_DDRSDRC_TXSNR (0xff << 8) /* Exit self-refresh to non-read */
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#define AT91_DDRSDRC_TXSRD (0xff << 16) /* Exit self-refresh to read */
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#define AT91_DDRSDRC_TXP (0xf << 24) /* Exit power-down delay */
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#define AT91_DDRSDRC_T2PR 0x14 /* Timing 2 Register */
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#define AT91_DDRSDRC_TXARD (0xf << 0) /* Exit active power down delay to read command in mode "Fast Exit" */
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#define AT91_DDRSDRC_TXARDS (0xf << 4) /* Exit active power down delay to read command in mode "Slow Exit" */
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#define AT91_DDRSDRC_TRPA (0xf << 8) /* Row Precharge All delay */
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#define AT91_DDRSDRC_TRTP (0x7 << 12) /* Read to Precharge delay */
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#define AT91_DDRSDRC_LPR 0x1C /* Low Power Register */
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#define AT91_DDRSDRC_LPCB (3 << 0) /* Low-power Configurations */
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#define AT91_DDRSDRC_LPCB_DISABLE 0
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#define AT91_DDRSDRC_LPCB_SELF_REFRESH 1
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#define AT91_DDRSDRC_LPCB_POWER_DOWN 2
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#define AT91_DDRSDRC_LPCB_DEEP_POWER_DOWN 3
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#define AT91_DDRSDRC_CLKFR (1 << 2) /* Clock Frozen */
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#define AT91_DDRSDRC_PASR (7 << 4) /* Partial Array Self Refresh */
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#define AT91_DDRSDRC_TCSR (3 << 8) /* Temperature Compensated Self Refresh */
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#define AT91_DDRSDRC_DS (3 << 10) /* Drive Strength */
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#define AT91_DDRSDRC_TIMEOUT (3 << 12) /* Time to define when Low Power Mode is enabled */
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#define AT91_DDRSDRC_TIMEOUT_0_CLK_CYCLES (0 << 12)
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#define AT91_DDRSDRC_TIMEOUT_64_CLK_CYCLES (1 << 12)
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#define AT91_DDRSDRC_TIMEOUT_128_CLK_CYCLES (2 << 12)
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#define AT91_DDRSDRC_APDE (1 << 16) /* Active power down exit time */
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#define AT91_DDRSDRC_UPD_MR (3 << 20) /* Update load mode register and extended mode register */
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#define AT91_DDRSDRC_MDR 0x20 /* Memory Device Register */
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#define AT91_DDRSDRC_MD (3 << 0) /* Memory Device Type */
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#define AT91_DDRSDRC_MD_SDR 0
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#define AT91_DDRSDRC_MD_LOW_POWER_SDR 1
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#define AT91_DDRSDRC_MD_LOW_POWER_DDR 3
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#define AT91_DDRSDRC_MD_DDR2 6
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#define AT91_DDRSDRC_DBW (1 << 4) /* Data Bus Width */
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#define AT91_DDRSDRC_DBW_32BITS (0 << 4)
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#define AT91_DDRSDRC_DBW_16BITS (1 << 4)
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#define AT91_DDRSDRC_DLL 0x24 /* DLL Information Register */
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#define AT91_DDRSDRC_MDINC (1 << 0) /* Master Delay increment */
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#define AT91_DDRSDRC_MDDEC (1 << 1) /* Master Delay decrement */
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#define AT91_DDRSDRC_MDOVF (1 << 2) /* Master Delay Overflow */
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#define AT91_DDRSDRC_MDVAL (0xff << 8) /* Master Delay value */
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#define AT91_DDRSDRC_HS 0x2C /* High Speed Register */
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#define AT91_DDRSDRC_DIS_ATCP_RD (1 << 2) /* Anticip read access is disabled */
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#define AT91_DDRSDRC_DELAY(n) (0x30 + (0x4 * (n))) /* Delay I/O Register n */
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#define AT91_DDRSDRC_WPMR 0xE4 /* Write Protect Mode Register */
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#define AT91_DDRSDRC_WP (1 << 0) /* Write protect enable */
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#define AT91_DDRSDRC_WPKEY (0xffffff << 8) /* Write protect key */
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#define AT91_DDRSDRC_KEY (0x444452 << 8) /* Write protect key = "DDR" */
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#define AT91_DDRSDRC_WPSR 0xE8 /* Write Protect Status Register */
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#define AT91_DDRSDRC_WPVS (1 << 0) /* Write protect violation status */
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#define AT91_DDRSDRC_WPVSRC (0xffff << 8) /* Write protect violation source */
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/* Register access macros */
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#define at91_ramc_read(num, reg) \
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at91_sys_read(AT91_DDRSDRC##num + reg)
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#define at91_ramc_write(num, reg, value) \
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at91_sys_write(AT91_DDRSDRC##num + reg, value)
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#endif
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@ -17,7 +17,7 @@
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#define AT91SAM9_SDRAMC_H
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/* SDRAM Controller (SDRAMC) registers */
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#define AT91_SDRAMC_MR (AT91_SDRAMC + 0x00) /* SDRAM Controller Mode Register */
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#define AT91_SDRAMC_MR 0x00 /* SDRAM Controller Mode Register */
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#define AT91_SDRAMC_MODE (0xf << 0) /* Command Mode */
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#define AT91_SDRAMC_MODE_NORMAL 0
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#define AT91_SDRAMC_MODE_NOP 1
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@ -27,10 +27,10 @@
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#define AT91_SDRAMC_MODE_EXT_LMR 5
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#define AT91_SDRAMC_MODE_DEEP 6
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#define AT91_SDRAMC_TR (AT91_SDRAMC + 0x04) /* SDRAM Controller Refresh Timer Register */
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#define AT91_SDRAMC_TR 0x04 /* SDRAM Controller Refresh Timer Register */
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#define AT91_SDRAMC_COUNT (0xfff << 0) /* Refresh Timer Counter */
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#define AT91_SDRAMC_CR (AT91_SDRAMC + 0x08) /* SDRAM Controller Configuration Register */
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#define AT91_SDRAMC_CR 0x08 /* SDRAM Controller Configuration Register */
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#define AT91_SDRAMC_NC (3 << 0) /* Number of Column Bits */
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#define AT91_SDRAMC_NC_8 (0 << 0)
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#define AT91_SDRAMC_NC_9 (1 << 0)
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@ -57,7 +57,7 @@
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#define AT91_SDRAMC_TRAS (0xf << 24) /* Active to Precharge Delay */
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#define AT91_SDRAMC_TXSR (0xf << 28) /* Exit Self Refresh to Active Delay */
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#define AT91_SDRAMC_LPR (AT91_SDRAMC + 0x10) /* SDRAM Controller Low Power Register */
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#define AT91_SDRAMC_LPR 0x10 /* SDRAM Controller Low Power Register */
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#define AT91_SDRAMC_LPCB (3 << 0) /* Low-power Configurations */
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#define AT91_SDRAMC_LPCB_DISABLE 0
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#define AT91_SDRAMC_LPCB_SELF_REFRESH 1
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@ -71,16 +71,21 @@
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#define AT91_SDRAMC_TIMEOUT_64_CLK_CYCLES (1 << 12)
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#define AT91_SDRAMC_TIMEOUT_128_CLK_CYCLES (2 << 12)
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#define AT91_SDRAMC_IER (AT91_SDRAMC + 0x14) /* SDRAM Controller Interrupt Enable Register */
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#define AT91_SDRAMC_IDR (AT91_SDRAMC + 0x18) /* SDRAM Controller Interrupt Disable Register */
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#define AT91_SDRAMC_IMR (AT91_SDRAMC + 0x1C) /* SDRAM Controller Interrupt Mask Register */
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#define AT91_SDRAMC_ISR (AT91_SDRAMC + 0x20) /* SDRAM Controller Interrupt Status Register */
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#define AT91_SDRAMC_IER 0x14 /* SDRAM Controller Interrupt Enable Register */
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#define AT91_SDRAMC_IDR 0x18 /* SDRAM Controller Interrupt Disable Register */
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#define AT91_SDRAMC_IMR 0x1C /* SDRAM Controller Interrupt Mask Register */
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#define AT91_SDRAMC_ISR 0x20 /* SDRAM Controller Interrupt Status Register */
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#define AT91_SDRAMC_RES (1 << 0) /* Refresh Error Status */
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#define AT91_SDRAMC_MDR (AT91_SDRAMC + 0x24) /* SDRAM Memory Device Register */
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#define AT91_SDRAMC_MDR 0x24 /* SDRAM Memory Device Register */
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#define AT91_SDRAMC_MD (3 << 0) /* Memory Device Type */
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#define AT91_SDRAMC_MD_SDRAM 0
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#define AT91_SDRAMC_MD_LOW_POWER_SDRAM 1
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/* Register access macros */
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#define at91_ramc_read(num, reg) \
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at91_sys_read(AT91_SDRAMC##num + reg)
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#define at91_ramc_write(num, reg, value) \
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at91_sys_write(AT91_SDRAMC##num + reg, value)
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#endif
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@ -74,7 +74,7 @@
|
|||
*/
|
||||
#define AT91_DMA (0xffffe600 - AT91_BASE_SYS)
|
||||
#define AT91_ECC (0xffffe800 - AT91_BASE_SYS)
|
||||
#define AT91_SDRAMC (0xffffea00 - AT91_BASE_SYS)
|
||||
#define AT91_SDRAMC0 (0xffffea00 - AT91_BASE_SYS)
|
||||
#define AT91_SMC (0xffffec00 - AT91_BASE_SYS)
|
||||
#define AT91_MATRIX (0xffffee00 - AT91_BASE_SYS)
|
||||
#define AT91_CCFG (0xffffef10 - AT91_BASE_SYS)
|
||||
|
|
|
|||
|
|
@ -30,14 +30,50 @@ static inline u32 sdram_selfrefresh_enable(void)
|
|||
{
|
||||
u32 saved_lpr, lpr;
|
||||
|
||||
saved_lpr = at91_sys_read(AT91_DDRSDRC_LPR);
|
||||
saved_lpr = at91_ramc_read(0, AT91_DDRSDRC_LPR);
|
||||
|
||||
lpr = saved_lpr & ~AT91_DDRSDRC_LPCB;
|
||||
at91_sys_write(AT91_DDRSDRC_LPR, lpr | AT91_DDRSDRC_LPCB_SELF_REFRESH);
|
||||
at91_ramc_write(0, AT91_DDRSDRC_LPR, lpr | AT91_DDRSDRC_LPCB_SELF_REFRESH);
|
||||
return saved_lpr;
|
||||
}
|
||||
|
||||
#define sdram_selfrefresh_disable(saved_lpr) at91_sys_write(AT91_DDRSDRC_LPR, saved_lpr)
|
||||
#define sdram_selfrefresh_disable(saved_lpr) at91_ramc_write(0, AT91_DDRSDRC_LPR, saved_lpr)
|
||||
|
||||
#elif defined(CONFIG_ARCH_AT91SAM9G45)
|
||||
#include <mach/at91sam9_ddrsdr.h>
|
||||
|
||||
/* We manage both DDRAM/SDRAM controllers, we need more than one value to
|
||||
* remember.
|
||||
*/
|
||||
static u32 saved_lpr1;
|
||||
|
||||
static inline u32 sdram_selfrefresh_enable(void)
|
||||
{
|
||||
/* Those tow values allow us to delay self-refresh activation
|
||||
* to the maximum. */
|
||||
u32 lpr0, lpr1;
|
||||
u32 saved_lpr0;
|
||||
|
||||
saved_lpr1 = at91_ramc_read(1, AT91_DDRSDRC_LPR);
|
||||
lpr1 = saved_lpr1 & ~AT91_DDRSDRC_LPCB;
|
||||
lpr1 |= AT91_DDRSDRC_LPCB_SELF_REFRESH;
|
||||
|
||||
saved_lpr0 = at91_ramc_read(0, AT91_DDRSDRC_LPR);
|
||||
lpr0 = saved_lpr0 & ~AT91_DDRSDRC_LPCB;
|
||||
lpr0 |= AT91_DDRSDRC_LPCB_SELF_REFRESH;
|
||||
|
||||
/* self-refresh mode now */
|
||||
at91_ramc_write(0, AT91_DDRSDRC_LPR, lpr0);
|
||||
at91_ramc_write(1, AT91_DDRSDRC_LPR, lpr1);
|
||||
|
||||
return saved_lpr0;
|
||||
}
|
||||
|
||||
#define sdram_selfrefresh_disable(saved_lpr0) \
|
||||
do { \
|
||||
at91_ramc_write(0, AT91_DDRSDRC_LPR, saved_lpr0); \
|
||||
at91_ramc_write(1, AT91_DDRSDRC_LPR, saved_lpr1); \
|
||||
} while (0)
|
||||
|
||||
#else
|
||||
#include <mach/at91sam9_sdramc.h>
|
||||
|
|
@ -47,7 +83,6 @@ static inline u32 sdram_selfrefresh_enable(void)
|
|||
* FIXME either or both the SDRAM controllers (EB0, EB1) might be in use;
|
||||
* handle those cases both here and in the Suspend-To-RAM support.
|
||||
*/
|
||||
#define AT91_SDRAMC AT91_SDRAMC0
|
||||
#warning Assuming EB1 SDRAM controller is *NOT* used
|
||||
#endif
|
||||
|
||||
|
|
@ -55,13 +90,13 @@ static inline u32 sdram_selfrefresh_enable(void)
|
|||
{
|
||||
u32 saved_lpr, lpr;
|
||||
|
||||
saved_lpr = at91_sys_read(AT91_SDRAMC_LPR);
|
||||
saved_lpr = at91_ramc_read(0, AT91_SDRAMC_LPR);
|
||||
|
||||
lpr = saved_lpr & ~AT91_SDRAMC_LPCB;
|
||||
at91_sys_write(AT91_SDRAMC_LPR, lpr | AT91_SDRAMC_LPCB_SELF_REFRESH);
|
||||
at91_ramc_write(0, AT91_SDRAMC_LPR, lpr | AT91_SDRAMC_LPCB_SELF_REFRESH);
|
||||
return saved_lpr;
|
||||
}
|
||||
|
||||
#define sdram_selfrefresh_disable(saved_lpr) at91_sys_write(AT91_SDRAMC_LPR, saved_lpr)
|
||||
#define sdram_selfrefresh_disable(saved_lpr) at91_ramc_write(0, AT91_SDRAMC_LPR, saved_lpr)
|
||||
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -16,10 +16,12 @@
|
|||
#include <mach/hardware.h>
|
||||
#include <mach/at91_pmc.h>
|
||||
|
||||
#ifdef CONFIG_ARCH_AT91RM9200
|
||||
#if defined(CONFIG_ARCH_AT91RM9200)
|
||||
#include <mach/at91rm9200_mc.h>
|
||||
#elif defined(CONFIG_ARCH_AT91CAP9)
|
||||
#include <mach/at91cap9_ddrsdr.h>
|
||||
#elif defined(CONFIG_ARCH_AT91SAM9G45)
|
||||
#include <mach/at91sam9_ddrsdr.h>
|
||||
#else
|
||||
#include <mach/at91sam9_sdramc.h>
|
||||
#endif
|
||||
|
|
@ -30,7 +32,6 @@
|
|||
* FIXME either or both the SDRAM controllers (EB0, EB1) might be in use;
|
||||
* handle those cases both here and in the Suspend-To-RAM support.
|
||||
*/
|
||||
#define AT91_SDRAMC AT91_SDRAMC0
|
||||
#warning Assuming EB1 SDRAM controller is *NOT* used
|
||||
#endif
|
||||
|
||||
|
|
@ -113,12 +114,14 @@ ENTRY(at91_slow_clock)
|
|||
/*
|
||||
* Register usage:
|
||||
* R1 = Base address of AT91_PMC
|
||||
* R2 = Base address of AT91_SDRAMC (or AT91_SYS on AT91RM9200)
|
||||
* R2 = Base address of RAM Controller (SDRAM, DDRSDR, or AT91_SYS)
|
||||
* R3 = temporary register
|
||||
* R4 = temporary register
|
||||
* R5 = Base address of second RAM Controller or 0 if not present
|
||||
*/
|
||||
ldr r1, .at91_va_base_pmc
|
||||
ldr r2, .at91_va_base_sdramc
|
||||
ldr r5, .at91_va_base_ramc1
|
||||
|
||||
/* Drain write buffer */
|
||||
mcr p15, 0, r0, c7, c10, 4
|
||||
|
|
@ -127,20 +130,33 @@ ENTRY(at91_slow_clock)
|
|||
/* Put SDRAM in self-refresh mode */
|
||||
mov r3, #1
|
||||
str r3, [r2, #AT91_SDRAMC_SRR]
|
||||
#elif defined(CONFIG_ARCH_AT91CAP9)
|
||||
/* Enable SDRAM self-refresh mode */
|
||||
ldr r3, [r2, #AT91_DDRSDRC_LPR - AT91_DDRSDRC]
|
||||
str r3, .saved_sam9_lpr
|
||||
#elif defined(CONFIG_ARCH_AT91CAP9) \
|
||||
|| defined(CONFIG_ARCH_AT91SAM9G45)
|
||||
|
||||
mov r3, #AT91_DDRSDRC_LPCB_SELF_REFRESH
|
||||
str r3, [r2, #AT91_DDRSDRC_LPR - AT91_DDRSDRC]
|
||||
/* prepare for DDRAM self-refresh mode */
|
||||
ldr r3, [r2, #AT91_DDRSDRC_LPR]
|
||||
str r3, .saved_sam9_lpr
|
||||
bic r3, #AT91_DDRSDRC_LPCB
|
||||
orr r3, #AT91_DDRSDRC_LPCB_SELF_REFRESH
|
||||
|
||||
/* figure out if we use the second ram controller */
|
||||
cmp r5, #0
|
||||
ldrne r4, [r5, #AT91_DDRSDRC_LPR]
|
||||
strne r4, .saved_sam9_lpr1
|
||||
bicne r4, #AT91_DDRSDRC_LPCB
|
||||
orrne r4, #AT91_DDRSDRC_LPCB_SELF_REFRESH
|
||||
|
||||
/* Enable DDRAM self-refresh mode */
|
||||
str r3, [r2, #AT91_DDRSDRC_LPR]
|
||||
strne r4, [r5, #AT91_DDRSDRC_LPR]
|
||||
#else
|
||||
/* Enable SDRAM self-refresh mode */
|
||||
ldr r3, [r2, #AT91_SDRAMC_LPR - AT91_SDRAMC]
|
||||
ldr r3, [r2, #AT91_SDRAMC_LPR]
|
||||
str r3, .saved_sam9_lpr
|
||||
|
||||
mov r3, #AT91_SDRAMC_LPCB_SELF_REFRESH
|
||||
str r3, [r2, #AT91_SDRAMC_LPR - AT91_SDRAMC]
|
||||
bic r3, #AT91_SDRAMC_LPCB
|
||||
orr r3, #AT91_SDRAMC_LPCB_SELF_REFRESH
|
||||
str r3, [r2, #AT91_SDRAMC_LPR]
|
||||
#endif
|
||||
|
||||
/* Save Master clock setting */
|
||||
|
|
@ -247,14 +263,21 @@ ENTRY(at91_slow_clock)
|
|||
|
||||
#ifdef CONFIG_ARCH_AT91RM9200
|
||||
/* Do nothing - self-refresh is automatically disabled. */
|
||||
#elif defined(CONFIG_ARCH_AT91CAP9)
|
||||
/* Restore LPR on AT91CAP9 */
|
||||
#elif defined(CONFIG_ARCH_AT91CAP9) \
|
||||
|| defined(CONFIG_ARCH_AT91SAM9G45)
|
||||
/* Restore LPR on AT91 with DDRAM */
|
||||
ldr r3, .saved_sam9_lpr
|
||||
str r3, [r2, #AT91_DDRSDRC_LPR - AT91_DDRSDRC]
|
||||
str r3, [r2, #AT91_DDRSDRC_LPR]
|
||||
|
||||
/* if we use the second ram controller */
|
||||
cmp r5, #0
|
||||
ldrne r4, .saved_sam9_lpr1
|
||||
strne r4, [r5, #AT91_DDRSDRC_LPR]
|
||||
|
||||
#else
|
||||
/* Restore LPR on AT91SAM9 */
|
||||
/* Restore LPR on AT91 with SDRAM */
|
||||
ldr r3, .saved_sam9_lpr
|
||||
str r3, [r2, #AT91_SDRAMC_LPR - AT91_SDRAMC]
|
||||
str r3, [r2, #AT91_SDRAMC_LPR]
|
||||
#endif
|
||||
|
||||
/* Restore registers, and return */
|
||||
|
|
@ -273,18 +296,29 @@ ENTRY(at91_slow_clock)
|
|||
.saved_sam9_lpr:
|
||||
.word 0
|
||||
|
||||
.saved_sam9_lpr1:
|
||||
.word 0
|
||||
|
||||
.at91_va_base_pmc:
|
||||
.word AT91_VA_BASE_SYS + AT91_PMC
|
||||
|
||||
#ifdef CONFIG_ARCH_AT91RM9200
|
||||
.at91_va_base_sdramc:
|
||||
.word AT91_VA_BASE_SYS
|
||||
#elif defined(CONFIG_ARCH_AT91CAP9)
|
||||
#elif defined(CONFIG_ARCH_AT91CAP9) \
|
||||
|| defined(CONFIG_ARCH_AT91SAM9G45)
|
||||
.at91_va_base_sdramc:
|
||||
.word AT91_VA_BASE_SYS + AT91_DDRSDRC
|
||||
.word AT91_VA_BASE_SYS + AT91_DDRSDRC0
|
||||
#else
|
||||
.at91_va_base_sdramc:
|
||||
.word AT91_VA_BASE_SYS + AT91_SDRAMC
|
||||
.word AT91_VA_BASE_SYS + AT91_SDRAMC0
|
||||
#endif
|
||||
|
||||
.at91_va_base_ramc1:
|
||||
#if defined(CONFIG_ARCH_AT91SAM9G45)
|
||||
.word AT91_VA_BASE_SYS + AT91_DDRSDRC1
|
||||
#else
|
||||
.word 0
|
||||
#endif
|
||||
|
||||
ENTRY(at91_slow_clock_sz)
|
||||
|
|
|
|||
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