ASoC: tas2552: Correct CFG1 register bit definitions
Remove the _MASK postfix of the bit definitions, collect the CFG1 bit definition in one place and correct the bit shifts at the same time. Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com> Signed-off-by: Mark Brown <broonie@kernel.org>
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89683fdefd
Коммит
7de544fd32
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@ -126,10 +126,10 @@ static void tas2552_sw_shutdown(struct tas2552_data *tas_data, int sw_shutdown)
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if (sw_shutdown)
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if (sw_shutdown)
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cfg1_reg = 0;
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cfg1_reg = 0;
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else
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else
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cfg1_reg = TAS2552_SWS_MASK;
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cfg1_reg = TAS2552_SWS;
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snd_soc_update_bits(tas_data->codec, TAS2552_CFG_1,
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snd_soc_update_bits(tas_data->codec, TAS2552_CFG_1, TAS2552_SWS,
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TAS2552_SWS_MASK, cfg1_reg);
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cfg1_reg);
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}
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}
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#endif
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#endif
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@ -258,11 +258,11 @@ static int tas2552_mute(struct snd_soc_dai *dai, int mute)
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struct snd_soc_codec *codec = dai->codec;
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struct snd_soc_codec *codec = dai->codec;
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if (mute)
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if (mute)
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cfg1_reg = TAS2552_MUTE_MASK;
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cfg1_reg = TAS2552_MUTE;
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else
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else
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cfg1_reg = ~TAS2552_MUTE_MASK;
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cfg1_reg = ~TAS2552_MUTE;
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snd_soc_update_bits(codec, TAS2552_CFG_1, TAS2552_MUTE_MASK, cfg1_reg);
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snd_soc_update_bits(codec, TAS2552_CFG_1, TAS2552_MUTE, cfg1_reg);
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return 0;
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return 0;
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}
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}
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@ -370,7 +370,7 @@ static int tas2552_codec_probe(struct snd_soc_codec *codec)
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goto probe_fail;
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goto probe_fail;
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}
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}
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snd_soc_write(codec, TAS2552_CFG_1, TAS2552_MUTE_MASK |
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snd_soc_write(codec, TAS2552_CFG_1, TAS2552_MUTE |
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TAS2552_PLL_SRC_BCLK);
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TAS2552_PLL_SRC_BCLK);
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snd_soc_write(codec, TAS2552_CFG_3, TAS2552_I2S_OUT_SEL |
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snd_soc_write(codec, TAS2552_CFG_3, TAS2552_I2S_OUT_SEL |
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TAS2552_DIN_SRC_SEL_AVG_L_R | TAS2552_88_96KHZ);
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TAS2552_DIN_SRC_SEL_AVG_L_R | TAS2552_88_96KHZ);
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@ -45,10 +45,14 @@
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#define TAS2552_MAX_REG 0x20
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#define TAS2552_MAX_REG 0x20
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/* CFG1 Register Masks */
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/* CFG1 Register Masks */
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#define TAS2552_MUTE_MASK (1 << 2)
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#define TAS2552_DEV_RESET (1 << 0)
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#define TAS2552_SWS_MASK (1 << 1)
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#define TAS2552_SWS (1 << 1)
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#define TAS2552_WCLK_MASK 0x07
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#define TAS2552_MUTE (1 << 2)
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#define TAS2552_CLASSD_EN_MASK (1 << 7)
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#define TAS2552_PLL_SRC_MCLK (0x0 << 4)
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#define TAS2552_PLL_SRC_BCLK (0x1 << 4)
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#define TAS2552_PLL_SRC_IVCLKIN (0x2 << 4)
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#define TAS2552_PLL_SRC_1_8_FIXED (0x3 << 4)
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#define TAS2552_PLL_SRC_MASK TAS2552_PLL_SRC_1_8_FIXED
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/* CFG2 Register Masks */
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/* CFG2 Register Masks */
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#define TAS2552_CLASSD_EN (1 << 7)
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#define TAS2552_CLASSD_EN (1 << 7)
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@ -68,11 +72,6 @@
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#define TAS2552_DAIFMT_RIGHT_J (1 << 4)
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#define TAS2552_DAIFMT_RIGHT_J (1 << 4)
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#define TAS2552_DAIFMT_LEFT_J (0x11 << 3)
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#define TAS2552_DAIFMT_LEFT_J (0x11 << 3)
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#define TAS2552_PLL_SRC_MCLK 0x00
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#define TAS2552_PLL_SRC_BCLK (1 << 3)
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#define TAS2552_PLL_SRC_IVCLKIN (1 << 4)
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#define TAS2552_PLL_SRC_1_8_FIXED (0x11 << 3)
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#define TAS2552_DIN_SRC_SEL_MUTED 0x00
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#define TAS2552_DIN_SRC_SEL_MUTED 0x00
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#define TAS2552_DIN_SRC_SEL_LEFT (1 << 4)
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#define TAS2552_DIN_SRC_SEL_LEFT (1 << 4)
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#define TAS2552_DIN_SRC_SEL_RIGHT (1 << 5)
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#define TAS2552_DIN_SRC_SEL_RIGHT (1 << 5)
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