[PATCH] skge: add PHY related debug messages
Cleanup messages (for debug) about PHY interrrupts, because when user can't get driver working that is often the problem. Use a consistent way of enabling interrupts by port. Signed-off-by: Stephen Hemminger <shemminger@osdl.org>
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45bada65c2
Коммит
7e676d9136
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@ -97,10 +97,12 @@ static void genesis_mac_init(struct skge_hw *hw, int port);
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static void genesis_reset(struct skge_hw *hw, int port);
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static void genesis_link_up(struct skge_port *skge);
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/* Avoid conditionals by using array */
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static const int txqaddr[] = { Q_XA1, Q_XA2 };
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static const int rxqaddr[] = { Q_R1, Q_R2 };
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static const u32 rxirqmask[] = { IS_R1_F, IS_R2_F };
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static const u32 txirqmask[] = { IS_XA1_F, IS_XA2_F };
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static const u32 portirqmask[] = { IS_PORT_1, IS_PORT_2 };
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/* Don't need to look at whole 16K.
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* last interesting register is descriptor poll timer.
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@ -1382,7 +1384,9 @@ static void genesis_mac_intr(struct skge_hw *hw, int port)
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struct skge_port *skge = netdev_priv(hw->dev[port]);
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u16 status = xm_read16(hw, port, XM_ISRC);
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pr_debug("genesis_intr status %x\n", status);
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if (netif_msg_intr(skge))
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printk(KERN_DEBUG PFX "%s: mac interrupt status 0x%x\n",
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skge->netdev->name, status);
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if (status & XM_IS_TXF_UR) {
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xm_write32(hw, port, XM_MODE, XM_MD_FTF);
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@ -1446,6 +1450,7 @@ static void genesis_link_up(struct skge_port *skge)
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*/
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if (skge->flow_control == FLOW_MODE_NONE ||
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skge->flow_control == FLOW_MODE_LOC_SEND)
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/* Disable Pause Frame Reception */
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cmd |= XM_MMU_IGN_PF;
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else
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/* Enable Pause Frame Reception */
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@ -1519,7 +1524,9 @@ static inline void bcom_phy_intr(struct skge_port *skge)
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u16 isrc;
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isrc = xm_phy_read(hw, port, PHY_BCOM_INT_STAT);
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pr_debug("bcom_phy_interrupt status=0x%x\n", isrc);
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if (netif_msg_intr(skge))
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printk(KERN_DEBUG PFX "%s: phy interrupt status 0x%x\n",
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skge->netdev->name, isrc);
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if (isrc & PHY_B_IS_PSE)
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printk(KERN_ERR PFX "%s: uncorrectable pair swap error\n",
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@ -1823,10 +1830,14 @@ static void yukon_get_stats(struct skge_port *skge, u64 *data)
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static void yukon_mac_intr(struct skge_hw *hw, int port)
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{
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struct skge_port *skge = netdev_priv(hw->dev[port]);
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struct net_device *dev = hw->dev[port];
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struct skge_port *skge = netdev_priv(dev);
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u8 status = skge_read8(hw, SK_REG(port, GMAC_IRQ_SRC));
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pr_debug("yukon_intr status %x\n", status);
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if (netif_msg_intr(skge))
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printk(KERN_DEBUG PFX "%s: mac interrupt status 0x%x\n",
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dev->name, status);
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if (status & GM_IS_RX_FF_OR) {
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++skge->net_stats.rx_fifo_errors;
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gma_write8(hw, port, RX_GMF_CTRL_T, GMF_CLI_RX_FO);
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@ -1908,7 +1919,10 @@ static void yukon_phy_intr(struct skge_port *skge)
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istatus = gm_phy_read(hw, port, PHY_MARV_INT_STAT);
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phystat = gm_phy_read(hw, port, PHY_MARV_PHY_STAT);
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pr_debug("yukon phy intr istat=%x phy_stat=%x\n", istatus, phystat);
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if (netif_msg_intr(skge))
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printk(KERN_DEBUG PFX "%s: phy interrupt status 0x%x 0x%x\n",
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skge->netdev->name, istatus, phystat);
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if (istatus & PHY_M_IS_AN_COMPL) {
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if (gm_phy_read(hw, port, PHY_MARV_AUNE_LP)
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@ -2055,6 +2069,10 @@ static int skge_up(struct net_device *dev)
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skge->tx_avail = skge->tx_ring.count - 1;
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/* Enable IRQ from port */
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hw->intr_mask |= portirqmask[port];
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skge_write32(hw, B0_IMSK, hw->intr_mask);
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/* Initialze MAC */
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if (hw->chip_id == CHIP_ID_GENESIS)
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genesis_mac_init(hw, port);
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@ -2449,7 +2467,8 @@ static int skge_poll(struct net_device *dev, int *budget)
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unsigned int to_do = min(dev->quota, *budget);
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unsigned int work_done = 0;
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int done;
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static const u32 irqmask[] = { IS_PORT_1, IS_PORT_2 };
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pr_debug("skge_poll\n");
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for (e = ring->to_clean; e != ring->to_use && work_done < to_do;
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e = e->next) {
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@ -2512,10 +2531,9 @@ static int skge_poll(struct net_device *dev, int *budget)
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if (done) {
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local_irq_disable();
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hw->intr_mask |= irqmask[skge->port];
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/* Order is important since data can get interrupted */
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skge_write32(hw, B0_IMSK, hw->intr_mask);
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__netif_rx_complete(dev);
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hw->intr_mask |= portirqmask[skge->port];
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skge_write32(hw, B0_IMSK, hw->intr_mask);
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local_irq_enable();
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}
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@ -2697,19 +2715,14 @@ static irqreturn_t skge_intr(int irq, void *dev_id, struct pt_regs *regs)
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return IRQ_NONE;
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status &= hw->intr_mask;
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if ((status & IS_R1_F) && netif_rx_schedule_prep(hw->dev[0])) {
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status &= ~IS_R1_F;
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if (status & IS_R1_F) {
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hw->intr_mask &= ~IS_R1_F;
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skge_write32(hw, B0_IMSK, hw->intr_mask);
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__netif_rx_schedule(hw->dev[0]);
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netif_rx_schedule(hw->dev[0]);
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}
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if ((status & IS_R2_F) && netif_rx_schedule_prep(hw->dev[1])) {
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status &= ~IS_R2_F;
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if (status & IS_R2_F) {
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hw->intr_mask &= ~IS_R2_F;
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skge_write32(hw, B0_IMSK, hw->intr_mask);
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__netif_rx_schedule(hw->dev[1]);
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netif_rx_schedule(hw->dev[1]);
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}
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if (status & IS_XA1_F)
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@ -2732,8 +2745,7 @@ static irqreturn_t skge_intr(int irq, void *dev_id, struct pt_regs *regs)
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tasklet_schedule(&hw->ext_tasklet);
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}
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if (status)
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skge_write32(hw, B0_IMSK, hw->intr_mask);
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skge_write32(hw, B0_IMSK, hw->intr_mask);
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return IRQ_HANDLED;
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}
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@ -2918,9 +2930,7 @@ static int skge_reset(struct skge_hw *hw)
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skge_write32(hw, B2_IRQM_INI, skge_usecs2clk(hw, 100));
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skge_write32(hw, B2_IRQM_CTRL, TIM_START);
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hw->intr_mask = IS_HW_ERR | IS_EXT_REG | IS_PORT_1;
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if (hw->ports > 1)
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hw->intr_mask |= IS_PORT_2;
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hw->intr_mask = IS_HW_ERR | IS_EXT_REG;
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skge_write32(hw, B0_IMSK, hw->intr_mask);
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if (hw->chip_id != CHIP_ID_GENESIS)
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@ -2317,8 +2317,8 @@ enum {
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};
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#define XM_PAUSE_MODE (XM_MD_SPOE_E | XM_MD_SPOL_I | XM_MD_SPOH_I)
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#define XM_DEF_MODE (XM_MD_RX_RUNT | XM_MD_RX_IRLE | XM_MD_RX_LONG |\
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XM_MD_RX_CRCE | XM_MD_RX_ERR | XM_MD_CSA | XM_MD_CAA)
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#define XM_DEF_MODE (XM_MD_RX_RUNT | XM_MD_RX_IRLE | XM_MD_RX_LONG |\
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XM_MD_RX_CRCE | XM_MD_RX_ERR | XM_MD_CSA)
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/* XM_STAT_CMD 16 bit r/w Statistics Command Register */
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enum {
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