MIPS: Octeon: Improve USB reset code for OCTEON II.
At boot time, do a better job of resetting the USB host controller to make the frequency "eye" diagram more compliant with the USB standard while making the controller more reliable. Signed-off-by: Steven J. Hill <steven.hill@cavium.com> Acked-by: David Daney <david.daney@cavium.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/13831/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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@ -3,33 +3,27 @@
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*
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* Copyright (C) 2004-2011 Cavium Networks
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* Copyright (C) 2004-2016 Cavium Networks
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* Copyright (C) 2008 Wind River Systems
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*/
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#include <linux/delay.h>
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#include <linux/init.h>
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#include <linux/irq.h>
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#include <linux/i2c.h>
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#include <linux/usb.h>
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#include <linux/dma-mapping.h>
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#include <linux/delay.h>
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#include <linux/etherdevice.h>
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#include <linux/module.h>
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#include <linux/mutex.h>
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#include <linux/slab.h>
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#include <linux/platform_device.h>
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#include <linux/of_platform.h>
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#include <linux/of_fdt.h>
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#include <linux/libfdt.h>
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#include <linux/usb/ehci_def.h>
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#include <linux/usb/ehci_pdriver.h>
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#include <linux/usb/ohci_pdriver.h>
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#include <asm/octeon/octeon.h>
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#include <asm/octeon/cvmx-rnm-defs.h>
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#include <asm/octeon/cvmx-helper.h>
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#include <asm/octeon/cvmx-helper-board.h>
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#include <asm/octeon/cvmx-uctlx-defs.h>
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#define CVMX_UAHCX_EHCI_USBCMD (CVMX_ADD_IO_SEG(0x00016F0000000010ull))
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#define CVMX_UAHCX_OHCI_USBCMD (CVMX_ADD_IO_SEG(0x00016F0000000408ull))
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/* Octeon Random Number Generator. */
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static int __init octeon_rng_device_init(void)
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{
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@ -78,12 +72,36 @@ static DEFINE_MUTEX(octeon2_usb_clocks_mutex);
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static int octeon2_usb_clock_start_cnt;
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static int __init octeon2_usb_reset(void)
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{
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union cvmx_uctlx_clk_rst_ctl clk_rst_ctl;
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u32 ucmd;
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if (!OCTEON_IS_OCTEON2())
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return 0;
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clk_rst_ctl.u64 = cvmx_read_csr(CVMX_UCTLX_CLK_RST_CTL(0));
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if (clk_rst_ctl.s.hrst) {
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ucmd = cvmx_read64_uint32(CVMX_UAHCX_EHCI_USBCMD);
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ucmd &= ~CMD_RUN;
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cvmx_write64_uint32(CVMX_UAHCX_EHCI_USBCMD, ucmd);
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mdelay(2);
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ucmd |= CMD_RESET;
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cvmx_write64_uint32(CVMX_UAHCX_EHCI_USBCMD, ucmd);
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ucmd = cvmx_read64_uint32(CVMX_UAHCX_OHCI_USBCMD);
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ucmd |= CMD_RUN;
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cvmx_write64_uint32(CVMX_UAHCX_OHCI_USBCMD, ucmd);
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}
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return 0;
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}
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arch_initcall(octeon2_usb_reset);
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static void octeon2_usb_clocks_start(struct device *dev)
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{
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u64 div;
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union cvmx_uctlx_if_ena if_ena;
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union cvmx_uctlx_clk_rst_ctl clk_rst_ctl;
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union cvmx_uctlx_uphy_ctl_status uphy_ctl_status;
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union cvmx_uctlx_uphy_portx_ctl_status port_ctl_status;
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int i;
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unsigned long io_clk_64_to_ns;
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@ -131,6 +149,17 @@ static void octeon2_usb_clocks_start(struct device *dev)
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if_ena.s.en = 1;
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cvmx_write_csr(CVMX_UCTLX_IF_ENA(0), if_ena.u64);
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for (i = 0; i <= 1; i++) {
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port_ctl_status.u64 =
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cvmx_read_csr(CVMX_UCTLX_UPHY_PORTX_CTL_STATUS(i, 0));
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/* Set txvreftune to 15 to obtain compliant 'eye' diagram. */
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port_ctl_status.s.txvreftune = 15;
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port_ctl_status.s.txrisetune = 1;
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port_ctl_status.s.txpreemphasistune = 1;
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cvmx_write_csr(CVMX_UCTLX_UPHY_PORTX_CTL_STATUS(i, 0),
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port_ctl_status.u64);
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}
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/* Step 3: Configure the reference clock, PHY, and HCLK */
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clk_rst_ctl.u64 = cvmx_read_csr(CVMX_UCTLX_CLK_RST_CTL(0));
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@ -218,29 +247,10 @@ static void octeon2_usb_clocks_start(struct device *dev)
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clk_rst_ctl.s.p_por = 0;
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cvmx_write_csr(CVMX_UCTLX_CLK_RST_CTL(0), clk_rst_ctl.u64);
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/* Step 5: Wait 1 ms for the PHY clock to start. */
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mdelay(1);
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/* Step 5: Wait 3 ms for the PHY clock to start. */
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mdelay(3);
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/*
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* Step 6: Program the reset input from automatic test
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* equipment field in the UPHY CSR
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*/
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uphy_ctl_status.u64 = cvmx_read_csr(CVMX_UCTLX_UPHY_CTL_STATUS(0));
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uphy_ctl_status.s.ate_reset = 1;
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cvmx_write_csr(CVMX_UCTLX_UPHY_CTL_STATUS(0), uphy_ctl_status.u64);
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/* Step 7: Wait for at least 10ns. */
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ndelay(10);
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/* Step 8: Clear the ATE_RESET field in the UPHY CSR. */
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uphy_ctl_status.s.ate_reset = 0;
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cvmx_write_csr(CVMX_UCTLX_UPHY_CTL_STATUS(0), uphy_ctl_status.u64);
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/*
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* Step 9: Wait for at least 20ns for UPHY to output PHY clock
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* signals and OHCI_CLK48
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*/
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ndelay(20);
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/* Steps 6..9 for ATE only, are skipped. */
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/* Step 10: Configure the OHCI_CLK48 and OHCI_CLK12 clocks. */
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/* 10a */
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@ -261,6 +271,20 @@ static void octeon2_usb_clocks_start(struct device *dev)
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clk_rst_ctl.s.p_prst = 1;
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cvmx_write_csr(CVMX_UCTLX_CLK_RST_CTL(0), clk_rst_ctl.u64);
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/* Step 11b */
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udelay(1);
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/* Step 11c */
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clk_rst_ctl.s.p_prst = 0;
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cvmx_write_csr(CVMX_UCTLX_CLK_RST_CTL(0), clk_rst_ctl.u64);
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/* Step 11d */
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mdelay(1);
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/* Step 11e */
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clk_rst_ctl.s.p_prst = 1;
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cvmx_write_csr(CVMX_UCTLX_CLK_RST_CTL(0), clk_rst_ctl.u64);
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/* Step 12: Wait 1 uS. */
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udelay(1);
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@ -269,21 +293,9 @@ static void octeon2_usb_clocks_start(struct device *dev)
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cvmx_write_csr(CVMX_UCTLX_CLK_RST_CTL(0), clk_rst_ctl.u64);
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end_clock:
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/* Now we can set some other registers. */
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for (i = 0; i <= 1; i++) {
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port_ctl_status.u64 =
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cvmx_read_csr(CVMX_UCTLX_UPHY_PORTX_CTL_STATUS(i, 0));
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/* Set txvreftune to 15 to obtain compliant 'eye' diagram. */
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port_ctl_status.s.txvreftune = 15;
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port_ctl_status.s.txrisetune = 1;
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port_ctl_status.s.txpreemphasistune = 1;
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cvmx_write_csr(CVMX_UCTLX_UPHY_PORTX_CTL_STATUS(i, 0),
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port_ctl_status.u64);
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}
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/* Set uSOF cycle period to 60,000 bits. */
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cvmx_write_csr(CVMX_UCTLX_EHCI_FLA(0), 0x20ull);
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exit:
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mutex_unlock(&octeon2_usb_clocks_mutex);
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}
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