phy: ti: am654-serdes: Support all clksel values
Add support to select all 16 CLKSEL combinations that are shown in "SerDes Reference Clock Distribution" in AM65 TRM. Signed-off-by: Roger Quadros <rogerq@ti.com> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
This commit is contained in:
Roger Quadros
Kishon Vijay Abraham I
Родитель
71e2f5c5c2
Коммит
7e7b8ca661
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@ -58,13 +58,14 @@
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#define SERDES_NUM_CLOCKS 3
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#define AM654_SERDES_CTRL_CLKSEL_MASK GENMASK(7, 4)
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#define AM654_SERDES_CTRL_CLKSEL_SHIFT 4
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struct serdes_am654_clk_mux {
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struct clk_hw hw;
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struct regmap *regmap;
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unsigned int reg;
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int *table;
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u32 mask;
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u8 shift;
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int clk_id;
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struct clk_init_data clk_data;
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};
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@ -282,31 +283,52 @@ static const struct phy_ops ops = {
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.owner = THIS_MODULE,
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};
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#define SERDES_NUM_MUX_COMBINATIONS 16
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#define LICLK 0
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#define EXT_REFCLK 1
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#define RICLK 2
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static const int
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serdes_am654_mux_table[SERDES_NUM_MUX_COMBINATIONS][SERDES_NUM_CLOCKS] = {
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/*
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* Each combination maps to one of
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* "Figure 12-1986. SerDes Reference Clock Distribution"
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* in TRM.
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*/
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/* Parent of CMU refclk, Left output, Right output
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* either of EXT_REFCLK, LICLK, RICLK
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*/
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{ EXT_REFCLK, EXT_REFCLK, EXT_REFCLK }, /* 0000 */
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{ RICLK, EXT_REFCLK, EXT_REFCLK }, /* 0001 */
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{ EXT_REFCLK, RICLK, LICLK }, /* 0010 */
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{ RICLK, RICLK, EXT_REFCLK }, /* 0011 */
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{ LICLK, EXT_REFCLK, EXT_REFCLK }, /* 0100 */
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{ EXT_REFCLK, EXT_REFCLK, EXT_REFCLK }, /* 0101 */
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{ LICLK, RICLK, LICLK }, /* 0110 */
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{ EXT_REFCLK, RICLK, LICLK }, /* 0111 */
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{ EXT_REFCLK, EXT_REFCLK, LICLK }, /* 1000 */
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{ RICLK, EXT_REFCLK, LICLK }, /* 1001 */
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{ EXT_REFCLK, RICLK, EXT_REFCLK }, /* 1010 */
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{ RICLK, RICLK, EXT_REFCLK }, /* 1011 */
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{ LICLK, EXT_REFCLK, LICLK }, /* 1100 */
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{ EXT_REFCLK, EXT_REFCLK, LICLK }, /* 1101 */
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{ LICLK, RICLK, EXT_REFCLK }, /* 1110 */
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{ EXT_REFCLK, RICLK, EXT_REFCLK }, /* 1111 */
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};
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static u8 serdes_am654_clk_mux_get_parent(struct clk_hw *hw)
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{
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struct serdes_am654_clk_mux *mux = to_serdes_am654_clk_mux(hw);
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unsigned int num_parents = clk_hw_get_num_parents(hw);
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struct regmap *regmap = mux->regmap;
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unsigned int reg = mux->reg;
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unsigned int val;
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int i;
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regmap_read(regmap, reg, &val);
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val >>= mux->shift;
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val &= mux->mask;
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val &= AM654_SERDES_CTRL_CLKSEL_MASK;
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val >>= AM654_SERDES_CTRL_CLKSEL_SHIFT;
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for (i = 0; i < num_parents; i++)
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if (mux->table[i] == val)
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return i;
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/*
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* No parent? This should never happen!
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* Verify if we set a valid parent in serdes_am654_clk_register()
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*/
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WARN(1, "Failed to find the parent of %s clock\n", hw->init->name);
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/* Make the parent lookup to fail */
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return num_parents;
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return serdes_am654_mux_table[val][mux->clk_id];
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}
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static int serdes_am654_clk_mux_set_parent(struct clk_hw *hw, u8 index)
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@ -314,16 +336,52 @@ static int serdes_am654_clk_mux_set_parent(struct clk_hw *hw, u8 index)
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struct serdes_am654_clk_mux *mux = to_serdes_am654_clk_mux(hw);
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struct regmap *regmap = mux->regmap;
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unsigned int reg = mux->reg;
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int val;
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int clk_id = mux->clk_id;
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int parents[SERDES_NUM_CLOCKS];
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const int *p;
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u32 val;
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int found, i;
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int ret;
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val = mux->table[index];
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/* get existing setting */
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regmap_read(regmap, reg, &val);
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val &= AM654_SERDES_CTRL_CLKSEL_MASK;
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val >>= AM654_SERDES_CTRL_CLKSEL_SHIFT;
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if (val == -1)
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for (i = 0; i < SERDES_NUM_CLOCKS; i++)
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parents[i] = serdes_am654_mux_table[val][i];
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/* change parent of this clock. others left intact */
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parents[clk_id] = index;
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/* Find the match */
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for (val = 0; val < SERDES_NUM_MUX_COMBINATIONS; val++) {
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p = serdes_am654_mux_table[val];
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found = 1;
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for (i = 0; i < SERDES_NUM_CLOCKS; i++) {
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if (parents[i] != p[i]) {
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found = 0;
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break;
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}
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}
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if (found)
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break;
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}
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if (!found) {
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/*
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* This can never happen, unless we missed
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* a valid combination in serdes_am654_mux_table.
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*/
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WARN(1, "Failed to find the parent of %s clock\n",
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hw->init->name);
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return -EINVAL;
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}
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val <<= mux->shift;
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ret = regmap_update_bits(regmap, reg, mux->mask << mux->shift, val);
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val <<= AM654_SERDES_CTRL_CLKSEL_SHIFT;
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ret = regmap_update_bits(regmap, reg, AM654_SERDES_CTRL_CLKSEL_MASK,
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val);
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return ret;
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}
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@ -333,21 +391,6 @@ static const struct clk_ops serdes_am654_clk_mux_ops = {
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.get_parent = serdes_am654_clk_mux_get_parent,
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};
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static int mux_table[SERDES_NUM_CLOCKS][3] = {
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/*
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* The entries represent values for selecting between
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* {left input, external reference clock, right input}
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* Only one of Left Output or Right Output should be used since
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* both left and right output clock uses the same bits and modifying
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* one clock will impact the other.
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*/
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{ BIT(2), 0, BIT(0) }, /* Mux of CMU refclk */
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{ -1, BIT(3), BIT(1) }, /* Mux of Left Output */
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{ BIT(1), BIT(3) | BIT(1), -1 }, /* Mux of Right Output */
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};
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static int mux_mask[SERDES_NUM_CLOCKS] = { 0x5, 0xa, 0xa };
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static int serdes_am654_clk_register(struct serdes_am654 *am654_phy,
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const char *clock_name, int clock_num)
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{
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@ -407,20 +450,11 @@ static int serdes_am654_clk_register(struct serdes_am654 *am654_phy,
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init->num_parents = num_parents;
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init->name = clock_name;
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mux->table = mux_table[clock_num];
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mux->regmap = regmap;
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mux->reg = reg;
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mux->shift = 4;
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mux->mask = mux_mask[clock_num];
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mux->clk_id = clock_num;
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mux->hw.init = init;
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/*
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* setup a sane default so get_parent() call evaluates
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* to a valid parent. Index 1 is the safest choice as
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* the default as it is valid value for all of serdes's
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* output clocks.
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*/
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serdes_am654_clk_mux_set_parent(&mux->hw, 1);
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clk = devm_clk_register(dev, &mux->hw);
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if (IS_ERR(clk))
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return PTR_ERR(clk);
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