spi: rspi: Fix handling of QSPI code when transmit and receive
Process handling QSPI when transmit/receive at qspi_trigger_transfer_out_in() as follows: Setting the trigger, is the number of bytes in the FIFO buffer to determine when there is an interrupt. Then check if the value of triggering number is 32-bytes or 1-byte, there will be corresponding processing Handling (if (n == QSPI_BUFFER_SIZE) esle) this is unnecessary, leads to the same processing of data transmission or reception, The difference here are with ret = rspi_wait_for_tx_empty(rspi); ret = rspi_wait_for_rx_full(rspi); When the nummber trigger is 32 bytes, we only write into FIFO when the FIFO is completely empty (interrupt transmission), and only receive if FIFO is full of 32 bytes of data. In the case of a nummber trigger that is 1 byte, in principle we still need to process rspi_wait_for_tx_empty/full so that FIFO is empty only with the amount of data we need to write to or equal to the number of bytes we need to receive, There is currently no processing of this. And in the current case with this patch, at this time it only needs at least 1 byte received in FIFO that has interrupt received, or FIFO at least 1bytes free can be written into FIFO, This patch therefore does not affect this processing. So we need to eliminate unnecessary waste processing (if (n == QSPI_BUFFER_SIZE) esle), more precisely in waiting for FIFO status. The same with handling in qspi_transfer_out()/qspi_transfer_in(). Signed-off-by: Hoan Nguyen An <na-hoan@jinso.co.jp> Signed-off-by: Mark Brown <broonie@kernel.org>
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e5c27498a0
Коммит
7e95b16625
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@ -739,27 +739,22 @@ static int qspi_trigger_transfer_out_in(struct rspi_data *rspi, const u8 *tx,
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while (len > 0) {
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while (len > 0) {
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n = qspi_set_send_trigger(rspi, len);
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n = qspi_set_send_trigger(rspi, len);
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qspi_set_receive_trigger(rspi, len);
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qspi_set_receive_trigger(rspi, len);
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if (n == QSPI_BUFFER_SIZE) {
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ret = rspi_wait_for_tx_empty(rspi);
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ret = rspi_wait_for_tx_empty(rspi);
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if (ret < 0) {
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if (ret < 0) {
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dev_err(&rspi->ctlr->dev, "transmit timeout\n");
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dev_err(&rspi->ctlr->dev, "transmit timeout\n");
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return ret;
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return ret;
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}
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for (i = 0; i < n; i++)
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rspi_write_data(rspi, *tx++);
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ret = rspi_wait_for_rx_full(rspi);
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if (ret < 0) {
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dev_err(&rspi->ctlr->dev, "receive timeout\n");
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return ret;
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}
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for (i = 0; i < n; i++)
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*rx++ = rspi_read_data(rspi);
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} else {
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ret = rspi_pio_transfer(rspi, tx, rx, n);
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if (ret < 0)
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return ret;
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}
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}
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for (i = 0; i < n; i++)
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rspi_write_data(rspi, *tx++);
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ret = rspi_wait_for_rx_full(rspi);
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if (ret < 0) {
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dev_err(&rspi->ctlr->dev, "receive timeout\n");
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return ret;
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}
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for (i = 0; i < n; i++)
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*rx++ = rspi_read_data(rspi);
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len -= n;
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len -= n;
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}
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}
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@ -796,19 +791,14 @@ static int qspi_transfer_out(struct rspi_data *rspi, struct spi_transfer *xfer)
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while (n > 0) {
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while (n > 0) {
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len = qspi_set_send_trigger(rspi, n);
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len = qspi_set_send_trigger(rspi, n);
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if (len == QSPI_BUFFER_SIZE) {
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ret = rspi_wait_for_tx_empty(rspi);
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ret = rspi_wait_for_tx_empty(rspi);
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if (ret < 0) {
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if (ret < 0) {
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dev_err(&rspi->ctlr->dev, "transmit timeout\n");
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dev_err(&rspi->ctlr->dev, "transmit timeout\n");
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return ret;
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return ret;
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}
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for (i = 0; i < len; i++)
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rspi_write_data(rspi, *tx++);
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} else {
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ret = rspi_pio_transfer(rspi, tx, NULL, len);
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if (ret < 0)
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return ret;
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}
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}
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for (i = 0; i < len; i++)
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rspi_write_data(rspi, *tx++);
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n -= len;
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n -= len;
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}
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}
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@ -833,19 +823,14 @@ static int qspi_transfer_in(struct rspi_data *rspi, struct spi_transfer *xfer)
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while (n > 0) {
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while (n > 0) {
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len = qspi_set_receive_trigger(rspi, n);
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len = qspi_set_receive_trigger(rspi, n);
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if (len == QSPI_BUFFER_SIZE) {
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ret = rspi_wait_for_rx_full(rspi);
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ret = rspi_wait_for_rx_full(rspi);
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if (ret < 0) {
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if (ret < 0) {
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dev_err(&rspi->ctlr->dev, "receive timeout\n");
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dev_err(&rspi->ctlr->dev, "receive timeout\n");
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return ret;
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return ret;
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}
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for (i = 0; i < len; i++)
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*rx++ = rspi_read_data(rspi);
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} else {
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ret = rspi_pio_transfer(rspi, NULL, rx, len);
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if (ret < 0)
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return ret;
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}
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}
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for (i = 0; i < len; i++)
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*rx++ = rspi_read_data(rspi);
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n -= len;
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n -= len;
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}
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}
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