MIPS: ath79: add common USB Host Controller device
Add common platform_device and helper code to make the registration of the built-in USB controllers easier on the board which are using them. Also register the USB controller on the AP81 and PB44 boards. Signed-off-by: Gabor Juhos <juhosg@openwrt.org> Signed-off-by: Imre Kaloz <kaloz@openwrt.org> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/2442/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
This commit is contained in:
Gabor Juhos
Ralf Baechle
Родитель
d2b4ac1e5d
Коммит
7e98aa4639
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@ -9,6 +9,7 @@ config ATH79_MACH_AP81
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select ATH79_DEV_GPIO_BUTTONS
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select ATH79_DEV_LEDS_GPIO
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select ATH79_DEV_SPI
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select ATH79_DEV_USB
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help
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Say 'Y' here if you want your kernel to support the
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Atheros AP81 reference board.
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@ -19,6 +20,7 @@ config ATH79_MACH_PB44
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select ATH79_DEV_GPIO_BUTTONS
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select ATH79_DEV_LEDS_GPIO
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select ATH79_DEV_SPI
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select ATH79_DEV_USB
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help
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Say 'Y' here if you want your kernel to support the
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Atheros PB44 reference board.
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@ -52,4 +54,7 @@ config ATH79_DEV_LEDS_GPIO
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config ATH79_DEV_SPI
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def_bool n
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config ATH79_DEV_USB
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def_bool n
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endif
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@ -20,6 +20,7 @@ obj-$(CONFIG_ATH79_DEV_AR913X_WMAC) += dev-ar913x-wmac.o
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obj-$(CONFIG_ATH79_DEV_GPIO_BUTTONS) += dev-gpio-buttons.o
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obj-$(CONFIG_ATH79_DEV_LEDS_GPIO) += dev-leds-gpio.o
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obj-$(CONFIG_ATH79_DEV_SPI) += dev-spi.o
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obj-$(CONFIG_ATH79_DEV_USB) += dev-usb.o
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#
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# Machines
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@ -0,0 +1,178 @@
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/*
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* Atheros AR7XXX/AR9XXX USB Host Controller device
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*
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* Copyright (C) 2008-2011 Gabor Juhos <juhosg@openwrt.org>
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* Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
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*
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* Parts of this file are based on Atheros' 2.6.15 BSP
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License version 2 as published
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* by the Free Software Foundation.
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*/
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#include <linux/kernel.h>
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#include <linux/init.h>
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#include <linux/delay.h>
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#include <linux/irq.h>
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#include <linux/dma-mapping.h>
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#include <linux/platform_device.h>
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#include <asm/mach-ath79/ath79.h>
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#include <asm/mach-ath79/ar71xx_regs.h>
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#include "common.h"
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#include "dev-usb.h"
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static struct resource ath79_ohci_resources[] = {
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[0] = {
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/* .start and .end fields are filled dynamically */
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.flags = IORESOURCE_MEM,
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},
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[1] = {
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.start = ATH79_MISC_IRQ_OHCI,
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.end = ATH79_MISC_IRQ_OHCI,
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.flags = IORESOURCE_IRQ,
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},
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};
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static u64 ath79_ohci_dmamask = DMA_BIT_MASK(32);
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static struct platform_device ath79_ohci_device = {
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.name = "ath79-ohci",
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.id = -1,
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.resource = ath79_ohci_resources,
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.num_resources = ARRAY_SIZE(ath79_ohci_resources),
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.dev = {
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.dma_mask = &ath79_ohci_dmamask,
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.coherent_dma_mask = DMA_BIT_MASK(32),
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},
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};
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static struct resource ath79_ehci_resources[] = {
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[0] = {
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/* .start and .end fields are filled dynamically */
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.flags = IORESOURCE_MEM,
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},
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[1] = {
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.start = ATH79_CPU_IRQ_USB,
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.end = ATH79_CPU_IRQ_USB,
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.flags = IORESOURCE_IRQ,
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},
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};
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static u64 ath79_ehci_dmamask = DMA_BIT_MASK(32);
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static struct platform_device ath79_ehci_device = {
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.name = "ath79-ehci",
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.id = -1,
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.resource = ath79_ehci_resources,
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.num_resources = ARRAY_SIZE(ath79_ehci_resources),
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.dev = {
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.dma_mask = &ath79_ehci_dmamask,
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.coherent_dma_mask = DMA_BIT_MASK(32),
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},
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};
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#define AR71XX_USB_RESET_MASK (AR71XX_RESET_USB_HOST | \
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AR71XX_RESET_USB_PHY | \
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AR71XX_RESET_USB_OHCI_DLL)
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static void __init ath79_usb_setup(void)
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{
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void __iomem *usb_ctrl_base;
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ath79_device_reset_set(AR71XX_USB_RESET_MASK);
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mdelay(1000);
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ath79_device_reset_clear(AR71XX_USB_RESET_MASK);
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usb_ctrl_base = ioremap(AR71XX_USB_CTRL_BASE, AR71XX_USB_CTRL_SIZE);
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/* Turning on the Buff and Desc swap bits */
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__raw_writel(0xf0000, usb_ctrl_base + AR71XX_USB_CTRL_REG_CONFIG);
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/* WAR for HW bug. Here it adjusts the duration between two SOFS */
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__raw_writel(0x20c00, usb_ctrl_base + AR71XX_USB_CTRL_REG_FLADJ);
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iounmap(usb_ctrl_base);
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mdelay(900);
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ath79_ohci_resources[0].start = AR71XX_OHCI_BASE;
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ath79_ohci_resources[0].end = AR71XX_OHCI_BASE + AR71XX_OHCI_SIZE - 1;
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platform_device_register(&ath79_ohci_device);
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ath79_ehci_resources[0].start = AR71XX_EHCI_BASE;
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ath79_ehci_resources[0].end = AR71XX_EHCI_BASE + AR71XX_EHCI_SIZE - 1;
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ath79_ehci_device.name = "ar71xx-ehci";
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platform_device_register(&ath79_ehci_device);
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}
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static void __init ar7240_usb_setup(void)
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{
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void __iomem *usb_ctrl_base;
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ath79_device_reset_clear(AR7240_RESET_OHCI_DLL);
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ath79_device_reset_set(AR7240_RESET_USB_HOST);
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mdelay(1000);
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ath79_device_reset_set(AR7240_RESET_OHCI_DLL);
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ath79_device_reset_clear(AR7240_RESET_USB_HOST);
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usb_ctrl_base = ioremap(AR7240_USB_CTRL_BASE, AR7240_USB_CTRL_SIZE);
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/* WAR for HW bug. Here it adjusts the duration between two SOFS */
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__raw_writel(0x3, usb_ctrl_base + AR71XX_USB_CTRL_REG_FLADJ);
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iounmap(usb_ctrl_base);
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ath79_ohci_resources[0].start = AR7240_OHCI_BASE;
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ath79_ohci_resources[0].end = AR7240_OHCI_BASE + AR7240_OHCI_SIZE - 1;
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platform_device_register(&ath79_ohci_device);
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}
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static void __init ar724x_usb_setup(void)
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{
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ath79_device_reset_set(AR724X_RESET_USBSUS_OVERRIDE);
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mdelay(10);
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ath79_device_reset_clear(AR724X_RESET_USB_HOST);
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mdelay(10);
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ath79_device_reset_clear(AR724X_RESET_USB_PHY);
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mdelay(10);
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ath79_ehci_resources[0].start = AR724X_EHCI_BASE;
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ath79_ehci_resources[0].end = AR724X_EHCI_BASE + AR724X_EHCI_SIZE - 1;
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ath79_ehci_device.name = "ar724x-ehci";
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platform_device_register(&ath79_ehci_device);
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}
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static void __init ar913x_usb_setup(void)
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{
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ath79_device_reset_set(AR913X_RESET_USBSUS_OVERRIDE);
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mdelay(10);
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ath79_device_reset_clear(AR913X_RESET_USB_HOST);
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mdelay(10);
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ath79_device_reset_clear(AR913X_RESET_USB_PHY);
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mdelay(10);
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ath79_ehci_resources[0].start = AR913X_EHCI_BASE;
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ath79_ehci_resources[0].end = AR913X_EHCI_BASE + AR913X_EHCI_SIZE - 1;
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ath79_ehci_device.name = "ar913x-ehci";
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platform_device_register(&ath79_ehci_device);
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}
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void __init ath79_register_usb(void)
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{
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if (soc_is_ar71xx())
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ath79_usb_setup();
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else if (soc_is_ar7240())
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ar7240_usb_setup();
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else if (soc_is_ar7241() || soc_is_ar7242())
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ar724x_usb_setup();
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else if (soc_is_ar913x())
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ar913x_usb_setup();
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else
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BUG();
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}
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@ -0,0 +1,17 @@
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/*
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* Atheros AR71XX/AR724X/AR913X USB Host Controller support
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*
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* Copyright (C) 2008-2010 Gabor Juhos <juhosg@openwrt.org>
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* Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License version 2 as published
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* by the Free Software Foundation.
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*/
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#ifndef _ATH79_DEV_USB_H
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#define _ATH79_DEV_USB_H
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void ath79_register_usb(void);
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#endif /* _ATH79_DEV_USB_H */
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@ -14,6 +14,7 @@
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#include "dev-gpio-buttons.h"
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#include "dev-leds-gpio.h"
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#include "dev-spi.h"
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#include "dev-usb.h"
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#define AP81_GPIO_LED_STATUS 1
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#define AP81_GPIO_LED_AOSS 3
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@ -92,6 +93,7 @@ static void __init ap81_setup(void)
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ath79_register_spi(&ap81_spi_data, ap81_spi_info,
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ARRAY_SIZE(ap81_spi_info));
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ath79_register_ar913x_wmac(cal_data);
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ath79_register_usb();
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}
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MIPS_MACHINE(ATH79_MACH_AP81, "AP81", "Atheros AP81 reference board",
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@ -18,6 +18,7 @@
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#include "dev-gpio-buttons.h"
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#include "dev-leds-gpio.h"
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#include "dev-spi.h"
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#include "dev-usb.h"
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#define PB44_GPIO_I2C_SCL 0
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#define PB44_GPIO_I2C_SDA 1
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@ -112,6 +113,7 @@ static void __init pb44_init(void)
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pb44_gpio_keys);
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ath79_register_spi(&pb44_spi_data, pb44_spi_info,
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ARRAY_SIZE(pb44_spi_info));
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ath79_register_usb();
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}
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MIPS_MACHINE(ATH79_MACH_PB44, "PB44", "Atheros PB44 reference board",
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@ -20,6 +20,10 @@
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#include <linux/bitops.h>
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#define AR71XX_APB_BASE 0x18000000
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#define AR71XX_EHCI_BASE 0x1b000000
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#define AR71XX_EHCI_SIZE 0x1000
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#define AR71XX_OHCI_BASE 0x1c000000
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#define AR71XX_OHCI_SIZE 0x1000
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#define AR71XX_SPI_BASE 0x1f000000
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#define AR71XX_SPI_SIZE 0x01000000
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@ -27,6 +31,8 @@
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#define AR71XX_DDR_CTRL_SIZE 0x100
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#define AR71XX_UART_BASE (AR71XX_APB_BASE + 0x00020000)
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#define AR71XX_UART_SIZE 0x100
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#define AR71XX_USB_CTRL_BASE (AR71XX_APB_BASE + 0x00030000)
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#define AR71XX_USB_CTRL_SIZE 0x100
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#define AR71XX_GPIO_BASE (AR71XX_APB_BASE + 0x00040000)
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#define AR71XX_GPIO_SIZE 0x100
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#define AR71XX_PLL_BASE (AR71XX_APB_BASE + 0x00050000)
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@ -34,6 +40,16 @@
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#define AR71XX_RESET_BASE (AR71XX_APB_BASE + 0x00060000)
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#define AR71XX_RESET_SIZE 0x100
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#define AR7240_USB_CTRL_BASE (AR71XX_APB_BASE + 0x00030000)
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#define AR7240_USB_CTRL_SIZE 0x100
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#define AR7240_OHCI_BASE 0x1b000000
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#define AR7240_OHCI_SIZE 0x1000
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#define AR724X_EHCI_BASE 0x1b000000
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#define AR724X_EHCI_SIZE 0x1000
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#define AR913X_EHCI_BASE 0x1b000000
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#define AR913X_EHCI_SIZE 0x1000
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#define AR913X_WMAC_BASE (AR71XX_APB_BASE + 0x000C0000)
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#define AR913X_WMAC_SIZE 0x30000
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@ -104,6 +120,12 @@
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#define AR913X_AHB_DIV_SHIFT 19
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#define AR913X_AHB_DIV_MASK 0x1
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/*
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* USB_CONFIG block
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*/
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#define AR71XX_USB_CTRL_REG_FLADJ 0x00
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#define AR71XX_USB_CTRL_REG_CONFIG 0x04
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/*
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* RESET block
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*/
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@ -162,14 +184,22 @@
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#define AR71XX_RESET_PCI_BUS BIT(1)
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#define AR71XX_RESET_PCI_CORE BIT(0)
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#define AR7240_RESET_USB_HOST BIT(5)
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#define AR7240_RESET_OHCI_DLL BIT(3)
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#define AR724X_RESET_GE1_MDIO BIT(23)
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#define AR724X_RESET_GE0_MDIO BIT(22)
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#define AR724X_RESET_PCIE_PHY_SERIAL BIT(10)
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#define AR724X_RESET_PCIE_PHY BIT(7)
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#define AR724X_RESET_PCIE BIT(6)
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#define AR724X_RESET_OHCI_DLL BIT(3)
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#define AR724X_RESET_USB_HOST BIT(5)
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#define AR724X_RESET_USB_PHY BIT(4)
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#define AR724X_RESET_USBSUS_OVERRIDE BIT(3)
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#define AR913X_RESET_AMBA2WMAC BIT(22)
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#define AR913X_RESET_USBSUS_OVERRIDE BIT(10)
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#define AR913X_RESET_USB_HOST BIT(5)
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#define AR913X_RESET_USB_PHY BIT(4)
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#define REV_ID_MAJOR_MASK 0xfff0
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#define REV_ID_MAJOR_AR71XX 0x00a0
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