Merge tag 'drm-intel-fixes-2016-11-01' of git://anongit.freedesktop.org/drm-intel into drm-fixes
batch of scattered i915 fixes. * tag 'drm-intel-fixes-2016-11-01' of git://anongit.freedesktop.org/drm-intel: drm/i915: Fix SKL+ 90/270 degree rotated plane coordinate computation drm/i915: Remove two invalid warns drm/i915: Rotated view does not need a fence drm/i915/fbc: fix CFB size calculation for gen8+ drm: i915: Wait for fences on new fb, not old drm/i915: Clean up DDI DDC/AUX CH sanitation drm/i915: Respect alternate_aux_channel for all DDI ports drm/i915/gen9: fix watermarks when using the pipe scaler drm/i915: Fix mismatched INIT power domain disabling during suspend drm/i915: fix a read size argument drm/i915: Use fence_write() from rpm resume drm/i915/gen9: fix DDB partitioning for multi-screen cases drm/i915: workaround sparse warning on variable length arrays drm/i915: keep declarations in i915_drv.h
This commit is contained in:
Dave Airlie
Коммит
7ec30fca2c
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@ -1447,8 +1447,6 @@ static int i915_drm_suspend(struct drm_device *dev)
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dev_priv->suspend_count++;
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intel_display_set_init_power(dev_priv, false);
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intel_csr_ucode_suspend(dev_priv);
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out:
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@ -1466,6 +1464,8 @@ static int i915_drm_suspend_late(struct drm_device *dev, bool hibernation)
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disable_rpm_wakeref_asserts(dev_priv);
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intel_display_set_init_power(dev_priv, false);
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fw_csr = !IS_BROXTON(dev_priv) &&
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suspend_to_idle(dev_priv) && dev_priv->csr.dmc_payload;
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/*
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@ -2883,6 +2883,11 @@ __i915_printk(struct drm_i915_private *dev_priv, const char *level,
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extern long i915_compat_ioctl(struct file *filp, unsigned int cmd,
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unsigned long arg);
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#endif
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extern const struct dev_pm_ops i915_pm_ops;
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extern int i915_driver_load(struct pci_dev *pdev,
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const struct pci_device_id *ent);
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extern void i915_driver_unload(struct drm_device *dev);
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extern int intel_gpu_reset(struct drm_i915_private *dev_priv, u32 engine_mask);
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extern bool intel_has_gpu_reset(struct drm_i915_private *dev_priv);
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extern void i915_reset(struct drm_i915_private *dev_priv);
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@ -3550,8 +3550,6 @@ i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object *obj,
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vma->display_alignment = max_t(u64, vma->display_alignment, alignment);
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WARN_ON(obj->pin_display > i915_vma_pin_count(vma));
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i915_gem_object_flush_cpu_write_domain(obj);
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old_write_domain = obj->base.write_domain;
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@ -3588,7 +3586,6 @@ i915_gem_object_unpin_from_display_plane(struct i915_vma *vma)
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list_move_tail(&vma->vm_link, &vma->vm->inactive_list);
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i915_vma_unpin(vma);
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WARN_ON(vma->obj->pin_display > i915_vma_pin_count(vma));
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}
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/**
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@ -3745,7 +3742,12 @@ void __i915_vma_set_map_and_fenceable(struct i915_vma *vma)
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mappable = (vma->node.start + fence_size <=
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dev_priv->ggtt.mappable_end);
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if (mappable && fenceable)
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/*
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* Explicitly disable for rotated VMA since the display does not
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* need the fence and the VMA is not accessible to other users.
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*/
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if (mappable && fenceable &&
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vma->ggtt_view.type != I915_GGTT_VIEW_ROTATED)
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vma->flags |= I915_VMA_CAN_FENCE;
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else
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vma->flags &= ~I915_VMA_CAN_FENCE;
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@ -290,6 +290,8 @@ i915_vma_put_fence(struct i915_vma *vma)
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{
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struct drm_i915_fence_reg *fence = vma->fence;
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assert_rpm_wakelock_held(to_i915(vma->vm->dev));
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if (!fence)
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return 0;
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@ -341,6 +343,8 @@ i915_vma_get_fence(struct i915_vma *vma)
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struct drm_i915_fence_reg *fence;
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struct i915_vma *set = i915_gem_object_is_tiled(vma->obj) ? vma : NULL;
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assert_rpm_wakelock_held(to_i915(vma->vm->dev));
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/* Just update our place in the LRU if our fence is getting reused. */
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if (vma->fence) {
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fence = vma->fence;
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@ -371,6 +375,12 @@ void i915_gem_restore_fences(struct drm_device *dev)
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struct drm_i915_private *dev_priv = to_i915(dev);
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int i;
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/* Note that this may be called outside of struct_mutex, by
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* runtime suspend/resume. The barrier we require is enforced by
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* rpm itself - all access to fences/GTT are only within an rpm
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* wakeref, and to acquire that wakeref you must pass through here.
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*/
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for (i = 0; i < dev_priv->num_fence_regs; i++) {
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struct drm_i915_fence_reg *reg = &dev_priv->fence_regs[i];
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struct i915_vma *vma = reg->vma;
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@ -379,10 +389,17 @@ void i915_gem_restore_fences(struct drm_device *dev)
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* Commit delayed tiling changes if we have an object still
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* attached to the fence, otherwise just clear the fence.
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*/
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if (vma && !i915_gem_object_is_tiled(vma->obj))
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vma = NULL;
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if (vma && !i915_gem_object_is_tiled(vma->obj)) {
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GEM_BUG_ON(!reg->dirty);
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GEM_BUG_ON(vma->obj->fault_mappable);
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fence_update(reg, vma);
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list_move(®->link, &dev_priv->mm.fence_list);
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vma->fence = NULL;
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vma = NULL;
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}
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fence_write(reg, vma);
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reg->vma = vma;
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}
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}
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@ -431,9 +431,6 @@ static const struct pci_device_id pciidlist[] = {
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};
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MODULE_DEVICE_TABLE(pci, pciidlist);
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extern int i915_driver_load(struct pci_dev *pdev,
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const struct pci_device_id *ent);
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static int i915_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
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{
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struct intel_device_info *intel_info =
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@ -463,8 +460,6 @@ static int i915_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
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return i915_driver_load(pdev, ent);
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}
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extern void i915_driver_unload(struct drm_device *dev);
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static void i915_pci_remove(struct pci_dev *pdev)
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{
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struct drm_device *dev = pci_get_drvdata(pdev);
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@ -473,8 +468,6 @@ static void i915_pci_remove(struct pci_dev *pdev)
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drm_dev_unref(dev);
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}
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extern const struct dev_pm_ops i915_pm_ops;
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static struct pci_driver i915_pci_driver = {
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.name = DRIVER_NAME,
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.id_table = pciidlist,
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@ -1031,6 +1031,77 @@ static u8 translate_iboost(u8 val)
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return mapping[val];
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}
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static void sanitize_ddc_pin(struct drm_i915_private *dev_priv,
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enum port port)
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{
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const struct ddi_vbt_port_info *info =
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&dev_priv->vbt.ddi_port_info[port];
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enum port p;
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if (!info->alternate_ddc_pin)
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return;
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for_each_port_masked(p, (1 << port) - 1) {
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struct ddi_vbt_port_info *i = &dev_priv->vbt.ddi_port_info[p];
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if (info->alternate_ddc_pin != i->alternate_ddc_pin)
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continue;
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DRM_DEBUG_KMS("port %c trying to use the same DDC pin (0x%x) as port %c, "
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"disabling port %c DVI/HDMI support\n",
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port_name(p), i->alternate_ddc_pin,
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port_name(port), port_name(p));
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/*
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* If we have multiple ports supposedly sharing the
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* pin, then dvi/hdmi couldn't exist on the shared
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* port. Otherwise they share the same ddc bin and
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* system couldn't communicate with them separately.
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*
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* Due to parsing the ports in alphabetical order,
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* a higher port will always clobber a lower one.
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*/
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i->supports_dvi = false;
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i->supports_hdmi = false;
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i->alternate_ddc_pin = 0;
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}
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}
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static void sanitize_aux_ch(struct drm_i915_private *dev_priv,
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enum port port)
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{
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const struct ddi_vbt_port_info *info =
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&dev_priv->vbt.ddi_port_info[port];
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enum port p;
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if (!info->alternate_aux_channel)
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return;
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for_each_port_masked(p, (1 << port) - 1) {
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struct ddi_vbt_port_info *i = &dev_priv->vbt.ddi_port_info[p];
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if (info->alternate_aux_channel != i->alternate_aux_channel)
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continue;
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DRM_DEBUG_KMS("port %c trying to use the same AUX CH (0x%x) as port %c, "
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"disabling port %c DP support\n",
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port_name(p), i->alternate_aux_channel,
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port_name(port), port_name(p));
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/*
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* If we have multiple ports supposedlt sharing the
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* aux channel, then DP couldn't exist on the shared
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* port. Otherwise they share the same aux channel
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* and system couldn't communicate with them separately.
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*
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* Due to parsing the ports in alphabetical order,
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* a higher port will always clobber a lower one.
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*/
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i->supports_dp = false;
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i->alternate_aux_channel = 0;
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}
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}
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static void parse_ddi_port(struct drm_i915_private *dev_priv, enum port port,
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const struct bdb_header *bdb)
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{
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@ -1105,54 +1176,15 @@ static void parse_ddi_port(struct drm_i915_private *dev_priv, enum port port,
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DRM_DEBUG_KMS("Port %c is internal DP\n", port_name(port));
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if (is_dvi) {
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if (port == PORT_E) {
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info->alternate_ddc_pin = ddc_pin;
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/* if DDIE share ddc pin with other port, then
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* dvi/hdmi couldn't exist on the shared port.
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* Otherwise they share the same ddc bin and system
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* couldn't communicate with them seperately. */
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if (ddc_pin == DDC_PIN_B) {
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dev_priv->vbt.ddi_port_info[PORT_B].supports_dvi = 0;
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dev_priv->vbt.ddi_port_info[PORT_B].supports_hdmi = 0;
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} else if (ddc_pin == DDC_PIN_C) {
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dev_priv->vbt.ddi_port_info[PORT_C].supports_dvi = 0;
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dev_priv->vbt.ddi_port_info[PORT_C].supports_hdmi = 0;
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} else if (ddc_pin == DDC_PIN_D) {
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dev_priv->vbt.ddi_port_info[PORT_D].supports_dvi = 0;
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dev_priv->vbt.ddi_port_info[PORT_D].supports_hdmi = 0;
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}
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} else if (ddc_pin == DDC_PIN_B && port != PORT_B)
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DRM_DEBUG_KMS("Unexpected DDC pin for port B\n");
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else if (ddc_pin == DDC_PIN_C && port != PORT_C)
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DRM_DEBUG_KMS("Unexpected DDC pin for port C\n");
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else if (ddc_pin == DDC_PIN_D && port != PORT_D)
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DRM_DEBUG_KMS("Unexpected DDC pin for port D\n");
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info->alternate_ddc_pin = ddc_pin;
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sanitize_ddc_pin(dev_priv, port);
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}
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if (is_dp) {
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if (port == PORT_E) {
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info->alternate_aux_channel = aux_channel;
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/* if DDIE share aux channel with other port, then
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* DP couldn't exist on the shared port. Otherwise
|
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* they share the same aux channel and system
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* couldn't communicate with them seperately. */
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if (aux_channel == DP_AUX_A)
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dev_priv->vbt.ddi_port_info[PORT_A].supports_dp = 0;
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else if (aux_channel == DP_AUX_B)
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dev_priv->vbt.ddi_port_info[PORT_B].supports_dp = 0;
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else if (aux_channel == DP_AUX_C)
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dev_priv->vbt.ddi_port_info[PORT_C].supports_dp = 0;
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else if (aux_channel == DP_AUX_D)
|
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dev_priv->vbt.ddi_port_info[PORT_D].supports_dp = 0;
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}
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else if (aux_channel == DP_AUX_A && port != PORT_A)
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DRM_DEBUG_KMS("Unexpected AUX channel for port A\n");
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else if (aux_channel == DP_AUX_B && port != PORT_B)
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DRM_DEBUG_KMS("Unexpected AUX channel for port B\n");
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else if (aux_channel == DP_AUX_C && port != PORT_C)
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DRM_DEBUG_KMS("Unexpected AUX channel for port C\n");
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else if (aux_channel == DP_AUX_D && port != PORT_D)
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DRM_DEBUG_KMS("Unexpected AUX channel for port D\n");
|
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info->alternate_aux_channel = aux_channel;
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|
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sanitize_aux_ch(dev_priv, port);
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}
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|
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if (bdb->version >= 158) {
|
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|
|
|
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|
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@ -192,7 +192,7 @@ static void broadwell_sseu_info_init(struct drm_i915_private *dev_priv)
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struct sseu_dev_info *sseu = &mkwrite_device_info(dev_priv)->sseu;
|
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const int s_max = 3, ss_max = 3, eu_max = 8;
|
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int s, ss;
|
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u32 fuse2, eu_disable[s_max];
|
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u32 fuse2, eu_disable[3]; /* s_max */
|
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|
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fuse2 = I915_READ(GEN8_FUSE2);
|
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sseu->slice_mask = (fuse2 & GEN8_F2_S_ENA_MASK) >> GEN8_F2_S_ENA_SHIFT;
|
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|
|
|
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|
|
@ -2978,7 +2978,8 @@ int skl_check_plane_surface(struct intel_plane_state *plane_state)
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|||
/* Rotate src coordinates to match rotated GTT view */
|
||||
if (intel_rotation_90_or_270(rotation))
|
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drm_rect_rotate(&plane_state->base.src,
|
||||
fb->width, fb->height, DRM_ROTATE_270);
|
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fb->width << 16, fb->height << 16,
|
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DRM_ROTATE_270);
|
||||
|
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/*
|
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* Handle the AUX surface first since
|
||||
|
|
@ -14310,7 +14311,7 @@ static void intel_atomic_commit_tail(struct drm_atomic_state *state)
|
|||
|
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for_each_plane_in_state(state, plane, plane_state, i) {
|
||||
struct intel_plane_state *intel_plane_state =
|
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to_intel_plane_state(plane_state);
|
||||
to_intel_plane_state(plane->state);
|
||||
|
||||
if (!intel_plane_state->wait_req)
|
||||
continue;
|
||||
|
|
|
|||
|
|
@ -1108,6 +1108,44 @@ intel_dp_aux_transfer(struct drm_dp_aux *aux, struct drm_dp_aux_msg *msg)
|
|||
return ret;
|
||||
}
|
||||
|
||||
static enum port intel_aux_port(struct drm_i915_private *dev_priv,
|
||||
enum port port)
|
||||
{
|
||||
const struct ddi_vbt_port_info *info =
|
||||
&dev_priv->vbt.ddi_port_info[port];
|
||||
enum port aux_port;
|
||||
|
||||
if (!info->alternate_aux_channel) {
|
||||
DRM_DEBUG_KMS("using AUX %c for port %c (platform default)\n",
|
||||
port_name(port), port_name(port));
|
||||
return port;
|
||||
}
|
||||
|
||||
switch (info->alternate_aux_channel) {
|
||||
case DP_AUX_A:
|
||||
aux_port = PORT_A;
|
||||
break;
|
||||
case DP_AUX_B:
|
||||
aux_port = PORT_B;
|
||||
break;
|
||||
case DP_AUX_C:
|
||||
aux_port = PORT_C;
|
||||
break;
|
||||
case DP_AUX_D:
|
||||
aux_port = PORT_D;
|
||||
break;
|
||||
default:
|
||||
MISSING_CASE(info->alternate_aux_channel);
|
||||
aux_port = PORT_A;
|
||||
break;
|
||||
}
|
||||
|
||||
DRM_DEBUG_KMS("using AUX %c for port %c (VBT)\n",
|
||||
port_name(aux_port), port_name(port));
|
||||
|
||||
return aux_port;
|
||||
}
|
||||
|
||||
static i915_reg_t g4x_aux_ctl_reg(struct drm_i915_private *dev_priv,
|
||||
enum port port)
|
||||
{
|
||||
|
|
@ -1168,36 +1206,9 @@ static i915_reg_t ilk_aux_data_reg(struct drm_i915_private *dev_priv,
|
|||
}
|
||||
}
|
||||
|
||||
/*
|
||||
* On SKL we don't have Aux for port E so we rely
|
||||
* on VBT to set a proper alternate aux channel.
|
||||
*/
|
||||
static enum port skl_porte_aux_port(struct drm_i915_private *dev_priv)
|
||||
{
|
||||
const struct ddi_vbt_port_info *info =
|
||||
&dev_priv->vbt.ddi_port_info[PORT_E];
|
||||
|
||||
switch (info->alternate_aux_channel) {
|
||||
case DP_AUX_A:
|
||||
return PORT_A;
|
||||
case DP_AUX_B:
|
||||
return PORT_B;
|
||||
case DP_AUX_C:
|
||||
return PORT_C;
|
||||
case DP_AUX_D:
|
||||
return PORT_D;
|
||||
default:
|
||||
MISSING_CASE(info->alternate_aux_channel);
|
||||
return PORT_A;
|
||||
}
|
||||
}
|
||||
|
||||
static i915_reg_t skl_aux_ctl_reg(struct drm_i915_private *dev_priv,
|
||||
enum port port)
|
||||
{
|
||||
if (port == PORT_E)
|
||||
port = skl_porte_aux_port(dev_priv);
|
||||
|
||||
switch (port) {
|
||||
case PORT_A:
|
||||
case PORT_B:
|
||||
|
|
@ -1213,9 +1224,6 @@ static i915_reg_t skl_aux_ctl_reg(struct drm_i915_private *dev_priv,
|
|||
static i915_reg_t skl_aux_data_reg(struct drm_i915_private *dev_priv,
|
||||
enum port port, int index)
|
||||
{
|
||||
if (port == PORT_E)
|
||||
port = skl_porte_aux_port(dev_priv);
|
||||
|
||||
switch (port) {
|
||||
case PORT_A:
|
||||
case PORT_B:
|
||||
|
|
@ -1253,7 +1261,8 @@ static i915_reg_t intel_aux_data_reg(struct drm_i915_private *dev_priv,
|
|||
static void intel_aux_reg_init(struct intel_dp *intel_dp)
|
||||
{
|
||||
struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
|
||||
enum port port = dp_to_dig_port(intel_dp)->port;
|
||||
enum port port = intel_aux_port(dev_priv,
|
||||
dp_to_dig_port(intel_dp)->port);
|
||||
int i;
|
||||
|
||||
intel_dp->aux_ch_ctl_reg = intel_aux_ctl_reg(dev_priv, port);
|
||||
|
|
@ -3551,8 +3560,8 @@ intel_edp_init_dpcd(struct intel_dp *intel_dp)
|
|||
/* Read the eDP Display control capabilities registers */
|
||||
if ((intel_dp->dpcd[DP_EDP_CONFIGURATION_CAP] & DP_DPCD_DISPLAY_CONTROL_CAPABLE) &&
|
||||
drm_dp_dpcd_read(&intel_dp->aux, DP_EDP_DPCD_REV,
|
||||
intel_dp->edp_dpcd, sizeof(intel_dp->edp_dpcd) ==
|
||||
sizeof(intel_dp->edp_dpcd)))
|
||||
intel_dp->edp_dpcd, sizeof(intel_dp->edp_dpcd)) ==
|
||||
sizeof(intel_dp->edp_dpcd))
|
||||
DRM_DEBUG_KMS("EDP DPCD : %*ph\n", (int) sizeof(intel_dp->edp_dpcd),
|
||||
intel_dp->edp_dpcd);
|
||||
|
||||
|
|
|
|||
|
|
@ -104,8 +104,10 @@ static int intel_fbc_calculate_cfb_size(struct drm_i915_private *dev_priv,
|
|||
int lines;
|
||||
|
||||
intel_fbc_get_plane_source_size(cache, NULL, &lines);
|
||||
if (INTEL_INFO(dev_priv)->gen >= 7)
|
||||
if (INTEL_GEN(dev_priv) == 7)
|
||||
lines = min(lines, 2048);
|
||||
else if (INTEL_GEN(dev_priv) >= 8)
|
||||
lines = min(lines, 2560);
|
||||
|
||||
/* Hardware needs the full buffer stride, not just the active area. */
|
||||
return lines * cache->fb.stride;
|
||||
|
|
|
|||
|
|
@ -3362,13 +3362,15 @@ skl_allocate_pipe_ddb(struct intel_crtc_state *cstate,
|
|||
int num_active;
|
||||
int id, i;
|
||||
|
||||
/* Clear the partitioning for disabled planes. */
|
||||
memset(ddb->plane[pipe], 0, sizeof(ddb->plane[pipe]));
|
||||
memset(ddb->y_plane[pipe], 0, sizeof(ddb->y_plane[pipe]));
|
||||
|
||||
if (WARN_ON(!state))
|
||||
return 0;
|
||||
|
||||
if (!cstate->base.active) {
|
||||
ddb->pipe[pipe].start = ddb->pipe[pipe].end = 0;
|
||||
memset(ddb->plane[pipe], 0, sizeof(ddb->plane[pipe]));
|
||||
memset(ddb->y_plane[pipe], 0, sizeof(ddb->y_plane[pipe]));
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
|
@ -3468,12 +3470,6 @@ skl_allocate_pipe_ddb(struct intel_crtc_state *cstate,
|
|||
return 0;
|
||||
}
|
||||
|
||||
static uint32_t skl_pipe_pixel_rate(const struct intel_crtc_state *config)
|
||||
{
|
||||
/* TODO: Take into account the scalers once we support them */
|
||||
return config->base.adjusted_mode.crtc_clock;
|
||||
}
|
||||
|
||||
/*
|
||||
* The max latency should be 257 (max the punit can code is 255 and we add 2us
|
||||
* for the read latency) and cpp should always be <= 8, so that
|
||||
|
|
@ -3524,7 +3520,7 @@ static uint32_t skl_adjusted_plane_pixel_rate(const struct intel_crtc_state *cst
|
|||
* Adjusted plane pixel rate is just the pipe's adjusted pixel rate
|
||||
* with additional adjustments for plane-specific scaling.
|
||||
*/
|
||||
adjusted_pixel_rate = skl_pipe_pixel_rate(cstate);
|
||||
adjusted_pixel_rate = ilk_pipe_pixel_rate(cstate);
|
||||
downscale_amount = skl_plane_downscale_amount(pstate);
|
||||
|
||||
pixel_rate = adjusted_pixel_rate * downscale_amount >> 16;
|
||||
|
|
@ -3736,11 +3732,11 @@ skl_compute_linetime_wm(struct intel_crtc_state *cstate)
|
|||
if (!cstate->base.active)
|
||||
return 0;
|
||||
|
||||
if (WARN_ON(skl_pipe_pixel_rate(cstate) == 0))
|
||||
if (WARN_ON(ilk_pipe_pixel_rate(cstate) == 0))
|
||||
return 0;
|
||||
|
||||
return DIV_ROUND_UP(8 * cstate->base.adjusted_mode.crtc_htotal * 1000,
|
||||
skl_pipe_pixel_rate(cstate));
|
||||
ilk_pipe_pixel_rate(cstate));
|
||||
}
|
||||
|
||||
static void skl_compute_transition_wm(struct intel_crtc_state *cstate,
|
||||
|
|
@ -4050,6 +4046,12 @@ skl_compute_ddb(struct drm_atomic_state *state)
|
|||
intel_state->wm_results.dirty_pipes = ~0;
|
||||
}
|
||||
|
||||
/*
|
||||
* We're not recomputing for the pipes not included in the commit, so
|
||||
* make sure we start with the current state.
|
||||
*/
|
||||
memcpy(ddb, &dev_priv->wm.skl_hw.ddb, sizeof(*ddb));
|
||||
|
||||
for_each_intel_crtc_mask(dev, intel_crtc, realloc_pipes) {
|
||||
struct intel_crtc_state *cstate;
|
||||
|
||||
|
|
|
|||
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Ссылка в новой задаче