ASoC: tlv320aic31xx: Choose PLL p divider automatically
This simplifies aic31xx_divs table. There is no more need for p_val or separate lines for 12 and 24 MHz mclks. Signed-off-by: Jyri Sarha <jsarha@ti.com> Tested-by: Peter Ujfalusi <peter.ujfalusi@ti.com> Signed-off-by: Mark Brown <broonie@kernel.org>
This commit is contained in:
Jyri Sarha
Mark Brown
Родитель
94fe356f4c
Коммит
7ed36e96fd
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@ -167,13 +167,13 @@ struct aic31xx_priv {
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struct regulator_bulk_data supplies[AIC31XX_NUM_SUPPLIES];
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struct aic31xx_disable_nb disable_nb[AIC31XX_NUM_SUPPLIES];
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unsigned int sysclk;
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u8 p_div;
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int rate_div_line;
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};
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struct aic31xx_rate_divs {
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u32 mclk;
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u32 mclk_p;
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u32 rate;
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u8 p_val;
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u8 pll_j;
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u16 pll_d;
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u16 dosr;
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@ -186,62 +186,51 @@ struct aic31xx_rate_divs {
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/* ADC dividers can be disabled by cofiguring them to 0 */
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static const struct aic31xx_rate_divs aic31xx_divs[] = {
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/* mclk rate pll: p j d dosr ndac mdac aors nadc madc */
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/* mclk/p rate pll: j d dosr ndac mdac aors nadc madc */
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/* 8k rate */
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{12000000, 8000, 1, 8, 1920, 128, 48, 2, 128, 48, 2},
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{12000000, 8000, 1, 8, 1920, 128, 32, 3, 128, 32, 3},
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{24000000, 8000, 2, 8, 1920, 128, 48, 2, 128, 48, 2},
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{25000000, 8000, 2, 7, 8643, 128, 48, 2, 128, 48, 2},
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{12000000, 8000, 8, 1920, 128, 48, 2, 128, 48, 2},
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{12000000, 8000, 8, 1920, 128, 32, 3, 128, 32, 3},
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{12500000, 8000, 7, 8643, 128, 48, 2, 128, 48, 2},
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/* 11.025k rate */
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{12000000, 11025, 1, 7, 5264, 128, 32, 2, 128, 32, 2},
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{12000000, 11025, 1, 8, 4672, 128, 24, 3, 128, 24, 3},
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{24000000, 11025, 2, 7, 5264, 128, 32, 2, 128, 32, 2},
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{25000000, 11025, 2, 7, 2253, 128, 32, 2, 128, 32, 2},
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{12000000, 11025, 7, 5264, 128, 32, 2, 128, 32, 2},
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{12000000, 11025, 8, 4672, 128, 24, 3, 128, 24, 3},
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{12500000, 11025, 7, 2253, 128, 32, 2, 128, 32, 2},
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/* 16k rate */
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{12000000, 16000, 1, 8, 1920, 128, 24, 2, 128, 24, 2},
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{12000000, 16000, 1, 8, 1920, 128, 16, 3, 128, 16, 3},
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{24000000, 16000, 2, 8, 1920, 128, 24, 2, 128, 24, 2},
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{25000000, 16000, 2, 7, 8643, 128, 24, 2, 128, 24, 2},
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{12000000, 16000, 8, 1920, 128, 24, 2, 128, 24, 2},
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{12000000, 16000, 8, 1920, 128, 16, 3, 128, 16, 3},
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{12500000, 16000, 7, 8643, 128, 24, 2, 128, 24, 2},
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/* 22.05k rate */
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{12000000, 22050, 1, 7, 5264, 128, 16, 2, 128, 16, 2},
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{12000000, 22050, 1, 8, 4672, 128, 12, 3, 128, 12, 3},
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{24000000, 22050, 2, 7, 5264, 128, 16, 2, 128, 16, 2},
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{25000000, 22050, 2, 7, 2253, 128, 16, 2, 128, 16, 2},
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{12000000, 22050, 7, 5264, 128, 16, 2, 128, 16, 2},
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{12000000, 22050, 8, 4672, 128, 12, 3, 128, 12, 3},
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{12500000, 22050, 7, 2253, 128, 16, 2, 128, 16, 2},
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/* 32k rate */
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{12000000, 32000, 1, 8, 1920, 128, 12, 2, 128, 12, 2},
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{12000000, 32000, 1, 8, 1920, 128, 8, 3, 128, 8, 3},
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{24000000, 32000, 2, 8, 1920, 128, 12, 2, 128, 12, 2},
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{25000000, 32000, 2, 7, 8643, 128, 12, 2, 128, 12, 2},
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{12000000, 32000, 8, 1920, 128, 12, 2, 128, 12, 2},
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{12000000, 32000, 8, 1920, 128, 8, 3, 128, 8, 3},
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{12500000, 32000, 7, 8643, 128, 12, 2, 128, 12, 2},
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/* 44.1k rate */
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{12000000, 44100, 1, 7, 5264, 128, 8, 2, 128, 8, 2},
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{12000000, 44100, 1, 8, 4672, 128, 6, 3, 128, 6, 3},
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{24000000, 44100, 2, 7, 5264, 128, 8, 2, 128, 8, 2},
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{25000000, 44100, 2, 7, 2253, 128, 8, 2, 128, 8, 2},
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{12000000, 44100, 7, 5264, 128, 8, 2, 128, 8, 2},
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{12000000, 44100, 8, 4672, 128, 6, 3, 128, 6, 3},
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{12500000, 44100, 7, 2253, 128, 8, 2, 128, 8, 2},
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/* 48k rate */
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{12000000, 48000, 1, 8, 1920, 128, 8, 2, 128, 8, 2},
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{12000000, 48000, 1, 7, 6800, 96, 5, 4, 96, 5, 4},
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{24000000, 48000, 2, 8, 1920, 128, 8, 2, 128, 8, 2},
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{25000000, 48000, 2, 7, 8643, 128, 8, 2, 128, 8, 2},
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{12000000, 48000, 8, 1920, 128, 8, 2, 128, 8, 2},
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{12000000, 48000, 7, 6800, 96, 5, 4, 96, 5, 4},
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{12500000, 48000, 7, 8643, 128, 8, 2, 128, 8, 2},
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/* 88.2k rate */
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{12000000, 88200, 1, 7, 5264, 64, 8, 2, 64, 8, 2},
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{12000000, 88200, 1, 8, 4672, 64, 6, 3, 64, 6, 3},
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{24000000, 88200, 2, 7, 5264, 64, 8, 2, 64, 8, 2},
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{25000000, 88200, 2, 7, 2253, 64, 8, 2, 64, 8, 2},
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{12000000, 88200, 7, 5264, 64, 8, 2, 64, 8, 2},
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{12000000, 88200, 8, 4672, 64, 6, 3, 64, 6, 3},
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{12500000, 88200, 7, 2253, 64, 8, 2, 64, 8, 2},
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/* 96k rate */
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{12000000, 96000, 1, 8, 1920, 64, 8, 2, 64, 8, 2},
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{12000000, 96000, 1, 7, 6800, 48, 5, 4, 48, 5, 4},
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{24000000, 96000, 2, 8, 1920, 64, 8, 2, 64, 8, 2},
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{25000000, 96000, 2, 7, 8643, 64, 8, 2, 64, 8, 2},
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{12000000, 96000, 8, 1920, 64, 8, 2, 64, 8, 2},
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{12000000, 96000, 7, 6800, 48, 5, 4, 48, 5, 4},
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{12500000, 96000, 7, 8643, 64, 8, 2, 64, 8, 2},
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/* 176.4k rate */
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{12000000, 176400, 1, 7, 5264, 32, 8, 2, 32, 8, 2},
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{12000000, 176400, 1, 8, 4672, 32, 6, 3, 32, 6, 3},
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{24000000, 176400, 2, 7, 5264, 32, 8, 2, 32, 8, 2},
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{25000000, 176400, 2, 7, 2253, 32, 8, 2, 32, 8, 2},
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{12000000, 176400, 7, 5264, 32, 8, 2, 32, 8, 2},
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{12000000, 176400, 8, 4672, 32, 6, 3, 32, 6, 3},
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{12500000, 176400, 7, 2253, 32, 8, 2, 32, 8, 2},
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/* 192k rate */
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{12000000, 192000, 1, 8, 1920, 32, 8, 2, 32, 8, 2},
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{12000000, 192000, 1, 7, 6800, 24, 5, 4, 24, 5, 4},
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{24000000, 192000, 2, 8, 1920, 32, 8, 2, 32, 8, 2},
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{25000000, 192000, 2, 7, 8643, 32, 8, 2, 32, 8, 2},
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{12000000, 192000, 8, 1920, 32, 8, 2, 32, 8, 2},
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{12000000, 192000, 7, 6800, 24, 5, 4, 24, 5, 4},
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{12500000, 192000, 7, 8643, 32, 8, 2, 32, 8, 2},
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};
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static const char * const ldac_in_text[] = {
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@ -692,6 +681,7 @@ static int aic31xx_setup_pll(struct snd_soc_codec *codec,
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{
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struct aic31xx_priv *aic31xx = snd_soc_codec_get_drvdata(codec);
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int bclk_score = snd_soc_params_to_frame_size(params);
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int mclk_p = aic31xx->sysclk / aic31xx->p_div;
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int bclk_n = 0;
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int match = -1;
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int i;
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@ -704,7 +694,7 @@ static int aic31xx_setup_pll(struct snd_soc_codec *codec,
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for (i = 0; i < ARRAY_SIZE(aic31xx_divs); i++) {
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if (aic31xx_divs[i].rate == params_rate(params) &&
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aic31xx_divs[i].mclk == aic31xx->sysclk) {
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aic31xx_divs[i].mclk_p == mclk_p) {
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int s = (aic31xx_divs[i].dosr * aic31xx_divs[i].mdac) %
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snd_soc_params_to_frame_size(params);
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int bn = (aic31xx_divs[i].dosr * aic31xx_divs[i].mdac) /
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@ -738,7 +728,7 @@ static int aic31xx_setup_pll(struct snd_soc_codec *codec,
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/* PLL configuration */
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snd_soc_update_bits(codec, AIC31XX_PLLPR, AIC31XX_PLL_MASK,
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(aic31xx_divs[i].p_val << 4) | 0x01);
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(aic31xx->p_div << 4) | 0x01);
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snd_soc_write(codec, AIC31XX_PLLJ, aic31xx_divs[i].pll_j);
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snd_soc_write(codec, AIC31XX_PLLDMSB,
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@ -772,7 +762,7 @@ static int aic31xx_setup_pll(struct snd_soc_codec *codec,
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dev_dbg(codec->dev,
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"pll %d.%04d/%d dosr %d n %d m %d aosr %d n %d m %d bclk_n %d\n",
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aic31xx_divs[i].pll_j, aic31xx_divs[i].pll_d,
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aic31xx_divs[i].p_val, aic31xx_divs[i].dosr,
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aic31xx->p_div, aic31xx_divs[i].dosr,
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aic31xx_divs[i].ndac, aic31xx_divs[i].mdac,
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aic31xx_divs[i].aosr, aic31xx_divs[i].nadc,
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aic31xx_divs[i].madc, bclk_n);
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@ -912,7 +902,16 @@ static int aic31xx_set_dai_sysclk(struct snd_soc_dai *codec_dai,
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dev_dbg(codec->dev, "## %s: clk_id = %d, freq = %d, dir = %d\n",
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__func__, clk_id, freq, dir);
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for (i = 0; aic31xx_divs[i].mclk != freq; i++) {
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for (i = 1; freq/i > 20000000 && i < 8; i++)
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;
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if (freq/i > 20000000) {
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dev_err(aic31xx->dev, "%s: Too high mclk frequency %u\n",
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__func__, freq);
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return -EINVAL;
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}
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aic31xx->p_div = i;
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for (i = 0; aic31xx_divs[i].mclk_p != freq/aic31xx->p_div; i++) {
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if (i == ARRAY_SIZE(aic31xx_divs)) {
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dev_err(aic31xx->dev, "%s: Unsupported frequency %d\n",
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__func__, freq);
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