Allwinner clock fixes for 4.11

A few fixes for a bunch of clocks on a few SoCs. The most important one is
 probably one that fixes the NKMP clock frequency calculation and could end
 up with clocking the CPU frequency to out of bounds rates.
 -----BEGIN PGP SIGNATURE-----
 
 iQIcBAABCAAGBQJYz6SKAAoJEBx+YmzsjxAgDOwP/RIJDNpZJNr7b2tiqzLCAgr2
 yYJ9+sO/qBQ3gV2MhusE8BApvjWqTaiuOR/SO53tpGiC/5eX30JzlwTRuf4tLcpe
 sug8KYvL1VHgnQISo4oa+zUglWv0TFZYZKBC5IQhRq01OGo9bHhs/+nSyKpYYQA2
 T+NO8UbeVwOaPGGxYsA0edXtbnqAlDlWeZAxq+smZFyk3q95+O2vYLGRAxGNPK7s
 X8V91Q38ysB7RxeTbyKYd2VdyCqrAupF3OMGnybxpvfQ6ndNjUPe54ljvAlVIV4p
 51i7U4Ayr6YeTmgYYq4wsXWKmxoRtaauIeW0ZuGaCaNjTXY28r68qOVUignHTlRU
 XuV0cfhzxUYp8qbSpS0LEXBWc4aL52V1najYfDMY9tKsc42bhogc//kkssha9dI7
 uvPn4FBg7QsmgFZJwnIL9mujCJGByU1pN1+6JR0oSw5n3cnOyqq5LltyEbFHmGAc
 JTt+a03029fVyvxXa1BQYv05W9ANBqnF13puVRoywGmcRL2L2ytyzhrNSQhuOhSB
 /8kos+IOvrkeMgyCMmT0LGCdls4yd3wH0rl6r3ZNqyZHgD4LF9Qm5/L73GJkRHZP
 ymOU6sTonPsBir/T95PT/LYfsl3wF2YpmrqCuTPyF/Lek24d0SU5s5DO3XRSqKxS
 quM4ey2fux1Qre0OjLJk
 =27Fn
 -----END PGP SIGNATURE-----

Merge tag 'sunxi-clk-fixes-for-4.11' of https://git.kernel.org/pub/scm/linux/kernel/git/mripard/linux into clk-fixes

Pull Allwinner clock fixes from Maxime Ripard:

A few fixes for a bunch of clocks on a few SoCs. The most important one is
probably one that fixes the NKMP clock frequency calculation and could end
up with clocking the CPU frequency to out of bounds rates.

* tag 'sunxi-clk-fixes-for-4.11' of https://git.kernel.org/pub/scm/linux/kernel/git/mripard/linux:
  clk: sunxi-ng: fix recalc_rate formula of NKMP clocks
  clk: sunxi-ng: Fix div/mult settings for osc12M on A64
  clk: sunxi-ng: sun6i: Fix enable bit offset for hdmi-ddc module clock
  clk: sunxi: ccu-sun5i needs nkmp
  clk: sunxi-ng: mp: Adjust parent rate for pre-dividers

drivers/clk/sunxi-ng/Kconfig

@@ -80,6 +80,7 @@ config SUN6I_A31_CCU
 	select SUNXI_CCU_DIV
 	select SUNXI_CCU_NK
 	select SUNXI_CCU_NKM
+	select SUNXI_CCU_NKMP
 	select SUNXI_CCU_NM
 	select SUNXI_CCU_MP
 	select SUNXI_CCU_PHASE

drivers/clk/sunxi-ng/ccu-sun50i-a64.c

@@ -566,7 +566,7 @@ static SUNXI_CCU_M_WITH_GATE(gpu_clk, "gpu", "pll-gpu",
 			     0x1a0, 0, 3, BIT(31), CLK_SET_RATE_PARENT);
 
 /* Fixed Factor clocks */
-static CLK_FIXED_FACTOR(osc12M_clk, "osc12M", "osc24M", 1, 2, 0);
+static CLK_FIXED_FACTOR(osc12M_clk, "osc12M", "osc24M", 2, 1, 0);
 
 /* We hardcode the divider to 4 for now */
 static CLK_FIXED_FACTOR(pll_audio_clk, "pll-audio",

drivers/clk/sunxi-ng/ccu-sun6i-a31.c

@@ -608,7 +608,7 @@ static SUNXI_CCU_M_WITH_MUX_GATE(hdmi_clk, "hdmi", lcd_ch1_parents,
 				 0x150, 0, 4, 24, 2, BIT(31),
 				 CLK_SET_RATE_PARENT);
 
-static SUNXI_CCU_GATE(hdmi_ddc_clk, "hdmi-ddc", "osc24M", 0x150, BIT(31), 0);
+static SUNXI_CCU_GATE(hdmi_ddc_clk, "hdmi-ddc", "osc24M", 0x150, BIT(30), 0);
 
 static SUNXI_CCU_GATE(ps_clk, "ps", "lcd1-ch1", 0x140, BIT(31), 0);
 

drivers/clk/sunxi-ng/ccu_mp.c

@@ -85,6 +85,10 @@ static unsigned long ccu_mp_recalc_rate(struct clk_hw *hw,
 	unsigned int m, p;
 	u32 reg;
 
+	/* Adjust parent_rate according to pre-dividers */
+	ccu_mux_helper_adjust_parent_for_prediv(&cmp->common, &cmp->mux,
+						-1, &parent_rate);
+
 	reg = readl(cmp->common.base + cmp->common.reg);
 
 	m = reg >> cmp->m.shift;
@@ -117,6 +121,10 @@ static int ccu_mp_set_rate(struct clk_hw *hw, unsigned long rate,
 	unsigned int m, p;
 	u32 reg;
 
+	/* Adjust parent_rate according to pre-dividers */
+	ccu_mux_helper_adjust_parent_for_prediv(&cmp->common, &cmp->mux,
+						-1, &parent_rate);
+
 	max_m = cmp->m.max ?: 1 << cmp->m.width;
 	max_p = cmp->p.max ?: 1 << ((1 << cmp->p.width) - 1);
 

drivers/clk/sunxi-ng/ccu_nkmp.c

@@ -107,7 +107,7 @@ static unsigned long ccu_nkmp_recalc_rate(struct clk_hw *hw,
 	p = reg >> nkmp->p.shift;
 	p &= (1 << nkmp->p.width) - 1;
 
-	return parent_rate * n * k >> p / m;
+	return (parent_rate * n * k >> p) / m;
 }
 
 static long ccu_nkmp_round_rate(struct clk_hw *hw, unsigned long rate,