ARC: [mm] remove the pessimistic all-alias-invalidate icache helpers
No users of this code anymore - so RIP ! Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
This commit is contained in:
Vineet Gupta
Родитель
94bad1afee
Коммит
7f250a0fa1
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@ -72,16 +72,6 @@
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#include <asm/cachectl.h>
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#include <asm/setup.h>
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#ifdef CONFIG_ARC_HAS_ICACHE
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static void __ic_line_inv_no_alias(unsigned long, int);
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static void __ic_line_inv_2_alias(unsigned long, int);
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static void __ic_line_inv_4_alias(unsigned long, int);
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/* Holds the ptr to flush routine, dependign on size due to aliasing issues */
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static void (*___flush_icache_rtn) (unsigned long, int);
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#endif
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char *arc_cache_mumbojumbo(int cpu_id, char *buf, int len)
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{
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int n = 0;
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@ -171,30 +161,6 @@ void __cpuinit arc_cache_init(void)
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}
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#endif
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/*
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* if Cache way size is <= page size then no aliasing exhibited
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* otherwise ratio determines num of aliases.
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* e.g. 32K I$, 2 way set assoc, 8k pg size
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* way-sz = 32k/2 = 16k
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* way-pg-ratio = 16k/8k = 2, so 2 aliases possible
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* (meaning 1 line could be in 2 possible locations).
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*/
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way_pg_ratio = ic->sz / ARC_ICACHE_WAYS / PAGE_SIZE;
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switch (way_pg_ratio) {
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case 0:
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case 1:
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___flush_icache_rtn = __ic_line_inv_no_alias;
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break;
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case 2:
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___flush_icache_rtn = __ic_line_inv_2_alias;
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break;
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case 4:
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___flush_icache_rtn = __ic_line_inv_4_alias;
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break;
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default:
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panic("Unsupported I-Cache Sz\n");
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}
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#endif
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/* Enable/disable I-Cache */
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@ -391,75 +357,38 @@ static inline void __dc_line_op(unsigned long start, unsigned long sz,
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/*
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* I-Cache Aliasing in ARC700 VIPT caches
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*
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* For fetching code from I$, ARC700 uses vaddr (embedded in program code)
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* to "index" into SET of cache-line and paddr from MMU to match the TAG
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* in the WAYS of SET.
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* ARC VIPT I-cache uses vaddr to index into cache and paddr to match the tag.
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* The orig Cache Management Module "CDU" only required paddr to invalidate a
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* certain line since it sufficed as index in Non-Aliasing VIPT cache-geometry.
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* Infact for distinct V1,V2,P: all of {V1-P},{V2-P},{P-P} would end up fetching
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* the exact same line.
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*
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* However the CDU iterface (to flush/inv) lines from software, only takes
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* paddr (to have simpler hardware interface). For simpler cases, using paddr
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* alone suffices.
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* e.g. 2-way-set-assoc, 16K I$ (8k MMU pg sz, 32b cache line size):
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* way_sz = cache_sz / num_ways = 16k/2 = 8k
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* num_sets = way_sz / line_sz = 8k/32 = 256 => 8 bits
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* Ignoring the bottom 5 bits corresp to the off within a 32b cacheline,
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* bits req for calc set-index = bits 12:5 (0 based). Since this range fits
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* inside the bottom 13 bits of paddr, which are same for vaddr and paddr
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* (with 8k pg sz), paddr alone can be safely used by CDU to unambigously
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* locate a cache-line.
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*
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* However for a difft sized cache, say 32k I$, above math yields need
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* for 14 bits of vaddr to locate a cache line, which can't be provided by
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* paddr, since the bit 13 (0 based) might differ between the two.
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*
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* This lack of extra bits needed for correct line addressing, defines the
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* classical problem of Cache aliasing with VIPT architectures
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* num_aliases = 1 << extra_bits
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* e.g. 2-way-set-assoc, 32K I$ with 8k MMU pg sz => 2 aliases
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* 2-way-set-assoc, 64K I$ with 8k MMU pg sz => 4 aliases
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* 2-way-set-assoc, 16K I$ with 8k MMU pg sz => NO aliases
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* However for larger Caches (way-size > page-size) - i.e. in Aliasing config,
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* paddr alone could not be used to correctly index the cache.
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*
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* ------------------
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* MMU v1/v2 (Fixed Page Size 8k)
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* ------------------
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* The solution was to provide CDU with these additonal vaddr bits. These
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* would be bits [x:13], x would depend on cache-geom.
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* would be bits [x:13], x would depend on cache-geometry, 13 comes from
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* standard page size of 8k.
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* H/w folks chose [17:13] to be a future safe range, and moreso these 5 bits
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* of vaddr could easily be "stuffed" in the paddr as bits [4:0] since the
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* orig 5 bits of paddr were anyways ignored by CDU line ops, as they
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* represent the offset within cache-line. The adv of using this "clumsy"
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* interface for additional info was no new reg was needed in CDU.
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* interface for additional info was no new reg was needed in CDU programming
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* model.
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*
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* 17:13 represented the max num of bits passable, actual bits needed were
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* fewer, based on the num-of-aliases possible.
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* -for 2 alias possibility, only bit 13 needed (32K cache)
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* -for 4 alias possibility, bits 14:13 needed (64K cache)
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*
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* Since vaddr was not available for all instances of I$ flush req by core
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* kernel, the only safe way (non-optimal though) was to kill all possible
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* lines which could represent an alias (even if they didnt represent one
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* in execution).
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* e.g. for 64K I$, 4 aliases possible, so we did
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* flush start
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* flush start | 0x01
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* flush start | 0x2
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* flush start | 0x3
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*
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* The penalty was invoking the operation itself, since tag match is anyways
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* paddr based, a line which didn't represent an alias would not match the
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* paddr, hence wont be killed
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*
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* Note that aliasing concerns are independent of line-sz for a given cache
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* geometry (size + set_assoc) because the extra bits required by line-sz are
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* reduced from the set calc.
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* e.g. 2-way-set-assoc, 32K I$ with 8k MMU pg sz and using math above
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* 32b line-sz: 9 bits set-index-calc, 5 bits offset-in-line => 1 extra bit
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* 64b line-sz: 8 bits set-index-calc, 6 bits offset-in-line => 1 extra bit
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*
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* ------------------
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* MMU v3
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* ------------------
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* This ver of MMU supports var page sizes (1k-16k) - Linux will support
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* 8k (default), 16k and 4k.
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* This ver of MMU supports variable page sizes (1k-16k): although Linux will
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* only support 8k (default), 16k and 4k.
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* However from hardware perspective, smaller page sizes aggrevate aliasing
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* meaning more vaddr bits needed to disambiguate the cache-line-op ;
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* the existing scheme of piggybacking won't work for certain configurations.
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@ -468,105 +397,10 @@ static inline void __dc_line_op(unsigned long start, unsigned long sz,
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*/
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/***********************************************************
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* Machine specific helpers for per line I-Cache invalidate.
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* 3 routines to accpunt for 1, 2, 4 aliases possible
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* Machine specific helper for per line I-Cache invalidate.
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*/
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static void __ic_line_inv_no_alias(unsigned long start, int num_lines)
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{
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while (num_lines-- > 0) {
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#if (CONFIG_ARC_MMU_VER > 2)
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write_aux_reg(ARC_REG_IC_PTAG, start);
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#endif
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write_aux_reg(ARC_REG_IC_IVIL, start);
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start += ARC_ICACHE_LINE_LEN;
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}
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}
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static void __ic_line_inv_2_alias(unsigned long start, int num_lines)
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{
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while (num_lines-- > 0) {
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#if (CONFIG_ARC_MMU_VER > 2)
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/*
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* MMU v3, CDU prog model (for line ops) now uses a new IC_PTAG
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* reg to pass the "tag" bits and existing IVIL reg only looks
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* at bits relevant for "index" (details above)
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* Programming Notes:
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* -when writing tag to PTAG reg, bit chopping can be avoided,
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* CDU ignores non-tag bits.
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* -Ideally "index" must be computed from vaddr, but it is not
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* avail in these rtns. So to be safe, we kill the lines in all
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* possible indexes corresp to num of aliases possible for
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* given cache config.
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*/
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write_aux_reg(ARC_REG_IC_PTAG, start);
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write_aux_reg(ARC_REG_IC_IVIL,
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start & ~(0x1 << PAGE_SHIFT));
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write_aux_reg(ARC_REG_IC_IVIL, start | (0x1 << PAGE_SHIFT));
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#else
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write_aux_reg(ARC_REG_IC_IVIL, start);
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write_aux_reg(ARC_REG_IC_IVIL, start | 0x01);
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#endif
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start += ARC_ICACHE_LINE_LEN;
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}
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}
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static void __ic_line_inv_4_alias(unsigned long start, int num_lines)
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{
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while (num_lines-- > 0) {
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#if (CONFIG_ARC_MMU_VER > 2)
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write_aux_reg(ARC_REG_IC_PTAG, start);
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write_aux_reg(ARC_REG_IC_IVIL,
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start & ~(0x3 << PAGE_SHIFT));
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write_aux_reg(ARC_REG_IC_IVIL,
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start & ~(0x2 << PAGE_SHIFT));
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write_aux_reg(ARC_REG_IC_IVIL,
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start & ~(0x1 << PAGE_SHIFT));
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write_aux_reg(ARC_REG_IC_IVIL, start | (0x3 << PAGE_SHIFT));
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#else
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write_aux_reg(ARC_REG_IC_IVIL, start);
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write_aux_reg(ARC_REG_IC_IVIL, start | 0x01);
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write_aux_reg(ARC_REG_IC_IVIL, start | 0x02);
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write_aux_reg(ARC_REG_IC_IVIL, start | 0x03);
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#endif
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start += ARC_ICACHE_LINE_LEN;
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}
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}
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static void __ic_line_inv(unsigned long start, unsigned long sz)
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{
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unsigned long flags;
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int num_lines, slack;
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/*
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* Ensure we properly floor/ceil the non-line aligned/sized requests
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* and have @start - aligned to cache line, and integral @num_lines
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* However page sized flushes can be compile time optimised.
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* -@start will be cache-line aligned already (being page aligned)
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* -@sz will be integral multiple of line size (being page sized).
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*/
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if (!(__builtin_constant_p(sz) && sz == PAGE_SIZE)) {
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slack = start & ~ICACHE_LINE_MASK;
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sz += slack;
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start -= slack;
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}
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num_lines = DIV_ROUND_UP(sz, ARC_ICACHE_LINE_LEN);
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local_irq_save(flags);
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(*___flush_icache_rtn) (start, num_lines);
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local_irq_restore(flags);
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}
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/* Unlike routines above, having vaddr for flush op (along with paddr),
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* prevents the need to speculatively kill the lines in multiple sets
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* based on ratio of way_sz : pg_sz
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*/
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static void __ic_line_inv_vaddr(unsigned long phy_start,
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unsigned long vaddr, unsigned long sz)
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static void __ic_line_inv_vaddr(unsigned long phy_start, unsigned long vaddr,
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unsigned long sz)
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{
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unsigned long flags;
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int num_lines, slack;
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@ -595,7 +429,7 @@ static void __ic_line_inv_vaddr(unsigned long phy_start,
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write_aux_reg(ARC_REG_IC_IVIL, vaddr);
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vaddr += ARC_ICACHE_LINE_LEN;
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#else
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/* this paddr contains vaddrs bits as needed */
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/* paddr contains stuffed vaddrs bits */
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write_aux_reg(ARC_REG_IC_IVIL, addr);
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#endif
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addr += ARC_ICACHE_LINE_LEN;
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@ -605,7 +439,6 @@ static void __ic_line_inv_vaddr(unsigned long phy_start,
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#else
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#define __ic_line_inv(start, sz)
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#define __ic_line_inv_vaddr(pstart, vstart, sz)
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#endif /* CONFIG_ARC_HAS_ICACHE */
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