ARM OMAP2+ GPMC: fix WAITMONITORINGTIME divider bug
The WAITMONITORINGTIME is expressed as a number of GPMC_CLK clock cycles, even though the access is defined as asynchronous, and no GPMC_CLK clock is provided to the external device. Still, GPMCFCLKDIVIDER is used as a divider for the GPMC clock, so it must be programmed to define the correct WAITMONITORINGTIME delay. This patch correctly computes WAITMONITORINGTIME in GPMC_CLK cycles instead of GPMC_FCLK cycles, both during programming (gpmc_cs_set_timings) and during retrieval (gpmc_cs_show_timings). Signed-off-by: Robert ABEL <rabel@cit-ec.uni-bielefeld.de> Acked-by: Tony Lindgren <tony@atomide.com> Signed-off-by: Roger Quadros <rogerq@ti.com>
This commit is contained in:
Robert ABEL
Roger Quadros
Родитель
2e67690137
Коммит
7f2e8c58ae
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@ -179,6 +179,11 @@
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*/
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#define GPMC_NR_IRQ 2
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enum gpmc_clk_domain {
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GPMC_CD_FCLK,
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GPMC_CD_CLK
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};
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struct gpmc_cs_data {
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const char *name;
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@ -277,16 +282,55 @@ static unsigned long gpmc_get_fclk_period(void)
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return rate;
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}
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static unsigned int gpmc_ns_to_ticks(unsigned int time_ns)
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/**
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* gpmc_get_clk_period - get period of selected clock domain in ps
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* @cs Chip Select Region.
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* @cd Clock Domain.
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*
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* GPMC_CS_CONFIG1 GPMCFCLKDIVIDER for cs has to be setup
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* prior to calling this function with GPMC_CD_CLK.
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*/
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static unsigned long gpmc_get_clk_period(int cs, enum gpmc_clk_domain cd)
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{
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unsigned long tick_ps = gpmc_get_fclk_period();
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u32 l;
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int div;
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switch (cd) {
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case GPMC_CD_CLK:
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/* get current clk divider */
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l = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG1);
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div = (l & 0x03) + 1;
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/* get GPMC_CLK period */
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tick_ps *= div;
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break;
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case GPMC_CD_FCLK:
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/* FALL-THROUGH */
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default:
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break;
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}
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return tick_ps;
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}
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static unsigned int gpmc_ns_to_clk_ticks(unsigned int time_ns, int cs,
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enum gpmc_clk_domain cd)
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{
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unsigned long tick_ps;
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/* Calculate in picosecs to yield more exact results */
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tick_ps = gpmc_get_fclk_period();
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tick_ps = gpmc_get_clk_period(cs, cd);
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return (time_ns * 1000 + tick_ps - 1) / tick_ps;
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}
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static unsigned int gpmc_ns_to_ticks(unsigned int time_ns)
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{
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return gpmc_ns_to_clk_ticks(time_ns, /* any CS */ 0, GPMC_CD_FCLK);
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}
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static unsigned int gpmc_ps_to_ticks(unsigned int time_ps)
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{
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unsigned long tick_ps;
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@ -297,9 +341,15 @@ static unsigned int gpmc_ps_to_ticks(unsigned int time_ps)
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return (time_ps + tick_ps - 1) / tick_ps;
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}
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unsigned int gpmc_clk_ticks_to_ns(unsigned ticks, int cs,
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enum gpmc_clk_domain cd)
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{
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return ticks * gpmc_get_clk_period(cs, cd) / 1000;
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}
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unsigned int gpmc_ticks_to_ns(unsigned int ticks)
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{
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return ticks * gpmc_get_fclk_period() / 1000;
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return gpmc_clk_ticks_to_ns(ticks, /* any CS */ 0, GPMC_CD_FCLK);
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}
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static unsigned int gpmc_ticks_to_ps(unsigned int ticks)
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@ -355,18 +405,24 @@ static void gpmc_cs_bool_timings(int cs, const struct gpmc_bool_timings *p)
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* @st_bit: Start Bit
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* @end_bit: End Bit. Must be >= @st_bit.
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* @name: DTS node name, w/o "gpmc,"
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* @cd: Clock Domain of timing parameter.
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* @shift: Parameter value left shifts @shift, which is then printed instead of value.
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* @raw: Raw Format Option.
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* raw format: gpmc,name = <value>
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* tick format: gpmc,name = <value> /‍* x ns -- y ns; x ticks *‍/
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* Where x ns -- y ns result in the same tick value.
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* @noval: Parameter values equal to 0 are not printed.
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* @shift: Parameter value left shifts @shift, which is then printed instead of value.
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* @return: Specified timing parameter (after optional @shift).
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*
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*/
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static int get_gpmc_timing_reg(int cs, int reg, int st_bit, int end_bit,
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bool raw, bool noval, int shift,
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const char *name)
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static int get_gpmc_timing_reg(
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/* timing specifiers */
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int cs, int reg, int st_bit, int end_bit,
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const char *name, const enum gpmc_clk_domain cd,
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/* value transform */
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int shift,
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/* format specifiers */
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bool raw, bool noval)
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{
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u32 l;
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int nr_bits;
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@ -386,8 +442,8 @@ static int get_gpmc_timing_reg(int cs, int reg, int st_bit, int end_bit,
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unsigned int time_ns_min = 0;
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if (l)
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time_ns_min = gpmc_ticks_to_ns(l - 1) + 1;
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time_ns = gpmc_ticks_to_ns(l);
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time_ns_min = gpmc_clk_ticks_to_ns(l - 1, cs, cd) + 1;
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time_ns = gpmc_clk_ticks_to_ns(l, cs, cd);
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pr_info("gpmc,%s = <%u> /* %u ns - %u ns; %i ticks */\n",
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name, time_ns, time_ns_min, time_ns, l);
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} else {
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@ -402,13 +458,15 @@ static int get_gpmc_timing_reg(int cs, int reg, int st_bit, int end_bit,
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pr_info("cs%i %s: 0x%08x\n", cs, #config, \
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gpmc_cs_read_reg(cs, config))
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#define GPMC_GET_RAW(reg, st, end, field) \
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get_gpmc_timing_reg(cs, (reg), (st), (end), 1, 0, 0, field)
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get_gpmc_timing_reg(cs, (reg), (st), (end), field, GPMC_CD_FCLK, 0, 1, 0)
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#define GPMC_GET_RAW_BOOL(reg, st, end, field) \
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get_gpmc_timing_reg(cs, (reg), (st), (end), 1, 1, 0, field)
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get_gpmc_timing_reg(cs, (reg), (st), (end), field, GPMC_CD_FCLK, 0, 1, 1)
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#define GPMC_GET_RAW_SHIFT(reg, st, end, shift, field) \
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get_gpmc_timing_reg(cs, (reg), (st), (end), 1, 1, (shift), field)
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get_gpmc_timing_reg(cs, (reg), (st), (end), field, GPMC_CD_FCLK, (shift), 1, 1)
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#define GPMC_GET_TICKS(reg, st, end, field) \
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get_gpmc_timing_reg(cs, (reg), (st), (end), 0, 0, 0, field)
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get_gpmc_timing_reg(cs, (reg), (st), (end), field, GPMC_CD_FCLK, 0, 0, 0)
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#define GPMC_GET_TICKS_CD(reg, st, end, field, cd) \
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get_gpmc_timing_reg(cs, (reg), (st), (end), field, (cd), 0, 0, 0)
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static void gpmc_show_regs(int cs, const char *desc)
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{
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@ -476,7 +534,7 @@ static void gpmc_cs_show_timings(int cs, const char *desc)
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GPMC_GET_TICKS(GPMC_CS_CONFIG6, 0, 3, "bus-turnaround-ns");
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GPMC_GET_TICKS(GPMC_CS_CONFIG6, 8, 11, "cycle2cycle-delay-ns");
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GPMC_GET_TICKS(GPMC_CS_CONFIG1, 18, 19, "wait-monitoring-ns");
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GPMC_GET_TICKS_CD(GPMC_CS_CONFIG1, 18, 19, "wait-monitoring-ns", GPMC_CD_CLK);
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GPMC_GET_TICKS(GPMC_CS_CONFIG1, 25, 26, "clk-activation-ns");
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GPMC_GET_TICKS(GPMC_CS_CONFIG6, 16, 19, "wr-data-mux-bus-ns");
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@ -488,8 +546,22 @@ static inline void gpmc_cs_show_timings(int cs, const char *desc)
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}
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#endif
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/**
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* set_gpmc_timing_reg - set a single timing parameter for Chip Select Region.
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* Caller is expected to have initialized CONFIG1 GPMCFCLKDIVIDER
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* prior to calling this function with @cd equal to GPMC_CD_CLK.
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*
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* @cs: Chip Select Region.
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* @reg: GPMC_CS_CONFIGn register offset.
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* @st_bit: Start Bit
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* @end_bit: End Bit. Must be >= @st_bit.
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* @time: Timing parameter in ns.
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* @cd: Timing parameter clock domain.
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* @name: Timing parameter name.
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* @return: 0 on success, -1 on error.
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*/
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static int set_gpmc_timing_reg(int cs, int reg, int st_bit, int end_bit,
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int time, const char *name)
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int time, enum gpmc_clk_domain cd, const char *name)
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{
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u32 l;
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int ticks, mask, nr_bits;
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@ -497,12 +569,12 @@ static int set_gpmc_timing_reg(int cs, int reg, int st_bit, int end_bit,
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if (time == 0)
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ticks = 0;
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else
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ticks = gpmc_ns_to_ticks(time);
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ticks = gpmc_ns_to_clk_ticks(time, cs, cd);
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nr_bits = end_bit - st_bit + 1;
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mask = (1 << nr_bits) - 1;
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if (ticks > mask) {
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pr_err("%s: GPMC error! CS%d: %s: %d ns, %d ticks > %d\n",
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pr_err("%s: GPMC CS%d: %s %d ns, %d ticks > %d ticks\n",
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__func__, cs, name, time, ticks, mask);
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return -1;
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@ -512,7 +584,7 @@ static int set_gpmc_timing_reg(int cs, int reg, int st_bit, int end_bit,
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#ifdef DEBUG
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pr_info(
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"GPMC CS%d: %-17s: %3d ticks, %3lu ns (was %3i ticks) %3d ns\n",
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cs, name, ticks, gpmc_get_fclk_period() * ticks / 1000,
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cs, name, ticks, gpmc_get_clk_period(cs, cd) * ticks / 1000,
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(l >> st_bit) & mask, time);
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#endif
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l &= ~(mask << st_bit);
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@ -522,11 +594,14 @@ static int set_gpmc_timing_reg(int cs, int reg, int st_bit, int end_bit,
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return 0;
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}
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#define GPMC_SET_ONE(reg, st, end, field) \
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if (set_gpmc_timing_reg(cs, (reg), (st), (end), \
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t->field, #field) < 0) \
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#define GPMC_SET_ONE_CD(reg, st, end, field, cd) \
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if (set_gpmc_timing_reg(cs, (reg), (st), (end), \
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t->field, (cd), #field) < 0) \
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return -1
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#define GPMC_SET_ONE(reg, st, end, field) \
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GPMC_SET_ONE_CD(reg, st, end, field, GPMC_CD_FCLK)
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/**
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* gpmc_calc_waitmonitoring_divider - calculate proper GPMCFCLKDIVIDER based on WAITMONITORINGTIME
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* WAITMONITORINGTIME will be _at least_ as long as desired, i.e.
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@ -644,22 +719,23 @@ int gpmc_cs_set_timings(int cs, const struct gpmc_timings *t,
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GPMC_SET_ONE(GPMC_CS_CONFIG6, 0, 3, bus_turnaround);
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GPMC_SET_ONE(GPMC_CS_CONFIG6, 8, 11, cycle2cycle_delay);
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GPMC_SET_ONE(GPMC_CS_CONFIG1, 18, 19, wait_monitoring);
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GPMC_SET_ONE(GPMC_CS_CONFIG1, 25, 26, clk_activation);
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if (gpmc_capability & GPMC_HAS_WR_DATA_MUX_BUS)
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GPMC_SET_ONE(GPMC_CS_CONFIG6, 16, 19, wr_data_mux_bus);
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if (gpmc_capability & GPMC_HAS_WR_ACCESS)
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GPMC_SET_ONE(GPMC_CS_CONFIG6, 24, 28, wr_access);
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l = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG1);
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l &= ~0x03;
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l |= (div - 1);
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gpmc_cs_write_reg(cs, GPMC_CS_CONFIG1, l);
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GPMC_SET_ONE_CD(GPMC_CS_CONFIG1, 18, 19, wait_monitoring, GPMC_CD_CLK);
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GPMC_SET_ONE(GPMC_CS_CONFIG1, 25, 26, clk_activation);
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#ifdef DEBUG
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pr_info("GPMC CS%d CLK period is %lu ns (div %d)\n",
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cs, (div * gpmc_get_fclk_period()) / 1000, div);
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#endif
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l &= ~0x03;
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l |= (div - 1);
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gpmc_cs_write_reg(cs, GPMC_CS_CONFIG1, l);
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gpmc_cs_bool_timings(cs, &t->bool_timings);
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gpmc_cs_show_timings(cs, "after gpmc_cs_set_timings");
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