RDMA/irdma: Align AE id codes to correct flush code and event
A number of asynchronous event (AE) ids were not aligned to the
correct flush_code and event_type. Fix these up so that the
correct IBV error and event codes are returned to application.
Also, add handling for new AE ids like IRDMA_AE_INVALID_REQUEST to
return the correct WC error code.
Fixes: 44d9e52977
("RDMA/irdma: Implement device initialization definitions")
Signed-off-by: Sindhu-Devale <sindhu.devale@intel.com>
Signed-off-by: Shiraz Saleem <shiraz.saleem@intel.com>
Link: https://lore.kernel.org/r/20220907191324.1173-2-shiraz.saleem@intel.com
Signed-off-by: Leon Romanovsky <leon@kernel.org>
This commit is contained in:
Родитель
e866025b3b
Коммит
7f51a961f8
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@ -314,6 +314,7 @@ enum irdma_cqp_op_type {
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#define IRDMA_AE_IB_REMOTE_ACCESS_ERROR 0x020d
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#define IRDMA_AE_IB_REMOTE_OP_ERROR 0x020e
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#define IRDMA_AE_WQE_LSMM_TOO_LONG 0x0220
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#define IRDMA_AE_INVALID_REQUEST 0x0223
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#define IRDMA_AE_DDP_INVALID_MSN_GAP_IN_MSN 0x0301
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#define IRDMA_AE_DDP_UBE_DDP_MESSAGE_TOO_LONG_FOR_AVAILABLE_BUFFER 0x0303
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#define IRDMA_AE_DDP_UBE_INVALID_DDP_VERSION 0x0304
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@ -138,59 +138,68 @@ static void irdma_set_flush_fields(struct irdma_sc_qp *qp,
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qp->event_type = IRDMA_QP_EVENT_CATASTROPHIC;
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switch (info->ae_id) {
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case IRDMA_AE_AMP_UNALLOCATED_STAG:
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case IRDMA_AE_AMP_BOUNDS_VIOLATION:
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case IRDMA_AE_AMP_INVALID_STAG:
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qp->event_type = IRDMA_QP_EVENT_ACCESS_ERR;
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fallthrough;
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case IRDMA_AE_AMP_RIGHTS_VIOLATION:
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case IRDMA_AE_AMP_UNALLOCATED_STAG:
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case IRDMA_AE_AMP_BAD_PD:
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case IRDMA_AE_UDA_XMIT_BAD_PD:
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qp->flush_code = FLUSH_PROT_ERR;
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break;
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case IRDMA_AE_AMP_BAD_QP:
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case IRDMA_AE_WQE_UNEXPECTED_OPCODE:
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qp->flush_code = FLUSH_LOC_QP_OP_ERR;
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break;
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case IRDMA_AE_AMP_BAD_STAG_KEY:
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case IRDMA_AE_AMP_BAD_STAG_INDEX:
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case IRDMA_AE_AMP_TO_WRAP:
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case IRDMA_AE_AMP_RIGHTS_VIOLATION:
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case IRDMA_AE_AMP_INVALIDATE_NO_REMOTE_ACCESS_RIGHTS:
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case IRDMA_AE_PRIV_OPERATION_DENIED:
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case IRDMA_AE_IB_INVALID_REQUEST:
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qp->flush_code = FLUSH_PROT_ERR;
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qp->event_type = IRDMA_QP_EVENT_ACCESS_ERR;
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break;
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case IRDMA_AE_UDA_XMIT_BAD_PD:
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case IRDMA_AE_WQE_UNEXPECTED_OPCODE:
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qp->flush_code = FLUSH_LOC_QP_OP_ERR;
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qp->event_type = IRDMA_QP_EVENT_CATASTROPHIC;
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break;
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case IRDMA_AE_UDA_XMIT_DGRAM_TOO_LONG:
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case IRDMA_AE_UDA_XMIT_DGRAM_TOO_SHORT:
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case IRDMA_AE_UDA_L4LEN_INVALID:
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case IRDMA_AE_DDP_UBE_INVALID_MO:
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case IRDMA_AE_DDP_UBE_DDP_MESSAGE_TOO_LONG_FOR_AVAILABLE_BUFFER:
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qp->flush_code = FLUSH_LOC_LEN_ERR;
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qp->event_type = IRDMA_QP_EVENT_CATASTROPHIC;
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break;
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case IRDMA_AE_AMP_INVALIDATE_NO_REMOTE_ACCESS_RIGHTS:
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case IRDMA_AE_IB_REMOTE_ACCESS_ERROR:
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qp->flush_code = FLUSH_REM_ACCESS_ERR;
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qp->event_type = IRDMA_QP_EVENT_ACCESS_ERR;
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break;
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case IRDMA_AE_LLP_SEGMENT_TOO_SMALL:
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case IRDMA_AE_DDP_UBE_DDP_MESSAGE_TOO_LONG_FOR_AVAILABLE_BUFFER:
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case IRDMA_AE_UDA_XMIT_DGRAM_TOO_LONG:
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case IRDMA_AE_UDA_XMIT_DGRAM_TOO_SHORT:
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case IRDMA_AE_UDA_L4LEN_INVALID:
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case IRDMA_AE_LLP_RECEIVED_MPA_CRC_ERROR:
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case IRDMA_AE_ROCE_RSP_LENGTH_ERROR:
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qp->flush_code = FLUSH_LOC_LEN_ERR;
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case IRDMA_AE_IB_REMOTE_OP_ERROR:
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qp->flush_code = FLUSH_REM_OP_ERR;
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qp->event_type = IRDMA_QP_EVENT_CATASTROPHIC;
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break;
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case IRDMA_AE_LCE_QP_CATASTROPHIC:
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qp->flush_code = FLUSH_FATAL_ERR;
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qp->event_type = IRDMA_QP_EVENT_CATASTROPHIC;
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break;
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case IRDMA_AE_DDP_UBE_INVALID_MO:
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case IRDMA_AE_IB_RREQ_AND_Q1_FULL:
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case IRDMA_AE_LLP_RECEIVED_MPA_CRC_ERROR:
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qp->flush_code = FLUSH_GENERAL_ERR;
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break;
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case IRDMA_AE_LLP_TOO_MANY_RETRIES:
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qp->flush_code = FLUSH_RETRY_EXC_ERR;
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qp->event_type = IRDMA_QP_EVENT_CATASTROPHIC;
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break;
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case IRDMA_AE_AMP_MWBIND_INVALID_RIGHTS:
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case IRDMA_AE_AMP_MWBIND_BIND_DISABLED:
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case IRDMA_AE_AMP_MWBIND_INVALID_BOUNDS:
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qp->flush_code = FLUSH_MW_BIND_ERR;
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qp->event_type = IRDMA_QP_EVENT_ACCESS_ERR;
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break;
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case IRDMA_AE_IB_REMOTE_OP_ERROR:
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qp->flush_code = FLUSH_REM_OP_ERR;
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case IRDMA_AE_IB_INVALID_REQUEST:
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qp->flush_code = FLUSH_REM_INV_REQ_ERR;
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qp->event_type = IRDMA_QP_EVENT_REQ_ERR;
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break;
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default:
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qp->flush_code = FLUSH_FATAL_ERR;
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qp->flush_code = FLUSH_GENERAL_ERR;
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qp->event_type = IRDMA_QP_EVENT_CATASTROPHIC;
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break;
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}
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}
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@ -98,6 +98,7 @@ enum irdma_term_mpa_errors {
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enum irdma_qp_event_type {
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IRDMA_QP_EVENT_CATASTROPHIC,
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IRDMA_QP_EVENT_ACCESS_ERR,
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IRDMA_QP_EVENT_REQ_ERR,
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};
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enum irdma_hw_stats_index_32b {
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@ -103,6 +103,7 @@ enum irdma_flush_opcode {
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FLUSH_FATAL_ERR,
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FLUSH_RETRY_EXC_ERR,
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FLUSH_MW_BIND_ERR,
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FLUSH_REM_INV_REQ_ERR,
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};
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enum irdma_cmpl_status {
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@ -2476,6 +2476,9 @@ void irdma_ib_qp_event(struct irdma_qp *iwqp, enum irdma_qp_event_type event)
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case IRDMA_QP_EVENT_ACCESS_ERR:
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ibevent.event = IB_EVENT_QP_ACCESS_ERR;
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break;
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case IRDMA_QP_EVENT_REQ_ERR:
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ibevent.event = IB_EVENT_QP_REQ_ERR;
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break;
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}
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ibevent.device = iwqp->ibqp.device;
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ibevent.element.qp = &iwqp->ibqp;
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@ -3308,6 +3308,8 @@ static enum ib_wc_status irdma_flush_err_to_ib_wc_status(enum irdma_flush_opcode
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return IB_WC_RETRY_EXC_ERR;
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case FLUSH_MW_BIND_ERR:
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return IB_WC_MW_BIND_ERR;
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case FLUSH_REM_INV_REQ_ERR:
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return IB_WC_REM_INV_REQ_ERR;
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case FLUSH_FATAL_ERR:
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default:
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return IB_WC_FATAL_ERR;
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