cxl/mem: Enumerate port targets before adding endpoints
The port scanning algorithm in devm_cxl_enumerate_ports() walks up the topology and adds cxl_port objects starting from the root down to the endpoint. When those ports are initially created they know all their dports, but they do not know the downstream cxl_port instance that represents the next descendant in the topology. Rework create_endpoint() into devm_cxl_add_endpoint() that enumerates the downstream cxl_port topology into each port's 'struct cxl_ep' record for each endpoint it that the port is an ancestor. Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> Link: https://lore.kernel.org/r/20220624041950.559155-7-dan.j.williams@intel.com Signed-off-by: Dan Williams <dan.j.williams@intel.com>
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@ -1087,6 +1087,47 @@ static struct cxl_ep *cxl_ep_load(struct cxl_port *port,
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return xa_load(&port->endpoints, (unsigned long)&cxlmd->dev);
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}
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int devm_cxl_add_endpoint(struct cxl_memdev *cxlmd,
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struct cxl_dport *parent_dport)
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{
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struct cxl_port *parent_port = parent_dport->port;
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struct cxl_dev_state *cxlds = cxlmd->cxlds;
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struct cxl_port *endpoint, *iter, *down;
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int rc;
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/*
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* Now that the path to the root is established record all the
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* intervening ports in the chain.
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*/
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for (iter = parent_port, down = NULL; !is_cxl_root(iter);
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down = iter, iter = to_cxl_port(iter->dev.parent)) {
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struct cxl_ep *ep;
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ep = cxl_ep_load(iter, cxlmd);
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ep->next = down;
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}
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endpoint = devm_cxl_add_port(&parent_port->dev, &cxlmd->dev,
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cxlds->component_reg_phys, parent_dport);
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if (IS_ERR(endpoint))
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return PTR_ERR(endpoint);
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dev_dbg(&cxlmd->dev, "add: %s\n", dev_name(&endpoint->dev));
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rc = cxl_endpoint_autoremove(cxlmd, endpoint);
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if (rc)
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return rc;
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if (!endpoint->dev.driver) {
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dev_err(&cxlmd->dev, "%s failed probe\n",
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dev_name(&endpoint->dev));
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return -ENXIO;
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}
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return 0;
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}
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EXPORT_SYMBOL_NS_GPL(devm_cxl_add_endpoint, CXL);
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static void cxl_detach_ep(void *data)
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{
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struct cxl_memdev *cxlmd = data;
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@ -385,10 +385,13 @@ struct cxl_dport {
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* struct cxl_ep - track an endpoint's interest in a port
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* @ep: device that hosts a generic CXL endpoint (expander or accelerator)
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* @dport: which dport routes to this endpoint on @port
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* @next: cxl switch port across the link attached to @dport NULL if
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* attached to an endpoint
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*/
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struct cxl_ep {
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struct device *ep;
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struct cxl_dport *dport;
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struct cxl_port *next;
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};
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/*
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@ -411,6 +414,8 @@ struct pci_bus *cxl_port_to_pci_bus(struct cxl_port *port);
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struct cxl_port *devm_cxl_add_port(struct device *host, struct device *uport,
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resource_size_t component_reg_phys,
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struct cxl_dport *parent_dport);
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int devm_cxl_add_endpoint(struct cxl_memdev *cxlmd,
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struct cxl_dport *parent_dport);
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struct cxl_port *find_cxl_root(struct device *dev);
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int devm_cxl_enumerate_ports(struct cxl_memdev *cxlmd);
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int cxl_bus_rescan(void);
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@ -25,34 +25,6 @@
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* in higher level operations.
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*/
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static int create_endpoint(struct cxl_memdev *cxlmd,
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struct cxl_dport *parent_dport)
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{
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struct cxl_port *parent_port = parent_dport->port;
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struct cxl_dev_state *cxlds = cxlmd->cxlds;
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struct cxl_port *endpoint;
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int rc;
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endpoint = devm_cxl_add_port(&parent_port->dev, &cxlmd->dev,
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cxlds->component_reg_phys, parent_dport);
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if (IS_ERR(endpoint))
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return PTR_ERR(endpoint);
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dev_dbg(&cxlmd->dev, "add: %s\n", dev_name(&endpoint->dev));
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rc = cxl_endpoint_autoremove(cxlmd, endpoint);
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if (rc)
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return rc;
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if (!endpoint->dev.driver) {
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dev_err(&cxlmd->dev, "%s failed probe\n",
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dev_name(&endpoint->dev));
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return -ENXIO;
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}
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return 0;
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}
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static void enable_suspend(void *data)
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{
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cxl_mem_active_dec();
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@ -116,7 +88,7 @@ static int cxl_mem_probe(struct device *dev)
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goto unlock;
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}
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rc = create_endpoint(cxlmd, dport);
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rc = devm_cxl_add_endpoint(cxlmd, dport);
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unlock:
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device_unlock(&parent_port->dev);
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put_device(&parent_port->dev);
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