Merge branch 'topic/pcm-nonatomic' into for-next
This is a merge for exending PCM ops to be non-atomic.
This commit is contained in:
Takashi Iwai
Коммит
7fd4394dfe
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@ -4,11 +4,13 @@ Specifying interrupt information for devices
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|||
1) Interrupt client nodes
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||||
-------------------------
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||||
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||||
Nodes that describe devices which generate interrupts must contain an either an
|
||||
"interrupts" property or an "interrupts-extended" property. These properties
|
||||
contain a list of interrupt specifiers, one per output interrupt. The format of
|
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the interrupt specifier is determined by the interrupt controller to which the
|
||||
interrupts are routed; see section 2 below for details.
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||||
Nodes that describe devices which generate interrupts must contain an
|
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"interrupts" property, an "interrupts-extended" property, or both. If both are
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present, the latter should take precedence; the former may be provided simply
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for compatibility with software that does not recognize the latter. These
|
||||
properties contain a list of interrupt specifiers, one per output interrupt. The
|
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format of the interrupt specifier is determined by the interrupt controller to
|
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which the interrupts are routed; see section 2 below for details.
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Example:
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interrupt-parent = <&intc1>;
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|
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@ -2,6 +2,10 @@
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|||
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Required properties:
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- compatible: should contain "snps,dw-pcie" to identify the core.
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- reg: Should contain the configuration address space.
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- reg-names: Must be "config" for the PCIe configuration space.
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(The old way of getting the configuration address space from "ranges"
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is deprecated and should be avoided.)
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- #address-cells: set to <3>
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- #size-cells: set to <2>
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- device_type: set to "pci"
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|
|
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|
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@ -0,0 +1,59 @@
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TI PCI Controllers
|
||||
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PCIe Designware Controller
|
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- compatible: Should be "ti,dra7-pcie""
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- reg : Two register ranges as listed in the reg-names property
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- reg-names : The first entry must be "ti-conf" for the TI specific registers
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The second entry must be "rc-dbics" for the designware pcie
|
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registers
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The third entry must be "config" for the PCIe configuration space
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- phys : list of PHY specifiers (used by generic PHY framework)
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- phy-names : must be "pcie-phy0", "pcie-phy1", "pcie-phyN".. based on the
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number of PHYs as specified in *phys* property.
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- ti,hwmods : Name of the hwmod associated to the pcie, "pcie<X>",
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where <X> is the instance number of the pcie from the HW spec.
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- interrupts : Two interrupt entries must be specified. The first one is for
|
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main interrupt line and the second for MSI interrupt line.
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- #address-cells,
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#size-cells,
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#interrupt-cells,
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device_type,
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ranges,
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num-lanes,
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interrupt-map-mask,
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interrupt-map : as specified in ../designware-pcie.txt
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Example:
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axi {
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compatible = "simple-bus";
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#size-cells = <1>;
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#address-cells = <1>;
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ranges = <0x51000000 0x51000000 0x3000
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0x0 0x20000000 0x10000000>;
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pcie@51000000 {
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compatible = "ti,dra7-pcie";
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reg = <0x51000000 0x2000>, <0x51002000 0x14c>, <0x1000 0x2000>;
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reg-names = "rc_dbics", "ti_conf", "config";
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interrupts = <0 232 0x4>, <0 233 0x4>;
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#address-cells = <3>;
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#size-cells = <2>;
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device_type = "pci";
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ranges = <0x81000000 0 0 0x03000 0 0x00010000
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0x82000000 0 0x20013000 0x13000 0 0xffed000>;
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#interrupt-cells = <1>;
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num-lanes = <1>;
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ti,hwmods = "pcie1";
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phys = <&pcie1_phy>;
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phy-names = "pcie-phy0";
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interrupt-map-mask = <0 0 0 7>;
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interrupt-map = <0 0 0 1 &pcie_intc 1>,
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||||
<0 0 0 2 &pcie_intc 2>,
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<0 0 0 3 &pcie_intc 3>,
|
||||
<0 0 0 4 &pcie_intc 4>;
|
||||
pcie_intc: interrupt-controller {
|
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interrupt-controller;
|
||||
#address-cells = <0>;
|
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#interrupt-cells = <1>;
|
||||
};
|
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};
|
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};
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|
|
@ -35,7 +35,7 @@ invlpg instruction (or instructions _near_ it) show up high in
|
|||
profiles. If you believe that individual invalidations being
|
||||
called too often, you can lower the tunable:
|
||||
|
||||
/sys/debug/kernel/x86/tlb_single_page_flush_ceiling
|
||||
/sys/kernel/debug/x86/tlb_single_page_flush_ceiling
|
||||
|
||||
This will cause us to do the global flush for more cases.
|
||||
Lowering it to 0 will disable the use of the individual flushes.
|
||||
|
|
|
|||
41
MAINTAINERS
41
MAINTAINERS
|
|
@ -1277,6 +1277,7 @@ F: drivers/scsi/arm/
|
|||
ARM/Rockchip SoC support
|
||||
M: Heiko Stuebner <heiko@sntech.de>
|
||||
L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
|
||||
L: linux-rockchip@lists.infradead.org
|
||||
S: Maintained
|
||||
F: arch/arm/mach-rockchip/
|
||||
F: drivers/*/*rockchip*
|
||||
|
|
@ -1843,6 +1844,12 @@ S: Orphan
|
|||
F: Documentation/filesystems/befs.txt
|
||||
F: fs/befs/
|
||||
|
||||
BECKHOFF CX5020 ETHERCAT MASTER DRIVER
|
||||
M: Dariusz Marcinkiewicz <reksio@newterm.pl>
|
||||
L: netdev@vger.kernel.org
|
||||
S: Maintained
|
||||
F: drivers/net/ethernet/ec_bhf.c
|
||||
|
||||
BFS FILE SYSTEM
|
||||
M: "Tigran A. Aivazian" <tigran@aivazian.fsnet.co.uk>
|
||||
S: Maintained
|
||||
|
|
@ -2059,7 +2066,7 @@ S: Supported
|
|||
F: drivers/scsi/bnx2i/
|
||||
|
||||
BROADCOM KONA GPIO DRIVER
|
||||
M: Markus Mayer <markus.mayer@linaro.org>
|
||||
M: Ray Jui <rjui@broadcom.com>
|
||||
L: bcm-kernel-feedback-list@broadcom.com
|
||||
S: Supported
|
||||
F: drivers/gpio/gpio-bcm-kona.c
|
||||
|
|
@ -3115,6 +3122,17 @@ F: include/linux/host1x.h
|
|||
F: include/uapi/drm/tegra_drm.h
|
||||
F: Documentation/devicetree/bindings/gpu/nvidia,tegra20-host1x.txt
|
||||
|
||||
DRM DRIVERS FOR RENESAS
|
||||
M: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
|
||||
L: dri-devel@lists.freedesktop.org
|
||||
L: linux-sh@vger.kernel.org
|
||||
T: git git://people.freedesktop.org/~airlied/linux
|
||||
S: Supported
|
||||
F: drivers/gpu/drm/rcar-du/
|
||||
F: drivers/gpu/drm/shmobile/
|
||||
F: include/linux/platform_data/rcar-du.h
|
||||
F: include/linux/platform_data/shmob_drm.h
|
||||
|
||||
DSBR100 USB FM RADIO DRIVER
|
||||
M: Alexey Klimov <klimov.linux@gmail.com>
|
||||
L: linux-media@vger.kernel.org
|
||||
|
|
@ -4449,6 +4467,13 @@ F: include/linux/i2c-*.h
|
|||
F: include/uapi/linux/i2c.h
|
||||
F: include/uapi/linux/i2c-*.h
|
||||
|
||||
I2C ACPI SUPPORT
|
||||
M: Mika Westerberg <mika.westerberg@linux.intel.com>
|
||||
L: linux-i2c@vger.kernel.org
|
||||
L: linux-acpi@vger.kernel.org
|
||||
S: Maintained
|
||||
F: drivers/i2c/i2c-acpi.c
|
||||
|
||||
I2C-TAOS-EVM DRIVER
|
||||
M: Jean Delvare <jdelvare@suse.de>
|
||||
L: linux-i2c@vger.kernel.org
|
||||
|
|
@ -5975,6 +6000,12 @@ T: git git://linuxtv.org/media_tree.git
|
|||
S: Maintained
|
||||
F: drivers/media/radio/radio-mr800.c
|
||||
|
||||
MRF24J40 IEEE 802.15.4 RADIO DRIVER
|
||||
M: Alan Ott <alan@signal11.us>
|
||||
L: linux-wpan@vger.kernel.org
|
||||
S: Maintained
|
||||
F: drivers/net/ieee802154/mrf24j40.c
|
||||
|
||||
MSI LAPTOP SUPPORT
|
||||
M: "Lee, Chun-Yi" <jlee@suse.com>
|
||||
L: platform-driver-x86@vger.kernel.org
|
||||
|
|
@ -6861,6 +6892,14 @@ S: Supported
|
|||
F: Documentation/devicetree/bindings/pci/nvidia,tegra20-pcie.txt
|
||||
F: drivers/pci/host/pci-tegra.c
|
||||
|
||||
PCI DRIVER FOR TI DRA7XX
|
||||
M: Kishon Vijay Abraham I <kishon@ti.com>
|
||||
L: linux-omap@vger.kernel.org
|
||||
L: linux-pci@vger.kernel.org
|
||||
S: Supported
|
||||
F: Documentation/devicetree/bindings/pci/ti-pci.txt
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F: drivers/pci/host/pci-dra7xx.c
|
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|
||||
PCI DRIVER FOR RENESAS R-CAR
|
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M: Simon Horman <horms@verge.net.au>
|
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L: linux-pci@vger.kernel.org
|
||||
|
|
|
|||
2
Makefile
2
Makefile
|
|
@ -1,7 +1,7 @@
|
|||
VERSION = 3
|
||||
PATCHLEVEL = 17
|
||||
SUBLEVEL = 0
|
||||
EXTRAVERSION = -rc1
|
||||
EXTRAVERSION = -rc2
|
||||
NAME = Shuffling Zombie Juror
|
||||
|
||||
# *DOCUMENTATION*
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||||
|
|
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|
|
@ -134,6 +134,8 @@
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i2c@13860000 {
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pinctrl-0 = <&i2c0_bus>;
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pinctrl-names = "default";
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samsung,i2c-sda-delay = <100>;
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samsung,i2c-max-bus-freq = <400000>;
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status = "okay";
|
||||
|
||||
usb3503: usb3503@08 {
|
||||
|
|
@ -148,6 +150,10 @@
|
|||
|
||||
max77686: pmic@09 {
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compatible = "maxim,max77686";
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interrupt-parent = <&gpx3>;
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interrupts = <2 0>;
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pinctrl-names = "default";
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pinctrl-0 = <&max77686_irq>;
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reg = <0x09>;
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#clock-cells = <1>;
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|
|
@ -368,4 +374,11 @@
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samsung,pins = "gpx1-3";
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samsung,pin-pud = <0>;
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};
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max77686_irq: max77686-irq {
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samsung,pins = "gpx3-2";
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samsung,pin-function = <0>;
|
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samsung,pin-pud = <0>;
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samsung,pin-drv = <0>;
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};
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};
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|
|
|
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|
|
@ -731,7 +731,7 @@
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compatible = "fsl,imx53-vpu";
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reg = <0x63ff4000 0x1000>;
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interrupts = <9>;
|
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clocks = <&clks IMX5_CLK_VPU_GATE>,
|
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clocks = <&clks IMX5_CLK_VPU_REFERENCE_GATE>,
|
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<&clks IMX5_CLK_VPU_GATE>;
|
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clock-names = "per", "ahb";
|
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resets = <&src 1>;
|
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|
|
|
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|
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@ -119,7 +119,7 @@
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_enet>;
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phy-mode = "rgmii";
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phy-reset-gpios = <&gpio3 23 0>;
|
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phy-reset-gpios = <&gpio1 25 0>;
|
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phy-supply = <&vgen2_1v2_eth>;
|
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status = "okay";
|
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};
|
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|
|
@ -339,6 +339,7 @@
|
|||
MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0
|
||||
MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0
|
||||
MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0
|
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MX6QDL_PAD_ENET_CRS_DV__GPIO1_IO25 0x1b0b0
|
||||
MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8
|
||||
>;
|
||||
};
|
||||
|
|
|
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|
|
@ -78,7 +78,7 @@
|
|||
#define MX6SX_PAD_GPIO1_IO07__USDHC2_WP 0x0030 0x0378 0x0870 0x1 0x1
|
||||
#define MX6SX_PAD_GPIO1_IO07__ENET2_MDIO 0x0030 0x0378 0x0770 0x2 0x0
|
||||
#define MX6SX_PAD_GPIO1_IO07__AUDMUX_MCLK 0x0030 0x0378 0x0000 0x3 0x0
|
||||
#define MX6SX_PAD_GPIO1_IO07__UART1_CTS_B 0x0030 0x0378 0x082C 0x4 0x1
|
||||
#define MX6SX_PAD_GPIO1_IO07__UART1_CTS_B 0x0030 0x0378 0x0000 0x4 0x0
|
||||
#define MX6SX_PAD_GPIO1_IO07__GPIO1_IO_7 0x0030 0x0378 0x0000 0x5 0x0
|
||||
#define MX6SX_PAD_GPIO1_IO07__SRC_EARLY_RESET 0x0030 0x0378 0x0000 0x6 0x0
|
||||
#define MX6SX_PAD_GPIO1_IO07__DCIC2_OUT 0x0030 0x0378 0x0000 0x7 0x0
|
||||
|
|
@ -96,7 +96,7 @@
|
|||
#define MX6SX_PAD_GPIO1_IO09__WDOG2_WDOG_B 0x0038 0x0380 0x0000 0x1 0x0
|
||||
#define MX6SX_PAD_GPIO1_IO09__SDMA_EXT_EVENT_1 0x0038 0x0380 0x0820 0x2 0x0
|
||||
#define MX6SX_PAD_GPIO1_IO09__CCM_OUT0 0x0038 0x0380 0x0000 0x3 0x0
|
||||
#define MX6SX_PAD_GPIO1_IO09__UART2_CTS_B 0x0038 0x0380 0x0834 0x4 0x1
|
||||
#define MX6SX_PAD_GPIO1_IO09__UART2_CTS_B 0x0038 0x0380 0x0000 0x4 0x0
|
||||
#define MX6SX_PAD_GPIO1_IO09__GPIO1_IO_9 0x0038 0x0380 0x0000 0x5 0x0
|
||||
#define MX6SX_PAD_GPIO1_IO09__SRC_INT_BOOT 0x0038 0x0380 0x0000 0x6 0x0
|
||||
#define MX6SX_PAD_GPIO1_IO09__OBSERVE_MUX_OUT_4 0x0038 0x0380 0x0000 0x7 0x0
|
||||
|
|
@ -213,7 +213,7 @@
|
|||
#define MX6SX_PAD_CSI_DATA07__ESAI_TX3_RX2 0x0068 0x03B0 0x079C 0x1 0x1
|
||||
#define MX6SX_PAD_CSI_DATA07__I2C4_SDA 0x0068 0x03B0 0x07C4 0x2 0x2
|
||||
#define MX6SX_PAD_CSI_DATA07__KPP_ROW_7 0x0068 0x03B0 0x07DC 0x3 0x0
|
||||
#define MX6SX_PAD_CSI_DATA07__UART6_CTS_B 0x0068 0x03B0 0x0854 0x4 0x1
|
||||
#define MX6SX_PAD_CSI_DATA07__UART6_CTS_B 0x0068 0x03B0 0x0000 0x4 0x0
|
||||
#define MX6SX_PAD_CSI_DATA07__GPIO1_IO_21 0x0068 0x03B0 0x0000 0x5 0x0
|
||||
#define MX6SX_PAD_CSI_DATA07__WEIM_DATA_16 0x0068 0x03B0 0x0000 0x6 0x0
|
||||
#define MX6SX_PAD_CSI_DATA07__DCIC1_OUT 0x0068 0x03B0 0x0000 0x7 0x0
|
||||
|
|
@ -254,7 +254,7 @@
|
|||
#define MX6SX_PAD_CSI_VSYNC__CSI1_VSYNC 0x0078 0x03C0 0x0708 0x0 0x0
|
||||
#define MX6SX_PAD_CSI_VSYNC__ESAI_TX5_RX0 0x0078 0x03C0 0x07A4 0x1 0x1
|
||||
#define MX6SX_PAD_CSI_VSYNC__AUDMUX_AUD6_RXD 0x0078 0x03C0 0x0674 0x2 0x1
|
||||
#define MX6SX_PAD_CSI_VSYNC__UART4_CTS_B 0x0078 0x03C0 0x0844 0x3 0x3
|
||||
#define MX6SX_PAD_CSI_VSYNC__UART4_CTS_B 0x0078 0x03C0 0x0000 0x3 0x0
|
||||
#define MX6SX_PAD_CSI_VSYNC__MQS_RIGHT 0x0078 0x03C0 0x0000 0x4 0x0
|
||||
#define MX6SX_PAD_CSI_VSYNC__GPIO1_IO_25 0x0078 0x03C0 0x0000 0x5 0x0
|
||||
#define MX6SX_PAD_CSI_VSYNC__WEIM_DATA_24 0x0078 0x03C0 0x0000 0x6 0x0
|
||||
|
|
@ -352,7 +352,7 @@
|
|||
#define MX6SX_PAD_ENET2_TX_CLK__ENET2_TX_CLK 0x00A0 0x03E8 0x0000 0x0 0x0
|
||||
#define MX6SX_PAD_ENET2_TX_CLK__ENET2_REF_CLK2 0x00A0 0x03E8 0x076C 0x1 0x1
|
||||
#define MX6SX_PAD_ENET2_TX_CLK__I2C3_SDA 0x00A0 0x03E8 0x07BC 0x2 0x1
|
||||
#define MX6SX_PAD_ENET2_TX_CLK__UART1_CTS_B 0x00A0 0x03E8 0x082C 0x3 0x3
|
||||
#define MX6SX_PAD_ENET2_TX_CLK__UART1_CTS_B 0x00A0 0x03E8 0x0000 0x3 0x0
|
||||
#define MX6SX_PAD_ENET2_TX_CLK__MLB_CLK 0x00A0 0x03E8 0x07E8 0x4 0x1
|
||||
#define MX6SX_PAD_ENET2_TX_CLK__GPIO2_IO_9 0x00A0 0x03E8 0x0000 0x5 0x0
|
||||
#define MX6SX_PAD_ENET2_TX_CLK__USB_OTG2_PWR 0x00A0 0x03E8 0x0000 0x6 0x0
|
||||
|
|
@ -404,7 +404,7 @@
|
|||
#define MX6SX_PAD_KEY_COL4__SAI2_RX_BCLK 0x00B4 0x03FC 0x0808 0x7 0x0
|
||||
#define MX6SX_PAD_KEY_ROW0__KPP_ROW_0 0x00B8 0x0400 0x0000 0x0 0x0
|
||||
#define MX6SX_PAD_KEY_ROW0__USDHC3_WP 0x00B8 0x0400 0x0000 0x1 0x0
|
||||
#define MX6SX_PAD_KEY_ROW0__UART6_CTS_B 0x00B8 0x0400 0x0854 0x2 0x3
|
||||
#define MX6SX_PAD_KEY_ROW0__UART6_CTS_B 0x00B8 0x0400 0x0000 0x2 0x0
|
||||
#define MX6SX_PAD_KEY_ROW0__ECSPI1_MOSI 0x00B8 0x0400 0x0718 0x3 0x0
|
||||
#define MX6SX_PAD_KEY_ROW0__AUDMUX_AUD5_TXD 0x00B8 0x0400 0x0660 0x4 0x0
|
||||
#define MX6SX_PAD_KEY_ROW0__GPIO2_IO_15 0x00B8 0x0400 0x0000 0x5 0x0
|
||||
|
|
@ -423,7 +423,7 @@
|
|||
#define MX6SX_PAD_KEY_ROW1__M4_NMI 0x00BC 0x0404 0x0000 0x8 0x0
|
||||
#define MX6SX_PAD_KEY_ROW2__KPP_ROW_2 0x00C0 0x0408 0x0000 0x0 0x0
|
||||
#define MX6SX_PAD_KEY_ROW2__USDHC4_WP 0x00C0 0x0408 0x0878 0x1 0x1
|
||||
#define MX6SX_PAD_KEY_ROW2__UART5_CTS_B 0x00C0 0x0408 0x084C 0x2 0x3
|
||||
#define MX6SX_PAD_KEY_ROW2__UART5_CTS_B 0x00C0 0x0408 0x0000 0x2 0x0
|
||||
#define MX6SX_PAD_KEY_ROW2__CAN1_RX 0x00C0 0x0408 0x068C 0x3 0x1
|
||||
#define MX6SX_PAD_KEY_ROW2__CANFD_RX1 0x00C0 0x0408 0x0694 0x4 0x1
|
||||
#define MX6SX_PAD_KEY_ROW2__GPIO2_IO_17 0x00C0 0x0408 0x0000 0x5 0x0
|
||||
|
|
@ -815,7 +815,7 @@
|
|||
#define MX6SX_PAD_NAND_DATA05__RAWNAND_DATA05 0x0164 0x04AC 0x0000 0x0 0x0
|
||||
#define MX6SX_PAD_NAND_DATA05__USDHC2_DATA5 0x0164 0x04AC 0x0000 0x1 0x0
|
||||
#define MX6SX_PAD_NAND_DATA05__QSPI2_B_DQS 0x0164 0x04AC 0x0000 0x2 0x0
|
||||
#define MX6SX_PAD_NAND_DATA05__UART3_CTS_B 0x0164 0x04AC 0x083C 0x3 0x1
|
||||
#define MX6SX_PAD_NAND_DATA05__UART3_CTS_B 0x0164 0x04AC 0x0000 0x3 0x0
|
||||
#define MX6SX_PAD_NAND_DATA05__AUDMUX_AUD4_RXC 0x0164 0x04AC 0x064C 0x4 0x0
|
||||
#define MX6SX_PAD_NAND_DATA05__GPIO4_IO_9 0x0164 0x04AC 0x0000 0x5 0x0
|
||||
#define MX6SX_PAD_NAND_DATA05__WEIM_AD_5 0x0164 0x04AC 0x0000 0x6 0x0
|
||||
|
|
@ -957,7 +957,7 @@
|
|||
#define MX6SX_PAD_QSPI1A_SS1_B__SIM_M_HADDR_12 0x019C 0x04E4 0x0000 0x7 0x0
|
||||
#define MX6SX_PAD_QSPI1A_SS1_B__SDMA_DEBUG_PC_3 0x019C 0x04E4 0x0000 0x9 0x0
|
||||
#define MX6SX_PAD_QSPI1B_DATA0__QSPI1_B_DATA_0 0x01A0 0x04E8 0x0000 0x0 0x0
|
||||
#define MX6SX_PAD_QSPI1B_DATA0__UART3_CTS_B 0x01A0 0x04E8 0x083C 0x1 0x4
|
||||
#define MX6SX_PAD_QSPI1B_DATA0__UART3_CTS_B 0x01A0 0x04E8 0x0000 0x1 0x0
|
||||
#define MX6SX_PAD_QSPI1B_DATA0__ECSPI3_MOSI 0x01A0 0x04E8 0x0738 0x2 0x1
|
||||
#define MX6SX_PAD_QSPI1B_DATA0__ESAI_RX_FS 0x01A0 0x04E8 0x0778 0x3 0x2
|
||||
#define MX6SX_PAD_QSPI1B_DATA0__CSI1_DATA_22 0x01A0 0x04E8 0x06F4 0x4 0x1
|
||||
|
|
@ -1236,7 +1236,7 @@
|
|||
#define MX6SX_PAD_SD1_DATA2__AUDMUX_AUD5_TXFS 0x0230 0x0578 0x0670 0x1 0x1
|
||||
#define MX6SX_PAD_SD1_DATA2__PWM3_OUT 0x0230 0x0578 0x0000 0x2 0x0
|
||||
#define MX6SX_PAD_SD1_DATA2__GPT_COMPARE2 0x0230 0x0578 0x0000 0x3 0x0
|
||||
#define MX6SX_PAD_SD1_DATA2__UART2_CTS_B 0x0230 0x0578 0x0834 0x4 0x2
|
||||
#define MX6SX_PAD_SD1_DATA2__UART2_CTS_B 0x0230 0x0578 0x0000 0x4 0x0
|
||||
#define MX6SX_PAD_SD1_DATA2__GPIO6_IO_4 0x0230 0x0578 0x0000 0x5 0x0
|
||||
#define MX6SX_PAD_SD1_DATA2__ECSPI4_RDY 0x0230 0x0578 0x0000 0x6 0x0
|
||||
#define MX6SX_PAD_SD1_DATA2__CCM_OUT0 0x0230 0x0578 0x0000 0x7 0x0
|
||||
|
|
@ -1315,7 +1315,7 @@
|
|||
#define MX6SX_PAD_SD2_DATA3__VADC_CLAMP_CURRENT_3 0x024C 0x0594 0x0000 0x8 0x0
|
||||
#define MX6SX_PAD_SD2_DATA3__MMDC_DEBUG_31 0x024C 0x0594 0x0000 0x9 0x0
|
||||
#define MX6SX_PAD_SD3_CLK__USDHC3_CLK 0x0250 0x0598 0x0000 0x0 0x0
|
||||
#define MX6SX_PAD_SD3_CLK__UART4_CTS_B 0x0250 0x0598 0x0844 0x1 0x0
|
||||
#define MX6SX_PAD_SD3_CLK__UART4_CTS_B 0x0250 0x0598 0x0000 0x1 0x0
|
||||
#define MX6SX_PAD_SD3_CLK__ECSPI4_SCLK 0x0250 0x0598 0x0740 0x2 0x0
|
||||
#define MX6SX_PAD_SD3_CLK__AUDMUX_AUD6_RXFS 0x0250 0x0598 0x0680 0x3 0x0
|
||||
#define MX6SX_PAD_SD3_CLK__LCDIF2_VSYNC 0x0250 0x0598 0x0000 0x4 0x0
|
||||
|
|
@ -1409,7 +1409,7 @@
|
|||
#define MX6SX_PAD_SD3_DATA7__USDHC3_DATA7 0x0274 0x05BC 0x0000 0x0 0x0
|
||||
#define MX6SX_PAD_SD3_DATA7__CAN1_RX 0x0274 0x05BC 0x068C 0x1 0x0
|
||||
#define MX6SX_PAD_SD3_DATA7__CANFD_RX1 0x0274 0x05BC 0x0694 0x2 0x0
|
||||
#define MX6SX_PAD_SD3_DATA7__UART3_CTS_B 0x0274 0x05BC 0x083C 0x3 0x3
|
||||
#define MX6SX_PAD_SD3_DATA7__UART3_CTS_B 0x0274 0x05BC 0x0000 0x3 0x0
|
||||
#define MX6SX_PAD_SD3_DATA7__LCDIF2_DATA_5 0x0274 0x05BC 0x0000 0x4 0x0
|
||||
#define MX6SX_PAD_SD3_DATA7__GPIO7_IO_9 0x0274 0x05BC 0x0000 0x5 0x0
|
||||
#define MX6SX_PAD_SD3_DATA7__ENET1_1588_EVENT0_IN 0x0274 0x05BC 0x0000 0x6 0x0
|
||||
|
|
@ -1510,7 +1510,7 @@
|
|||
#define MX6SX_PAD_SD4_DATA6__SDMA_DEBUG_EVENT_CHANNEL_1 0x0298 0x05E0 0x0000 0x9 0x0
|
||||
#define MX6SX_PAD_SD4_DATA7__USDHC4_DATA7 0x029C 0x05E4 0x0000 0x0 0x0
|
||||
#define MX6SX_PAD_SD4_DATA7__RAWNAND_DATA08 0x029C 0x05E4 0x0000 0x1 0x0
|
||||
#define MX6SX_PAD_SD4_DATA7__UART5_CTS_B 0x029C 0x05E4 0x084C 0x2 0x1
|
||||
#define MX6SX_PAD_SD4_DATA7__UART5_CTS_B 0x029C 0x05E4 0x0000 0x2 0x0
|
||||
#define MX6SX_PAD_SD4_DATA7__ECSPI3_SS0 0x029C 0x05E4 0x073C 0x3 0x0
|
||||
#define MX6SX_PAD_SD4_DATA7__LCDIF2_DATA_15 0x029C 0x05E4 0x0000 0x4 0x0
|
||||
#define MX6SX_PAD_SD4_DATA7__GPIO6_IO_21 0x029C 0x05E4 0x0000 0x5 0x0
|
||||
|
|
|
|||
|
|
@ -275,11 +275,6 @@
|
|||
renesas,function = "msiof0";
|
||||
};
|
||||
|
||||
i2c6_pins: i2c6 {
|
||||
renesas,groups = "i2c6";
|
||||
renesas,function = "i2c6";
|
||||
};
|
||||
|
||||
usb0_pins: usb0 {
|
||||
renesas,groups = "usb0";
|
||||
renesas,function = "usb0";
|
||||
|
|
@ -420,8 +415,6 @@
|
|||
};
|
||||
|
||||
&i2c6 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&i2c6_pins>;
|
||||
status = "okay";
|
||||
clock-frequency = <100000>;
|
||||
|
||||
|
|
|
|||
|
|
@ -149,6 +149,8 @@
|
|||
&mmc0 { /* sdmmc */
|
||||
num-slots = <1>;
|
||||
status = "okay";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&sd0_clk>, <&sd0_cmd>, <&sd0_cd>, <&sd0_bus4>;
|
||||
vmmc-supply = <&vcc_sd0>;
|
||||
|
||||
slot@0 {
|
||||
|
|
|
|||
|
|
@ -179,6 +179,8 @@
|
|||
&mmc0 {
|
||||
num-slots = <1>;
|
||||
status = "okay";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&sd0_clk>, <&sd0_cmd>, <&sd0_cd>, <&sd0_bus4>;
|
||||
vmmc-supply = <&vcc_sd0>;
|
||||
|
||||
slot@0 {
|
||||
|
|
|
|||
|
|
@ -660,6 +660,8 @@
|
|||
clock-frequency = <100000>;
|
||||
resets = <&apb2_rst 0>;
|
||||
status = "disabled";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
};
|
||||
|
||||
i2c1: i2c@01c2b000 {
|
||||
|
|
@ -670,6 +672,8 @@
|
|||
clock-frequency = <100000>;
|
||||
resets = <&apb2_rst 1>;
|
||||
status = "disabled";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
};
|
||||
|
||||
i2c2: i2c@01c2b400 {
|
||||
|
|
@ -680,6 +684,8 @@
|
|||
clock-frequency = <100000>;
|
||||
resets = <&apb2_rst 2>;
|
||||
status = "disabled";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
};
|
||||
|
||||
i2c3: i2c@01c2b800 {
|
||||
|
|
@ -690,6 +696,8 @@
|
|||
clock-frequency = <100000>;
|
||||
resets = <&apb2_rst 3>;
|
||||
status = "disabled";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
};
|
||||
|
||||
gmac: ethernet@01c30000 {
|
||||
|
|
|
|||
|
|
@ -423,7 +423,7 @@
|
|||
vcc4-supply = <&sys_3v3_reg>;
|
||||
vcc5-supply = <&sys_3v3_reg>;
|
||||
vcc6-supply = <&vio_reg>;
|
||||
vcc7-supply = <&sys_5v0_reg>;
|
||||
vcc7-supply = <&charge_pump_5v0_reg>;
|
||||
vccio-supply = <&sys_3v3_reg>;
|
||||
|
||||
regulators {
|
||||
|
|
@ -674,5 +674,14 @@
|
|||
regulator-max-microvolt = <3300000>;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
charge_pump_5v0_reg: regulator@101 {
|
||||
compatible = "regulator-fixed";
|
||||
reg = <101>;
|
||||
regulator-name = "5v0";
|
||||
regulator-min-microvolt = <5000000>;
|
||||
regulator-max-microvolt = <5000000>;
|
||||
regulator-always-on;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
|
|||
|
|
@ -201,7 +201,7 @@
|
|||
vcc4-supply = <&sys_3v3_reg>;
|
||||
vcc5-supply = <&sys_3v3_reg>;
|
||||
vcc6-supply = <&vio_reg>;
|
||||
vcc7-supply = <&sys_5v0_reg>;
|
||||
vcc7-supply = <&charge_pump_5v0_reg>;
|
||||
vccio-supply = <&sys_3v3_reg>;
|
||||
|
||||
regulators {
|
||||
|
|
@ -373,5 +373,14 @@
|
|||
regulator-max-microvolt = <3300000>;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
charge_pump_5v0_reg: regulator@101 {
|
||||
compatible = "regulator-fixed";
|
||||
reg = <101>;
|
||||
regulator-name = "5v0";
|
||||
regulator-min-microvolt = <5000000>;
|
||||
regulator-max-microvolt = <5000000>;
|
||||
regulator-always-on;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
|
|||
|
|
@ -168,7 +168,7 @@
|
|||
};
|
||||
|
||||
pinctrl_esdhc1: esdhc1grp {
|
||||
fsl,fsl,pins = <
|
||||
fsl,pins = <
|
||||
VF610_PAD_PTA24__ESDHC1_CLK 0x31ef
|
||||
VF610_PAD_PTA25__ESDHC1_CMD 0x31ef
|
||||
VF610_PAD_PTA26__ESDHC1_DAT0 0x31ef
|
||||
|
|
|
|||
|
|
@ -85,7 +85,6 @@ config SOC_IMX25
|
|||
|
||||
config SOC_IMX27
|
||||
bool
|
||||
select ARCH_HAS_OPP
|
||||
select CPU_ARM926T
|
||||
select IMX_HAVE_IOMUX_V1
|
||||
select MXC_AVIC
|
||||
|
|
@ -659,7 +658,6 @@ comment "Device tree only"
|
|||
|
||||
config SOC_IMX5
|
||||
bool
|
||||
select ARCH_HAS_OPP
|
||||
select HAVE_IMX_SRC
|
||||
select MXC_TZIC
|
||||
|
||||
|
|
|
|||
|
|
@ -93,9 +93,11 @@ obj-$(CONFIG_HAVE_IMX_ANATOP) += anatop.o
|
|||
obj-$(CONFIG_HAVE_IMX_GPC) += gpc.o
|
||||
obj-$(CONFIG_HAVE_IMX_MMDC) += mmdc.o
|
||||
obj-$(CONFIG_HAVE_IMX_SRC) += src.o
|
||||
ifdef CONFIG_SOC_IMX6
|
||||
AFLAGS_headsmp.o :=-Wa,-march=armv7-a
|
||||
obj-$(CONFIG_SMP) += headsmp.o platsmp.o
|
||||
obj-$(CONFIG_HOTPLUG_CPU) += hotplug.o
|
||||
endif
|
||||
obj-$(CONFIG_SOC_IMX6Q) += clk-imx6q.o mach-imx6q.o
|
||||
obj-$(CONFIG_SOC_IMX6SL) += clk-imx6sl.o mach-imx6sl.o
|
||||
obj-$(CONFIG_SOC_IMX6SX) += clk-imx6sx.o mach-imx6sx.o
|
||||
|
|
|
|||
|
|
@ -194,6 +194,10 @@ static void __init imx6q_clocks_init(struct device_node *ccm_node)
|
|||
clk[IMX6QDL_CLK_PLL3_80M] = imx_clk_fixed_factor("pll3_80m", "pll3_usb_otg", 1, 6);
|
||||
clk[IMX6QDL_CLK_PLL3_60M] = imx_clk_fixed_factor("pll3_60m", "pll3_usb_otg", 1, 8);
|
||||
clk[IMX6QDL_CLK_TWD] = imx_clk_fixed_factor("twd", "arm", 1, 2);
|
||||
if (cpu_is_imx6dl()) {
|
||||
clk[IMX6QDL_CLK_GPU2D_AXI] = imx_clk_fixed_factor("gpu2d_axi", "mmdc_ch0_axi_podf", 1, 1);
|
||||
clk[IMX6QDL_CLK_GPU3D_AXI] = imx_clk_fixed_factor("gpu3d_axi", "mmdc_ch0_axi_podf", 1, 1);
|
||||
}
|
||||
|
||||
clk[IMX6QDL_CLK_PLL4_POST_DIV] = clk_register_divider_table(NULL, "pll4_post_div", "pll4_audio", CLK_SET_RATE_PARENT, base + 0x70, 19, 2, 0, post_div_table, &imx_ccm_lock);
|
||||
clk[IMX6QDL_CLK_PLL4_AUDIO_DIV] = clk_register_divider(NULL, "pll4_audio_div", "pll4_post_div", CLK_SET_RATE_PARENT, base + 0x170, 15, 1, 0, &imx_ccm_lock);
|
||||
|
|
@ -217,8 +221,10 @@ static void __init imx6q_clocks_init(struct device_node *ccm_node)
|
|||
clk[IMX6QDL_CLK_ESAI_SEL] = imx_clk_mux("esai_sel", base + 0x20, 19, 2, audio_sels, ARRAY_SIZE(audio_sels));
|
||||
clk[IMX6QDL_CLK_ASRC_SEL] = imx_clk_mux("asrc_sel", base + 0x30, 7, 2, audio_sels, ARRAY_SIZE(audio_sels));
|
||||
clk[IMX6QDL_CLK_SPDIF_SEL] = imx_clk_mux("spdif_sel", base + 0x30, 20, 2, audio_sels, ARRAY_SIZE(audio_sels));
|
||||
if (cpu_is_imx6q()) {
|
||||
clk[IMX6QDL_CLK_GPU2D_AXI] = imx_clk_mux("gpu2d_axi", base + 0x18, 0, 1, gpu_axi_sels, ARRAY_SIZE(gpu_axi_sels));
|
||||
clk[IMX6QDL_CLK_GPU3D_AXI] = imx_clk_mux("gpu3d_axi", base + 0x18, 1, 1, gpu_axi_sels, ARRAY_SIZE(gpu_axi_sels));
|
||||
}
|
||||
clk[IMX6QDL_CLK_GPU2D_CORE_SEL] = imx_clk_mux("gpu2d_core_sel", base + 0x18, 16, 2, gpu2d_core_sels, ARRAY_SIZE(gpu2d_core_sels));
|
||||
clk[IMX6QDL_CLK_GPU3D_CORE_SEL] = imx_clk_mux("gpu3d_core_sel", base + 0x18, 4, 2, gpu3d_core_sels, ARRAY_SIZE(gpu3d_core_sels));
|
||||
clk[IMX6QDL_CLK_GPU3D_SHADER_SEL] = imx_clk_mux("gpu3d_shader_sel", base + 0x18, 8, 2, gpu3d_shader_sels, ARRAY_SIZE(gpu3d_shader_sels));
|
||||
|
|
|
|||
|
|
@ -173,6 +173,8 @@ ENTRY(imx6_suspend)
|
|||
ldr r6, [r11, #0x0]
|
||||
ldr r11, [r0, #PM_INFO_MX6Q_GPC_V_OFFSET]
|
||||
ldr r6, [r11, #0x0]
|
||||
ldr r11, [r0, #PM_INFO_MX6Q_IOMUXC_V_OFFSET]
|
||||
ldr r6, [r11, #0x0]
|
||||
|
||||
/* use r11 to store the IO address */
|
||||
ldr r11, [r0, #PM_INFO_MX6Q_SRC_V_OFFSET]
|
||||
|
|
|
|||
|
|
@ -75,6 +75,7 @@ config ARCH_SH7372
|
|||
select ARM_CPU_SUSPEND if PM || CPU_IDLE
|
||||
select CPU_V7
|
||||
select SH_CLK_CPG
|
||||
select SH_INTC
|
||||
select SYS_SUPPORTS_SH_CMT
|
||||
select SYS_SUPPORTS_SH_TMU
|
||||
|
||||
|
|
@ -85,6 +86,7 @@ config ARCH_SH73A0
|
|||
select CPU_V7
|
||||
select I2C
|
||||
select SH_CLK_CPG
|
||||
select SH_INTC
|
||||
select RENESAS_INTC_IRQPIN
|
||||
select SYS_SUPPORTS_SH_CMT
|
||||
select SYS_SUPPORTS_SH_TMU
|
||||
|
|
|
|||
|
|
@ -39,7 +39,7 @@ head-y := arch/arm64/kernel/head.o
|
|||
|
||||
# The byte offset of the kernel image in RAM from the start of RAM.
|
||||
ifeq ($(CONFIG_ARM64_RANDOMIZE_TEXT_OFFSET), y)
|
||||
TEXT_OFFSET := $(shell awk 'BEGIN {srand(); printf "0x%04x0\n", int(65535 * rand())}')
|
||||
TEXT_OFFSET := $(shell awk 'BEGIN {srand(); printf "0x%03x000\n", int(512 * rand())}')
|
||||
else
|
||||
TEXT_OFFSET := 0x00080000
|
||||
endif
|
||||
|
|
|
|||
|
|
@ -64,6 +64,8 @@ CONFIG_VIRTIO_BLK=y
|
|||
CONFIG_BLK_DEV_SD=y
|
||||
# CONFIG_SCSI_LOWLEVEL is not set
|
||||
CONFIG_ATA=y
|
||||
CONFIG_AHCI_XGENE=y
|
||||
CONFIG_PHY_XGENE=y
|
||||
CONFIG_PATA_PLATFORM=y
|
||||
CONFIG_PATA_OF_PLATFORM=y
|
||||
CONFIG_NETDEVICES=y
|
||||
|
|
@ -71,6 +73,7 @@ CONFIG_TUN=y
|
|||
CONFIG_VIRTIO_NET=y
|
||||
CONFIG_SMC91X=y
|
||||
CONFIG_SMSC911X=y
|
||||
CONFIG_NET_XGENE=y
|
||||
# CONFIG_WLAN is not set
|
||||
CONFIG_INPUT_EVDEV=y
|
||||
# CONFIG_SERIO_SERPORT is not set
|
||||
|
|
|
|||
|
|
@ -17,7 +17,7 @@
|
|||
#define __ASM_SPARSEMEM_H
|
||||
|
||||
#ifdef CONFIG_SPARSEMEM
|
||||
#define MAX_PHYSMEM_BITS 40
|
||||
#define MAX_PHYSMEM_BITS 48
|
||||
#define SECTION_SIZE_BITS 30
|
||||
#endif
|
||||
|
||||
|
|
|
|||
|
|
@ -41,7 +41,7 @@
|
|||
#define __ARM_NR_compat_cacheflush (__ARM_NR_COMPAT_BASE+2)
|
||||
#define __ARM_NR_compat_set_tls (__ARM_NR_COMPAT_BASE+5)
|
||||
|
||||
#define __NR_compat_syscalls 383
|
||||
#define __NR_compat_syscalls 386
|
||||
#endif
|
||||
|
||||
#define __ARCH_WANT_SYS_CLONE
|
||||
|
|
|
|||
|
|
@ -787,3 +787,8 @@ __SYSCALL(__NR_sched_setattr, sys_sched_setattr)
|
|||
__SYSCALL(__NR_sched_getattr, sys_sched_getattr)
|
||||
#define __NR_renameat2 382
|
||||
__SYSCALL(__NR_renameat2, sys_renameat2)
|
||||
/* 383 for seccomp */
|
||||
#define __NR_getrandom 384
|
||||
__SYSCALL(__NR_getrandom, sys_getrandom)
|
||||
#define __NR_memfd_create 385
|
||||
__SYSCALL(__NR_memfd_create, sys_memfd_create)
|
||||
|
|
|
|||
|
|
@ -49,7 +49,7 @@ static void cpuinfo_detect_icache_policy(struct cpuinfo_arm64 *info)
|
|||
|
||||
if (l1ip != ICACHE_POLICY_PIPT)
|
||||
set_bit(ICACHEF_ALIASING, &__icache_flags);
|
||||
if (l1ip == ICACHE_POLICY_AIVIVT);
|
||||
if (l1ip == ICACHE_POLICY_AIVIVT)
|
||||
set_bit(ICACHEF_AIVIVT, &__icache_flags);
|
||||
|
||||
pr_info("Detected %s I-cache on CPU%d\n", icache_policy_str[l1ip], cpu);
|
||||
|
|
|
|||
|
|
@ -188,6 +188,8 @@ static __init void reserve_regions(void)
|
|||
if (uefi_debug)
|
||||
pr_cont("\n");
|
||||
}
|
||||
|
||||
set_bit(EFI_MEMMAP, &efi.flags);
|
||||
}
|
||||
|
||||
|
||||
|
|
@ -463,6 +465,8 @@ static int __init arm64_enter_virtual_mode(void)
|
|||
efi_native_runtime_setup();
|
||||
set_bit(EFI_RUNTIME_SERVICES, &efi.flags);
|
||||
|
||||
efi.runtime_version = efi.systab->hdr.revision;
|
||||
|
||||
return 0;
|
||||
|
||||
err_unmap:
|
||||
|
|
|
|||
|
|
@ -38,11 +38,11 @@
|
|||
|
||||
#define KERNEL_RAM_VADDR (PAGE_OFFSET + TEXT_OFFSET)
|
||||
|
||||
#if (TEXT_OFFSET & 0xf) != 0
|
||||
#error TEXT_OFFSET must be at least 16B aligned
|
||||
#elif (PAGE_OFFSET & 0xfffff) != 0
|
||||
#if (TEXT_OFFSET & 0xfff) != 0
|
||||
#error TEXT_OFFSET must be at least 4KB aligned
|
||||
#elif (PAGE_OFFSET & 0x1fffff) != 0
|
||||
#error PAGE_OFFSET must be at least 2MB aligned
|
||||
#elif TEXT_OFFSET > 0xfffff
|
||||
#elif TEXT_OFFSET > 0x1fffff
|
||||
#error TEXT_OFFSET must be less than 2MB
|
||||
#endif
|
||||
|
||||
|
|
|
|||
|
|
@ -1115,19 +1115,15 @@ asmlinkage int syscall_trace_enter(struct pt_regs *regs)
|
|||
if (test_thread_flag(TIF_SYSCALL_TRACEPOINT))
|
||||
trace_sys_enter(regs, regs->syscallno);
|
||||
|
||||
#ifdef CONFIG_AUDITSYSCALL
|
||||
audit_syscall_entry(syscall_get_arch(), regs->syscallno,
|
||||
regs->orig_x0, regs->regs[1], regs->regs[2], regs->regs[3]);
|
||||
#endif
|
||||
|
||||
return regs->syscallno;
|
||||
}
|
||||
|
||||
asmlinkage void syscall_trace_exit(struct pt_regs *regs)
|
||||
{
|
||||
#ifdef CONFIG_AUDITSYSCALL
|
||||
audit_syscall_exit(regs);
|
||||
#endif
|
||||
|
||||
if (test_thread_flag(TIF_SYSCALL_TRACEPOINT))
|
||||
trace_sys_exit(regs, regs_return_value(regs));
|
||||
|
|
|
|||
|
|
@ -32,6 +32,7 @@
|
|||
#include <linux/of_fdt.h>
|
||||
#include <linux/dma-mapping.h>
|
||||
#include <linux/dma-contiguous.h>
|
||||
#include <linux/efi.h>
|
||||
|
||||
#include <asm/fixmap.h>
|
||||
#include <asm/sections.h>
|
||||
|
|
@ -148,6 +149,7 @@ void __init arm64_memblock_init(void)
|
|||
memblock_reserve(__virt_to_phys(initrd_start), initrd_end - initrd_start);
|
||||
#endif
|
||||
|
||||
if (!efi_enabled(EFI_MEMMAP))
|
||||
early_init_fdt_scan_reserved_mem();
|
||||
|
||||
/* 4GB maximum for 32-bit only capable devices */
|
||||
|
|
|
|||
|
|
@ -130,6 +130,7 @@ unsigned long get_wchan(struct task_struct *p);
|
|||
#define KSTK_ESP(tsk) ((tsk)->thread.frame0->sp)
|
||||
|
||||
#define cpu_relax() barrier()
|
||||
#define cpu_relax_lowlatency() cpu_relax()
|
||||
|
||||
/* data cache prefetch */
|
||||
#define ARCH_HAS_PREFETCH
|
||||
|
|
|
|||
|
|
@ -11,7 +11,7 @@
|
|||
|
||||
|
||||
|
||||
#define NR_syscalls 316 /* length of syscall table */
|
||||
#define NR_syscalls 317 /* length of syscall table */
|
||||
|
||||
/*
|
||||
* The following defines stop scripts/checksyscalls.sh from complaining about
|
||||
|
|
|
|||
|
|
@ -329,5 +329,6 @@
|
|||
#define __NR_sched_getattr 1337
|
||||
#define __NR_renameat2 1338
|
||||
#define __NR_getrandom 1339
|
||||
#define __NR_memfd_create 1339
|
||||
|
||||
#endif /* _UAPI_ASM_IA64_UNISTD_H */
|
||||
|
|
|
|||
|
|
@ -1777,6 +1777,7 @@ sys_call_table:
|
|||
data8 sys_sched_getattr
|
||||
data8 sys_renameat2
|
||||
data8 sys_getrandom
|
||||
data8 sys_memfd_create // 1340
|
||||
|
||||
.org sys_call_table + 8*NR_syscalls // guard against failures to increase NR_syscalls
|
||||
#endif /* __IA64_ASM_PARAVIRTUALIZED_NATIVE */
|
||||
|
|
|
|||
|
|
@ -399,5 +399,8 @@
|
|||
#define __NR_sched_setattr 381
|
||||
#define __NR_sched_getattr 382
|
||||
#define __NR_renameat2 383
|
||||
#define __NR_seccomp 384
|
||||
#define __NR_getrandom 385
|
||||
#define __NR_memfd_create 386
|
||||
|
||||
#endif /* _UAPI_ASM_MICROBLAZE_UNISTD_H */
|
||||
|
|
|
|||
|
|
@ -384,3 +384,6 @@ ENTRY(sys_call_table)
|
|||
.long sys_sched_setattr
|
||||
.long sys_sched_getattr
|
||||
.long sys_renameat2
|
||||
.long sys_seccomp
|
||||
.long sys_getrandom /* 385 */
|
||||
.long sys_memfd_create
|
||||
|
|
|
|||
|
|
@ -847,6 +847,7 @@ int __init db1200_dev_setup(void)
|
|||
pr_warn("DB1200: cant get I2C close to 50MHz\n");
|
||||
else
|
||||
clk_set_rate(c, pfc);
|
||||
clk_prepare_enable(c);
|
||||
clk_put(c);
|
||||
}
|
||||
|
||||
|
|
@ -922,11 +923,6 @@ int __init db1200_dev_setup(void)
|
|||
}
|
||||
|
||||
/* Audio PSC clock is supplied externally. (FIXME: platdata!!) */
|
||||
c = clk_get(NULL, "psc1_intclk");
|
||||
if (!IS_ERR(c)) {
|
||||
clk_prepare_enable(c);
|
||||
clk_put(c);
|
||||
}
|
||||
__raw_writel(PSC_SEL_CLK_SERCLK,
|
||||
(void __iomem *)KSEG1ADDR(AU1550_PSC1_PHYS_ADDR) + PSC_SEL_OFFSET);
|
||||
wmb();
|
||||
|
|
|
|||
|
|
@ -59,12 +59,21 @@ static void bcm47xx_machine_restart(char *command)
|
|||
switch (bcm47xx_bus_type) {
|
||||
#ifdef CONFIG_BCM47XX_SSB
|
||||
case BCM47XX_BUS_TYPE_SSB:
|
||||
ssb_watchdog_timer_set(&bcm47xx_bus.ssb, 3);
|
||||
if (bcm47xx_bus.ssb.chip_id == 0x4785)
|
||||
write_c0_diag4(1 << 22);
|
||||
ssb_watchdog_timer_set(&bcm47xx_bus.ssb, 1);
|
||||
if (bcm47xx_bus.ssb.chip_id == 0x4785) {
|
||||
__asm__ __volatile__(
|
||||
".set\tmips3\n\t"
|
||||
"sync\n\t"
|
||||
"wait\n\t"
|
||||
".set\tmips0");
|
||||
}
|
||||
break;
|
||||
#endif
|
||||
#ifdef CONFIG_BCM47XX_BCMA
|
||||
case BCM47XX_BUS_TYPE_BCMA:
|
||||
bcma_chipco_watchdog_timer_set(&bcm47xx_bus.bcma.bus.drv_cc, 3);
|
||||
bcma_chipco_watchdog_timer_set(&bcm47xx_bus.bcma.bus.drv_cc, 1);
|
||||
break;
|
||||
#endif
|
||||
}
|
||||
|
|
|
|||
|
|
@ -263,7 +263,6 @@ static uint64_t crashk_size, crashk_base;
|
|||
static int octeon_uart;
|
||||
|
||||
extern asmlinkage void handle_int(void);
|
||||
extern asmlinkage void plat_irq_dispatch(void);
|
||||
|
||||
/**
|
||||
* Return non zero if we are currently running in the Octeon simulator
|
||||
|
|
@ -458,6 +457,18 @@ static void octeon_halt(void)
|
|||
octeon_kill_core(NULL);
|
||||
}
|
||||
|
||||
static char __read_mostly octeon_system_type[80];
|
||||
|
||||
static int __init init_octeon_system_type(void)
|
||||
{
|
||||
snprintf(octeon_system_type, sizeof(octeon_system_type), "%s (%s)",
|
||||
cvmx_board_type_to_string(octeon_bootinfo->board_type),
|
||||
octeon_model_get_string(read_c0_prid()));
|
||||
|
||||
return 0;
|
||||
}
|
||||
early_initcall(init_octeon_system_type);
|
||||
|
||||
/**
|
||||
* Return a string representing the system type
|
||||
*
|
||||
|
|
@ -465,11 +476,7 @@ static void octeon_halt(void)
|
|||
*/
|
||||
const char *octeon_board_type_string(void)
|
||||
{
|
||||
static char name[80];
|
||||
sprintf(name, "%s (%s)",
|
||||
cvmx_board_type_to_string(octeon_bootinfo->board_type),
|
||||
octeon_model_get_string(read_c0_prid()));
|
||||
return name;
|
||||
return octeon_system_type;
|
||||
}
|
||||
|
||||
const char *get_system_type(void)
|
||||
|
|
|
|||
|
|
@ -0,0 +1,43 @@
|
|||
/*
|
||||
* This file is subject to the terms and conditions of the GNU General Public
|
||||
* License. See the file "COPYING" in the main directory of this archive
|
||||
* for more details.
|
||||
*
|
||||
* Copyright (C) 2014, Imagination Technologies Ltd.
|
||||
*
|
||||
* EVA functions for generic code
|
||||
*/
|
||||
|
||||
#ifndef _ASM_EVA_H
|
||||
#define _ASM_EVA_H
|
||||
|
||||
#include <kernel-entry-init.h>
|
||||
|
||||
#ifdef __ASSEMBLY__
|
||||
|
||||
#ifdef CONFIG_EVA
|
||||
|
||||
/*
|
||||
* EVA early init code
|
||||
*
|
||||
* Platforms must define their own 'platform_eva_init' macro in
|
||||
* their kernel-entry-init.h header. This macro usually does the
|
||||
* platform specific configuration of the segmentation registers,
|
||||
* and it is normally called from assembly code.
|
||||
*
|
||||
*/
|
||||
|
||||
.macro eva_init
|
||||
platform_eva_init
|
||||
.endm
|
||||
|
||||
#else
|
||||
|
||||
.macro eva_init
|
||||
.endm
|
||||
|
||||
#endif /* CONFIG_EVA */
|
||||
|
||||
#endif /* __ASSEMBLY__ */
|
||||
|
||||
#endif
|
||||
|
|
@ -49,7 +49,7 @@
|
|||
#endif
|
||||
#define GICBIS(reg, mask, bits) \
|
||||
do { u32 data; \
|
||||
GICREAD((reg), data); \
|
||||
GICREAD(reg, data); \
|
||||
data &= ~(mask); \
|
||||
data |= ((bits) & (mask)); \
|
||||
GICWRITE((reg), data); \
|
||||
|
|
|
|||
|
|
@ -26,6 +26,8 @@ static inline int irq_canonicalize(int irq)
|
|||
#define irq_canonicalize(irq) (irq) /* Sane hardware, sane code ... */
|
||||
#endif
|
||||
|
||||
asmlinkage void plat_irq_dispatch(void);
|
||||
|
||||
extern void do_IRQ(unsigned int irq);
|
||||
|
||||
extern void arch_init_irq(void);
|
||||
|
|
|
|||
|
|
@ -10,14 +10,15 @@
|
|||
#ifndef __ASM_MACH_MIPS_KERNEL_ENTRY_INIT_H
|
||||
#define __ASM_MACH_MIPS_KERNEL_ENTRY_INIT_H
|
||||
|
||||
#include <asm/regdef.h>
|
||||
#include <asm/mipsregs.h>
|
||||
|
||||
/*
|
||||
* Prepare segments for EVA boot:
|
||||
*
|
||||
* This is in case the processor boots in legacy configuration
|
||||
* (SI_EVAReset is de-asserted and CONFIG5.K == 0)
|
||||
*
|
||||
* On entry, t1 is loaded with CP0_CONFIG
|
||||
*
|
||||
* ========================= Mappings =============================
|
||||
* Virtual memory Physical memory Mapping
|
||||
* 0x00000000 - 0x7fffffff 0x80000000 - 0xfffffffff MUSUK (kuseg)
|
||||
|
|
@ -30,12 +31,20 @@
|
|||
*
|
||||
*
|
||||
* Lowmem is expanded to 2GB
|
||||
*
|
||||
* The following code uses the t0, t1, t2 and ra registers without
|
||||
* previously preserving them.
|
||||
*
|
||||
*/
|
||||
.macro eva_entry
|
||||
.macro platform_eva_init
|
||||
|
||||
.set push
|
||||
.set reorder
|
||||
/*
|
||||
* Get Config.K0 value and use it to program
|
||||
* the segmentation registers
|
||||
*/
|
||||
mfc0 t1, CP0_CONFIG
|
||||
andi t1, 0x7 /* CCA */
|
||||
move t2, t1
|
||||
ins t2, t1, 16, 3
|
||||
|
|
@ -77,6 +86,8 @@
|
|||
mtc0 t0, $16, 5
|
||||
sync
|
||||
jal mips_ihb
|
||||
|
||||
.set pop
|
||||
.endm
|
||||
|
||||
.macro kernel_entry_setup
|
||||
|
|
@ -95,7 +106,7 @@
|
|||
sll t0, t0, 6 /* SC bit */
|
||||
bgez t0, 9f
|
||||
|
||||
eva_entry
|
||||
platform_eva_init
|
||||
b 0f
|
||||
9:
|
||||
/* Assume we came from YAMON... */
|
||||
|
|
@ -127,8 +138,7 @@ nonsc_processor:
|
|||
#ifdef CONFIG_EVA
|
||||
sync
|
||||
ehb
|
||||
mfc0 t1, CP0_CONFIG
|
||||
eva_entry
|
||||
platform_eva_init
|
||||
#endif
|
||||
.endm
|
||||
|
||||
|
|
|
|||
|
|
@ -10,13 +10,6 @@
|
|||
|
||||
#include <asm/mach-netlogic/multi-node.h>
|
||||
|
||||
#ifdef CONFIG_SMP
|
||||
#define topology_physical_package_id(cpu) cpu_to_node(cpu)
|
||||
#define topology_core_id(cpu) (cpu_logical_map(cpu) / NLM_THREADS_PER_CORE)
|
||||
#define topology_thread_cpumask(cpu) (&cpu_sibling_map[cpu])
|
||||
#define topology_core_cpumask(cpu) cpumask_of_node(cpu_to_node(cpu))
|
||||
#endif
|
||||
|
||||
#include <asm-generic/topology.h>
|
||||
|
||||
#endif /* _ASM_MACH_NETLOGIC_TOPOLOGY_H */
|
||||
|
|
|
|||
|
|
@ -122,6 +122,9 @@ do { \
|
|||
} \
|
||||
} while(0)
|
||||
|
||||
extern void set_pte_at(struct mm_struct *mm, unsigned long addr, pte_t *ptep,
|
||||
pte_t pteval);
|
||||
|
||||
#if defined(CONFIG_64BIT_PHYS_ADDR) && defined(CONFIG_CPU_MIPS32)
|
||||
|
||||
#define pte_none(pte) (!(((pte).pte_low | (pte).pte_high) & ~_PAGE_GLOBAL))
|
||||
|
|
@ -145,7 +148,6 @@ static inline void set_pte(pte_t *ptep, pte_t pte)
|
|||
}
|
||||
}
|
||||
}
|
||||
#define set_pte_at(mm, addr, ptep, pteval) set_pte(ptep, pteval)
|
||||
|
||||
static inline void pte_clear(struct mm_struct *mm, unsigned long addr, pte_t *ptep)
|
||||
{
|
||||
|
|
@ -183,7 +185,6 @@ static inline void set_pte(pte_t *ptep, pte_t pteval)
|
|||
}
|
||||
#endif
|
||||
}
|
||||
#define set_pte_at(mm, addr, ptep, pteval) set_pte(ptep, pteval)
|
||||
|
||||
static inline void pte_clear(struct mm_struct *mm, unsigned long addr, pte_t *ptep)
|
||||
{
|
||||
|
|
@ -390,15 +391,12 @@ static inline pte_t pte_modify(pte_t pte, pgprot_t newprot)
|
|||
|
||||
extern void __update_tlb(struct vm_area_struct *vma, unsigned long address,
|
||||
pte_t pte);
|
||||
extern void __update_cache(struct vm_area_struct *vma, unsigned long address,
|
||||
pte_t pte);
|
||||
|
||||
static inline void update_mmu_cache(struct vm_area_struct *vma,
|
||||
unsigned long address, pte_t *ptep)
|
||||
{
|
||||
pte_t pte = *ptep;
|
||||
__update_tlb(vma, address, pte);
|
||||
__update_cache(vma, address, pte);
|
||||
}
|
||||
|
||||
static inline void update_mmu_cache_pmd(struct vm_area_struct *vma,
|
||||
|
|
|
|||
|
|
@ -131,10 +131,12 @@ static inline int syscall_get_arch(void)
|
|||
{
|
||||
int arch = EM_MIPS;
|
||||
#ifdef CONFIG_64BIT
|
||||
if (!test_thread_flag(TIF_32BIT_REGS))
|
||||
if (!test_thread_flag(TIF_32BIT_REGS)) {
|
||||
arch |= __AUDIT_ARCH_64BIT;
|
||||
/* N32 sets only TIF_32BIT_ADDR */
|
||||
if (test_thread_flag(TIF_32BIT_ADDR))
|
||||
arch |= __AUDIT_ARCH_CONVENTION_MIPS64_N32;
|
||||
}
|
||||
#endif
|
||||
#if defined(__LITTLE_ENDIAN)
|
||||
arch |= __AUDIT_ARCH_LE;
|
||||
|
|
|
|||
|
|
@ -13,6 +13,7 @@
|
|||
#include <asm/asm-offsets.h>
|
||||
#include <asm/asmmacro.h>
|
||||
#include <asm/cacheops.h>
|
||||
#include <asm/eva.h>
|
||||
#include <asm/mipsregs.h>
|
||||
#include <asm/mipsmtregs.h>
|
||||
#include <asm/pm.h>
|
||||
|
|
@ -166,6 +167,9 @@ dcache_done:
|
|||
1: jal mips_cps_core_init
|
||||
nop
|
||||
|
||||
/* Do any EVA initialization if necessary */
|
||||
eva_init
|
||||
|
||||
/*
|
||||
* Boot any other VPEs within this core that should be online, and
|
||||
* deactivate this VPE if it should be offline.
|
||||
|
|
|
|||
|
|
@ -558,7 +558,7 @@ static int mipspmu_get_irq(void)
|
|||
if (mipspmu.irq >= 0) {
|
||||
/* Request my own irq handler. */
|
||||
err = request_irq(mipspmu.irq, mipsxx_pmu_handle_irq,
|
||||
IRQF_PERCPU | IRQF_NOBALANCING,
|
||||
IRQF_PERCPU | IRQF_NOBALANCING | IRQF_NO_THREAD,
|
||||
"mips_perf_pmu", NULL);
|
||||
if (err) {
|
||||
pr_warning("Unable to request IRQ%d for MIPS "
|
||||
|
|
|
|||
|
|
@ -113,15 +113,19 @@ trace_a_syscall:
|
|||
move s0, t2 # Save syscall pointer
|
||||
move a0, sp
|
||||
/*
|
||||
* syscall number is in v0 unless we called syscall(__NR_###)
|
||||
* absolute syscall number is in v0 unless we called syscall(__NR_###)
|
||||
* where the real syscall number is in a0
|
||||
* note: NR_syscall is the first O32 syscall but the macro is
|
||||
* only defined when compiling with -mabi=32 (CONFIG_32BIT)
|
||||
* therefore __NR_O32_Linux is used (4000)
|
||||
*/
|
||||
addiu a1, v0, __NR_O32_Linux
|
||||
bnez v0, 1f /* __NR_syscall at offset 0 */
|
||||
lw a1, PT_R4(sp)
|
||||
.set push
|
||||
.set reorder
|
||||
subu t1, v0, __NR_O32_Linux
|
||||
move a1, v0
|
||||
bnez t1, 1f /* __NR_syscall at offset 0 */
|
||||
lw a1, PT_R4(sp) /* Arg1 for __NR_syscall case */
|
||||
.set pop
|
||||
|
||||
1: jal syscall_trace_enter
|
||||
|
||||
|
|
|
|||
|
|
@ -22,13 +22,13 @@
|
|||
static int loongson_cu2_call(struct notifier_block *nfb, unsigned long action,
|
||||
void *data)
|
||||
{
|
||||
int fpu_enabled;
|
||||
int fpu_owned;
|
||||
int fr = !test_thread_flag(TIF_32BIT_FPREGS);
|
||||
|
||||
switch (action) {
|
||||
case CU2_EXCEPTION:
|
||||
preempt_disable();
|
||||
fpu_enabled = read_c0_status() & ST0_CU1;
|
||||
fpu_owned = __is_fpu_owner();
|
||||
if (!fr)
|
||||
set_c0_status(ST0_CU1 | ST0_CU2);
|
||||
else
|
||||
|
|
@ -39,8 +39,8 @@ static int loongson_cu2_call(struct notifier_block *nfb, unsigned long action,
|
|||
KSTK_STATUS(current) |= ST0_FR;
|
||||
else
|
||||
KSTK_STATUS(current) &= ~ST0_FR;
|
||||
/* If FPU is enabled, we needn't init or restore fp */
|
||||
if(!fpu_enabled) {
|
||||
/* If FPU is owned, we needn't init or restore fp */
|
||||
if (!fpu_owned) {
|
||||
set_thread_flag(TIF_USEDFPU);
|
||||
if (!used_math()) {
|
||||
_init_fpu();
|
||||
|
|
|
|||
|
|
@ -24,8 +24,6 @@
|
|||
#include <asm/page.h>
|
||||
#include <asm/pgalloc.h>
|
||||
#include <asm/sections.h>
|
||||
#include <linux/bootmem.h>
|
||||
#include <linux/init.h>
|
||||
#include <linux/irq.h>
|
||||
#include <asm/bootinfo.h>
|
||||
#include <asm/mc146818-time.h>
|
||||
|
|
|
|||
|
|
@ -119,25 +119,36 @@ void __flush_anon_page(struct page *page, unsigned long vmaddr)
|
|||
|
||||
EXPORT_SYMBOL(__flush_anon_page);
|
||||
|
||||
void __update_cache(struct vm_area_struct *vma, unsigned long address,
|
||||
pte_t pte)
|
||||
static void mips_flush_dcache_from_pte(pte_t pteval, unsigned long address)
|
||||
{
|
||||
struct page *page;
|
||||
unsigned long pfn, addr;
|
||||
int exec = (vma->vm_flags & VM_EXEC) && !cpu_has_ic_fills_f_dc;
|
||||
unsigned long pfn = pte_pfn(pteval);
|
||||
|
||||
pfn = pte_pfn(pte);
|
||||
if (unlikely(!pfn_valid(pfn)))
|
||||
return;
|
||||
|
||||
page = pfn_to_page(pfn);
|
||||
if (page_mapping(page) && Page_dcache_dirty(page)) {
|
||||
addr = (unsigned long) page_address(page);
|
||||
if (exec || pages_do_alias(addr, address & PAGE_MASK))
|
||||
flush_data_cache_page(addr);
|
||||
unsigned long page_addr = (unsigned long) page_address(page);
|
||||
|
||||
if (!cpu_has_ic_fills_f_dc ||
|
||||
pages_do_alias(page_addr, address & PAGE_MASK))
|
||||
flush_data_cache_page(page_addr);
|
||||
ClearPageDcacheDirty(page);
|
||||
}
|
||||
}
|
||||
|
||||
void set_pte_at(struct mm_struct *mm, unsigned long addr,
|
||||
pte_t *ptep, pte_t pteval)
|
||||
{
|
||||
if (cpu_has_dc_aliases || !cpu_has_ic_fills_f_dc) {
|
||||
if (pte_present(pteval))
|
||||
mips_flush_dcache_from_pte(pteval, addr);
|
||||
}
|
||||
|
||||
set_pte(ptep, pteval);
|
||||
}
|
||||
|
||||
unsigned long _page_cachable_default;
|
||||
EXPORT_SYMBOL(_page_cachable_default);
|
||||
|
||||
|
|
|
|||
|
|
@ -35,13 +35,19 @@ fw_memblock_t * __init fw_getmdesc(int eva)
|
|||
/* otherwise look in the environment */
|
||||
|
||||
memsize_str = fw_getenv("memsize");
|
||||
if (memsize_str)
|
||||
tmp = kstrtol(memsize_str, 0, &memsize);
|
||||
if (memsize_str) {
|
||||
tmp = kstrtoul(memsize_str, 0, &memsize);
|
||||
if (tmp)
|
||||
pr_warn("Failed to read the 'memsize' env variable.\n");
|
||||
}
|
||||
if (eva) {
|
||||
/* Look for ememsize for EVA */
|
||||
ememsize_str = fw_getenv("ememsize");
|
||||
if (ememsize_str)
|
||||
tmp = kstrtol(ememsize_str, 0, &ememsize);
|
||||
if (ememsize_str) {
|
||||
tmp = kstrtoul(ememsize_str, 0, &ememsize);
|
||||
if (tmp)
|
||||
pr_warn("Failed to read the 'ememsize' env variable.\n");
|
||||
}
|
||||
}
|
||||
if (!memsize && !ememsize) {
|
||||
pr_warn("memsize not set in YAMON, set to default (32Mb)\n");
|
||||
|
|
|
|||
|
|
@ -51,7 +51,7 @@ static inline void sec_int_dispatch(void) { do_IRQ(MSP_INT_SEC); }
|
|||
* the range 40-71.
|
||||
*/
|
||||
|
||||
asmlinkage void plat_irq_dispatch(struct pt_regs *regs)
|
||||
asmlinkage void plat_irq_dispatch(void)
|
||||
{
|
||||
u32 pending;
|
||||
|
||||
|
|
|
|||
|
|
@ -101,7 +101,7 @@ struct kvm_rma_info *kvm_alloc_rma()
|
|||
ri = kmalloc(sizeof(struct kvm_rma_info), GFP_KERNEL);
|
||||
if (!ri)
|
||||
return NULL;
|
||||
page = cma_alloc(kvm_cma, kvm_rma_pages, get_order(kvm_rma_pages));
|
||||
page = cma_alloc(kvm_cma, kvm_rma_pages, order_base_2(kvm_rma_pages));
|
||||
if (!page)
|
||||
goto err_out;
|
||||
atomic_set(&ri->use_count, 1);
|
||||
|
|
@ -135,12 +135,12 @@ struct page *kvm_alloc_hpt(unsigned long nr_pages)
|
|||
{
|
||||
unsigned long align_pages = HPT_ALIGN_PAGES;
|
||||
|
||||
VM_BUG_ON(get_order(nr_pages) < KVM_CMA_CHUNK_ORDER - PAGE_SHIFT);
|
||||
VM_BUG_ON(order_base_2(nr_pages) < KVM_CMA_CHUNK_ORDER - PAGE_SHIFT);
|
||||
|
||||
/* Old CPUs require HPT aligned on a multiple of its size */
|
||||
if (!cpu_has_feature(CPU_FTR_ARCH_206))
|
||||
align_pages = nr_pages;
|
||||
return cma_alloc(kvm_cma, nr_pages, get_order(align_pages));
|
||||
return cma_alloc(kvm_cma, nr_pages, order_base_2(align_pages));
|
||||
}
|
||||
EXPORT_SYMBOL_GPL(kvm_alloc_hpt);
|
||||
|
||||
|
|
|
|||
|
|
@ -172,6 +172,7 @@ menu "System type"
|
|||
#
|
||||
config CPU_SH2
|
||||
bool
|
||||
select SH_INTC
|
||||
|
||||
config CPU_SH2A
|
||||
bool
|
||||
|
|
@ -182,6 +183,7 @@ config CPU_SH3
|
|||
bool
|
||||
select CPU_HAS_INTEVT
|
||||
select CPU_HAS_SR_RB
|
||||
select SH_INTC
|
||||
select SYS_SUPPORTS_SH_TMU
|
||||
|
||||
config CPU_SH4
|
||||
|
|
@ -189,6 +191,7 @@ config CPU_SH4
|
|||
select CPU_HAS_INTEVT
|
||||
select CPU_HAS_SR_RB
|
||||
select CPU_HAS_FPU if !CPU_SH4AL_DSP
|
||||
select SH_INTC
|
||||
select SYS_SUPPORTS_SH_TMU
|
||||
select SYS_SUPPORTS_HUGETLBFS if MMU
|
||||
|
||||
|
|
|
|||
|
|
@ -95,7 +95,7 @@ static inline gfn_t gfn_to_index(gfn_t gfn, gfn_t base_gfn, int level)
|
|||
#define KVM_REFILL_PAGES 25
|
||||
#define KVM_MAX_CPUID_ENTRIES 80
|
||||
#define KVM_NR_FIXED_MTRR_REGION 88
|
||||
#define KVM_NR_VAR_MTRR 10
|
||||
#define KVM_NR_VAR_MTRR 8
|
||||
|
||||
#define ASYNC_PF_PER_VCPU 64
|
||||
|
||||
|
|
|
|||
|
|
@ -683,7 +683,7 @@ END(syscall_badsys)
|
|||
sysenter_badsys:
|
||||
movl $-ENOSYS,%eax
|
||||
jmp sysenter_after_call
|
||||
END(syscall_badsys)
|
||||
END(sysenter_badsys)
|
||||
CFI_ENDPROC
|
||||
|
||||
.macro FIXUP_ESPFIX_STACK
|
||||
|
|
|
|||
|
|
@ -1491,9 +1491,6 @@ static int __load_segment_descriptor(struct x86_emulate_ctxt *ctxt,
|
|||
goto exception;
|
||||
break;
|
||||
case VCPU_SREG_CS:
|
||||
if (in_task_switch && rpl != dpl)
|
||||
goto exception;
|
||||
|
||||
if (!(seg_desc.type & 8))
|
||||
goto exception;
|
||||
|
||||
|
|
@ -4394,8 +4391,11 @@ done_prefixes:
|
|||
|
||||
ctxt->execute = opcode.u.execute;
|
||||
|
||||
if (unlikely(ctxt->ud) && likely(!(ctxt->d & EmulateOnUD)))
|
||||
return EMULATION_FAILED;
|
||||
|
||||
if (unlikely(ctxt->d &
|
||||
(NotImpl|EmulateOnUD|Stack|Op3264|Sse|Mmx|Intercept|CheckPerm))) {
|
||||
(NotImpl|Stack|Op3264|Sse|Mmx|Intercept|CheckPerm))) {
|
||||
/*
|
||||
* These are copied unconditionally here, and checked unconditionally
|
||||
* in x86_emulate_insn.
|
||||
|
|
@ -4406,9 +4406,6 @@ done_prefixes:
|
|||
if (ctxt->d & NotImpl)
|
||||
return EMULATION_FAILED;
|
||||
|
||||
if (!(ctxt->d & EmulateOnUD) && ctxt->ud)
|
||||
return EMULATION_FAILED;
|
||||
|
||||
if (mode == X86EMUL_MODE_PROT64 && (ctxt->d & Stack))
|
||||
ctxt->op_bytes = 8;
|
||||
|
||||
|
|
|
|||
|
|
@ -49,7 +49,13 @@ void leave_mm(int cpu)
|
|||
if (cpumask_test_cpu(cpu, mm_cpumask(active_mm))) {
|
||||
cpumask_clear_cpu(cpu, mm_cpumask(active_mm));
|
||||
load_cr3(swapper_pg_dir);
|
||||
trace_tlb_flush(TLB_FLUSH_ON_TASK_SWITCH, TLB_FLUSH_ALL);
|
||||
/*
|
||||
* This gets called in the idle path where RCU
|
||||
* functions differently. Tracing normally
|
||||
* uses RCU, so we have to call the tracepoint
|
||||
* specially here.
|
||||
*/
|
||||
trace_tlb_flush_rcuidle(TLB_FLUSH_ON_TASK_SWITCH, TLB_FLUSH_ALL);
|
||||
}
|
||||
}
|
||||
EXPORT_SYMBOL_GPL(leave_mm);
|
||||
|
|
@ -174,7 +180,7 @@ void flush_tlb_current_task(void)
|
|||
*
|
||||
* This is in units of pages.
|
||||
*/
|
||||
unsigned long tlb_single_page_flush_ceiling = 33;
|
||||
static unsigned long tlb_single_page_flush_ceiling __read_mostly = 33;
|
||||
|
||||
void flush_tlb_mm_range(struct mm_struct *mm, unsigned long start,
|
||||
unsigned long end, unsigned long vmflag)
|
||||
|
|
|
|||
|
|
@ -24,8 +24,8 @@
|
|||
#include <linux/module.h>
|
||||
#include <linux/of_device.h>
|
||||
#include <linux/platform_device.h>
|
||||
#include <linux/tegra-powergate.h>
|
||||
#include <linux/regulator/consumer.h>
|
||||
#include <soc/tegra/pmc.h>
|
||||
#include "ahci.h"
|
||||
|
||||
#define SATA_CONFIGURATION_0 0x180
|
||||
|
|
|
|||
|
|
@ -344,7 +344,7 @@ static struct ata_port_operations xgene_ahci_ops = {
|
|||
};
|
||||
|
||||
static const struct ata_port_info xgene_ahci_port_info = {
|
||||
.flags = AHCI_FLAG_COMMON | ATA_FLAG_NCQ,
|
||||
.flags = AHCI_FLAG_COMMON,
|
||||
.pio_mask = ATA_PIO4,
|
||||
.udma_mask = ATA_UDMA6,
|
||||
.port_ops = &xgene_ahci_ops,
|
||||
|
|
@ -480,7 +480,7 @@ static int xgene_ahci_probe(struct platform_device *pdev)
|
|||
/* Configure the host controller */
|
||||
xgene_ahci_hw_init(hpriv);
|
||||
|
||||
hpriv->flags = AHCI_HFLAG_NO_PMP | AHCI_HFLAG_YES_NCQ;
|
||||
hpriv->flags = AHCI_HFLAG_NO_PMP | AHCI_HFLAG_NO_NCQ;
|
||||
|
||||
rc = ahci_platform_init_host(pdev, hpriv, &xgene_ahci_port_info);
|
||||
if (rc)
|
||||
|
|
|
|||
|
|
@ -4228,7 +4228,7 @@ static const struct ata_blacklist_entry ata_device_blacklist [] = {
|
|||
{ "Micron_M500*", NULL, ATA_HORKAGE_NO_NCQ_TRIM, },
|
||||
{ "Crucial_CT???M500SSD*", NULL, ATA_HORKAGE_NO_NCQ_TRIM, },
|
||||
{ "Micron_M550*", NULL, ATA_HORKAGE_NO_NCQ_TRIM, },
|
||||
{ "Crucial_CT???M550SSD*", NULL, ATA_HORKAGE_NO_NCQ_TRIM, },
|
||||
{ "Crucial_CT*M550SSD*", NULL, ATA_HORKAGE_NO_NCQ_TRIM, },
|
||||
|
||||
/*
|
||||
* Some WD SATA-I drives spin up and down erratically when the link
|
||||
|
|
|
|||
|
|
@ -360,7 +360,7 @@ static int pata_s3c_wait_after_reset(struct ata_link *link,
|
|||
/*
|
||||
* pata_s3c_bus_softreset - PATA device software reset
|
||||
*/
|
||||
static unsigned int pata_s3c_bus_softreset(struct ata_port *ap,
|
||||
static int pata_s3c_bus_softreset(struct ata_port *ap,
|
||||
unsigned long deadline)
|
||||
{
|
||||
struct ata_ioports *ioaddr = &ap->ioaddr;
|
||||
|
|
|
|||
|
|
@ -585,7 +585,7 @@ static int scc_wait_after_reset(struct ata_link *link, unsigned int devmask,
|
|||
* Note: Original code is ata_bus_softreset().
|
||||
*/
|
||||
|
||||
static unsigned int scc_bus_softreset(struct ata_port *ap, unsigned int devmask,
|
||||
static int scc_bus_softreset(struct ata_port *ap, unsigned int devmask,
|
||||
unsigned long deadline)
|
||||
{
|
||||
struct ata_ioports *ioaddr = &ap->ioaddr;
|
||||
|
|
@ -599,9 +599,7 @@ static unsigned int scc_bus_softreset(struct ata_port *ap, unsigned int devmask,
|
|||
udelay(20);
|
||||
out_be32(ioaddr->ctl_addr, ap->ctl);
|
||||
|
||||
scc_wait_after_reset(&ap->link, devmask, deadline);
|
||||
|
||||
return 0;
|
||||
return scc_wait_after_reset(&ap->link, devmask, deadline);
|
||||
}
|
||||
|
||||
/**
|
||||
|
|
@ -618,7 +616,8 @@ static int scc_softreset(struct ata_link *link, unsigned int *classes,
|
|||
{
|
||||
struct ata_port *ap = link->ap;
|
||||
unsigned int slave_possible = ap->flags & ATA_FLAG_SLAVE_POSS;
|
||||
unsigned int devmask = 0, err_mask;
|
||||
unsigned int devmask = 0;
|
||||
int rc;
|
||||
u8 err;
|
||||
|
||||
DPRINTK("ENTER\n");
|
||||
|
|
@ -634,9 +633,9 @@ static int scc_softreset(struct ata_link *link, unsigned int *classes,
|
|||
|
||||
/* issue bus reset */
|
||||
DPRINTK("about to softreset, devmask=%x\n", devmask);
|
||||
err_mask = scc_bus_softreset(ap, devmask, deadline);
|
||||
if (err_mask) {
|
||||
ata_port_err(ap, "SRST failed (err_mask=0x%x)\n", err_mask);
|
||||
rc = scc_bus_softreset(ap, devmask, deadline);
|
||||
if (rc) {
|
||||
ata_port_err(ap, "SRST failed (err_mask=0x%x)\n", rc);
|
||||
return -EIO;
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -662,7 +662,7 @@ static int arm_ccn_pmu_event_init(struct perf_event *event)
|
|||
}
|
||||
if (e->num_vcs && vc >= e->num_vcs) {
|
||||
dev_warn(ccn->dev, "Invalid vc %d for node/XP %d!\n",
|
||||
port, node_xp);
|
||||
vc, node_xp);
|
||||
return -EINVAL;
|
||||
}
|
||||
valid = 1;
|
||||
|
|
|
|||
|
|
@ -481,7 +481,7 @@ EXPORT_SYMBOL_GPL(efivar_entry_remove);
|
|||
*/
|
||||
static void efivar_entry_list_del_unlock(struct efivar_entry *entry)
|
||||
{
|
||||
WARN_ON(!spin_is_locked(&__efivars->lock));
|
||||
lockdep_assert_held(&__efivars->lock);
|
||||
|
||||
list_del(&entry->list);
|
||||
spin_unlock_irq(&__efivars->lock);
|
||||
|
|
@ -507,7 +507,7 @@ int __efivar_entry_delete(struct efivar_entry *entry)
|
|||
const struct efivar_operations *ops = __efivars->ops;
|
||||
efi_status_t status;
|
||||
|
||||
WARN_ON(!spin_is_locked(&__efivars->lock));
|
||||
lockdep_assert_held(&__efivars->lock);
|
||||
|
||||
status = ops->set_variable(entry->var.VariableName,
|
||||
&entry->var.VendorGuid,
|
||||
|
|
@ -667,7 +667,7 @@ struct efivar_entry *efivar_entry_find(efi_char16_t *name, efi_guid_t guid,
|
|||
int strsize1, strsize2;
|
||||
bool found = false;
|
||||
|
||||
WARN_ON(!spin_is_locked(&__efivars->lock));
|
||||
lockdep_assert_held(&__efivars->lock);
|
||||
|
||||
list_for_each_entry_safe(entry, n, head, list) {
|
||||
strsize1 = ucs2_strsize(name, 1024);
|
||||
|
|
@ -739,7 +739,7 @@ int __efivar_entry_get(struct efivar_entry *entry, u32 *attributes,
|
|||
const struct efivar_operations *ops = __efivars->ops;
|
||||
efi_status_t status;
|
||||
|
||||
WARN_ON(!spin_is_locked(&__efivars->lock));
|
||||
lockdep_assert_held(&__efivars->lock);
|
||||
|
||||
status = ops->get_variable(entry->var.VariableName,
|
||||
&entry->var.VendorGuid,
|
||||
|
|
|
|||
|
|
@ -90,7 +90,7 @@ struct gpio_desc *__must_check __devm_gpiod_get_index(struct device *dev,
|
|||
struct gpio_desc **dr;
|
||||
struct gpio_desc *desc;
|
||||
|
||||
dr = devres_alloc(devm_gpiod_release, sizeof(struct gpiod_desc *),
|
||||
dr = devres_alloc(devm_gpiod_release, sizeof(struct gpio_desc *),
|
||||
GFP_KERNEL);
|
||||
if (!dr)
|
||||
return ERR_PTR(-ENOMEM);
|
||||
|
|
|
|||
|
|
@ -407,9 +407,27 @@ static int lp_gpio_runtime_resume(struct device *dev)
|
|||
return 0;
|
||||
}
|
||||
|
||||
static int lp_gpio_resume(struct device *dev)
|
||||
{
|
||||
struct platform_device *pdev = to_platform_device(dev);
|
||||
struct lp_gpio *lg = platform_get_drvdata(pdev);
|
||||
unsigned long reg;
|
||||
int i;
|
||||
|
||||
/* on some hardware suspend clears input sensing, re-enable it here */
|
||||
for (i = 0; i < lg->chip.ngpio; i++) {
|
||||
if (gpiochip_is_requested(&lg->chip, i) != NULL) {
|
||||
reg = lp_gpio_reg(&lg->chip, i, LP_CONFIG2);
|
||||
outl(inl(reg) & ~GPINDIS_BIT, reg);
|
||||
}
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
|
||||
static const struct dev_pm_ops lp_gpio_pm_ops = {
|
||||
.runtime_suspend = lp_gpio_runtime_suspend,
|
||||
.runtime_resume = lp_gpio_runtime_resume,
|
||||
.resume = lp_gpio_resume,
|
||||
};
|
||||
|
||||
static const struct acpi_device_id lynxpoint_gpio_acpi_match[] = {
|
||||
|
|
|
|||
|
|
@ -95,6 +95,9 @@ struct zynq_gpio {
|
|||
struct clk *clk;
|
||||
};
|
||||
|
||||
static struct irq_chip zynq_gpio_level_irqchip;
|
||||
static struct irq_chip zynq_gpio_edge_irqchip;
|
||||
|
||||
/**
|
||||
* zynq_gpio_get_bank_pin - Get the bank number and pin number within that bank
|
||||
* for a given pin in the GPIO device
|
||||
|
|
@ -410,6 +413,15 @@ static int zynq_gpio_set_irq_type(struct irq_data *irq_data, unsigned int type)
|
|||
gpio->base_addr + ZYNQ_GPIO_INTPOL_OFFSET(bank_num));
|
||||
writel_relaxed(int_any,
|
||||
gpio->base_addr + ZYNQ_GPIO_INTANY_OFFSET(bank_num));
|
||||
|
||||
if (type & IRQ_TYPE_LEVEL_MASK) {
|
||||
__irq_set_chip_handler_name_locked(irq_data->irq,
|
||||
&zynq_gpio_level_irqchip, handle_fasteoi_irq, NULL);
|
||||
} else {
|
||||
__irq_set_chip_handler_name_locked(irq_data->irq,
|
||||
&zynq_gpio_edge_irqchip, handle_level_irq, NULL);
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
|
@ -424,9 +436,21 @@ static int zynq_gpio_set_wake(struct irq_data *data, unsigned int on)
|
|||
}
|
||||
|
||||
/* irq chip descriptor */
|
||||
static struct irq_chip zynq_gpio_irqchip = {
|
||||
static struct irq_chip zynq_gpio_level_irqchip = {
|
||||
.name = DRIVER_NAME,
|
||||
.irq_enable = zynq_gpio_irq_enable,
|
||||
.irq_eoi = zynq_gpio_irq_ack,
|
||||
.irq_mask = zynq_gpio_irq_mask,
|
||||
.irq_unmask = zynq_gpio_irq_unmask,
|
||||
.irq_set_type = zynq_gpio_set_irq_type,
|
||||
.irq_set_wake = zynq_gpio_set_wake,
|
||||
.flags = IRQCHIP_EOI_THREADED | IRQCHIP_EOI_IF_HANDLED,
|
||||
};
|
||||
|
||||
static struct irq_chip zynq_gpio_edge_irqchip = {
|
||||
.name = DRIVER_NAME,
|
||||
.irq_enable = zynq_gpio_irq_enable,
|
||||
.irq_ack = zynq_gpio_irq_ack,
|
||||
.irq_mask = zynq_gpio_irq_mask,
|
||||
.irq_unmask = zynq_gpio_irq_unmask,
|
||||
.irq_set_type = zynq_gpio_set_irq_type,
|
||||
|
|
@ -469,10 +493,6 @@ static void zynq_gpio_irqhandler(unsigned int irq, struct irq_desc *desc)
|
|||
offset);
|
||||
generic_handle_irq(gpio_irq);
|
||||
}
|
||||
|
||||
/* clear IRQ in HW */
|
||||
writel_relaxed(int_sts, gpio->base_addr +
|
||||
ZYNQ_GPIO_INTSTS_OFFSET(bank_num));
|
||||
}
|
||||
}
|
||||
|
||||
|
|
@ -610,14 +630,14 @@ static int zynq_gpio_probe(struct platform_device *pdev)
|
|||
writel_relaxed(ZYNQ_GPIO_IXR_DISABLE_ALL, gpio->base_addr +
|
||||
ZYNQ_GPIO_INTDIS_OFFSET(bank_num));
|
||||
|
||||
ret = gpiochip_irqchip_add(chip, &zynq_gpio_irqchip, 0,
|
||||
handle_simple_irq, IRQ_TYPE_NONE);
|
||||
ret = gpiochip_irqchip_add(chip, &zynq_gpio_edge_irqchip, 0,
|
||||
handle_level_irq, IRQ_TYPE_NONE);
|
||||
if (ret) {
|
||||
dev_err(&pdev->dev, "Failed to add irq chip\n");
|
||||
goto err_rm_gpiochip;
|
||||
}
|
||||
|
||||
gpiochip_set_chained_irqchip(chip, &zynq_gpio_irqchip, irq,
|
||||
gpiochip_set_chained_irqchip(chip, &zynq_gpio_edge_irqchip, irq,
|
||||
zynq_gpio_irqhandler);
|
||||
|
||||
pm_runtime_set_active(&pdev->dev);
|
||||
|
|
|
|||
|
|
@ -307,7 +307,5 @@ void of_gpiochip_add(struct gpio_chip *chip)
|
|||
void of_gpiochip_remove(struct gpio_chip *chip)
|
||||
{
|
||||
gpiochip_remove_pin_ranges(chip);
|
||||
|
||||
if (chip->of_node)
|
||||
of_node_put(chip->of_node);
|
||||
}
|
||||
|
|
|
|||
|
|
@ -494,6 +494,36 @@ bool i915_semaphore_is_enabled(struct drm_device *dev)
|
|||
return true;
|
||||
}
|
||||
|
||||
void intel_hpd_cancel_work(struct drm_i915_private *dev_priv)
|
||||
{
|
||||
spin_lock_irq(&dev_priv->irq_lock);
|
||||
|
||||
dev_priv->long_hpd_port_mask = 0;
|
||||
dev_priv->short_hpd_port_mask = 0;
|
||||
dev_priv->hpd_event_bits = 0;
|
||||
|
||||
spin_unlock_irq(&dev_priv->irq_lock);
|
||||
|
||||
cancel_work_sync(&dev_priv->dig_port_work);
|
||||
cancel_work_sync(&dev_priv->hotplug_work);
|
||||
cancel_delayed_work_sync(&dev_priv->hotplug_reenable_work);
|
||||
}
|
||||
|
||||
static void intel_suspend_encoders(struct drm_i915_private *dev_priv)
|
||||
{
|
||||
struct drm_device *dev = dev_priv->dev;
|
||||
struct drm_encoder *encoder;
|
||||
|
||||
drm_modeset_lock_all(dev);
|
||||
list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
|
||||
struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
|
||||
|
||||
if (intel_encoder->suspend)
|
||||
intel_encoder->suspend(intel_encoder);
|
||||
}
|
||||
drm_modeset_unlock_all(dev);
|
||||
}
|
||||
|
||||
static int i915_drm_freeze(struct drm_device *dev)
|
||||
{
|
||||
struct drm_i915_private *dev_priv = dev->dev_private;
|
||||
|
|
@ -538,6 +568,9 @@ static int i915_drm_freeze(struct drm_device *dev)
|
|||
flush_delayed_work(&dev_priv->rps.delayed_resume_work);
|
||||
|
||||
intel_runtime_pm_disable_interrupts(dev);
|
||||
intel_hpd_cancel_work(dev_priv);
|
||||
|
||||
intel_suspend_encoders(dev_priv);
|
||||
|
||||
intel_suspend_gt_powersave(dev);
|
||||
|
||||
|
|
|
|||
|
|
@ -1458,7 +1458,7 @@ struct drm_i915_private {
|
|||
} hpd_mark;
|
||||
} hpd_stats[HPD_NUM_PINS];
|
||||
u32 hpd_event_bits;
|
||||
struct timer_list hotplug_reenable_timer;
|
||||
struct delayed_work hotplug_reenable_work;
|
||||
|
||||
struct i915_fbc fbc;
|
||||
struct i915_drrs drrs;
|
||||
|
|
@ -2178,6 +2178,7 @@ extern unsigned long i915_mch_val(struct drm_i915_private *dev_priv);
|
|||
extern unsigned long i915_gfx_val(struct drm_i915_private *dev_priv);
|
||||
extern void i915_update_gfx_val(struct drm_i915_private *dev_priv);
|
||||
int vlv_force_gfx_clock(struct drm_i915_private *dev_priv, bool on);
|
||||
void intel_hpd_cancel_work(struct drm_i915_private *dev_priv);
|
||||
|
||||
extern void intel_console_resume(struct work_struct *work);
|
||||
|
||||
|
|
|
|||
|
|
@ -1189,8 +1189,8 @@ static void i915_hotplug_work_func(struct work_struct *work)
|
|||
* some connectors */
|
||||
if (hpd_disabled) {
|
||||
drm_kms_helper_poll_enable(dev);
|
||||
mod_timer(&dev_priv->hotplug_reenable_timer,
|
||||
jiffies + msecs_to_jiffies(I915_REENABLE_HOTPLUG_DELAY));
|
||||
mod_delayed_work(system_wq, &dev_priv->hotplug_reenable_work,
|
||||
msecs_to_jiffies(I915_REENABLE_HOTPLUG_DELAY));
|
||||
}
|
||||
|
||||
spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
|
||||
|
|
@ -1213,11 +1213,6 @@ static void i915_hotplug_work_func(struct work_struct *work)
|
|||
drm_kms_helper_hotplug_event(dev);
|
||||
}
|
||||
|
||||
static void intel_hpd_irq_uninstall(struct drm_i915_private *dev_priv)
|
||||
{
|
||||
del_timer_sync(&dev_priv->hotplug_reenable_timer);
|
||||
}
|
||||
|
||||
static void ironlake_rps_change_irq_handler(struct drm_device *dev)
|
||||
{
|
||||
struct drm_i915_private *dev_priv = dev->dev_private;
|
||||
|
|
@ -3892,8 +3887,6 @@ static void gen8_irq_uninstall(struct drm_device *dev)
|
|||
if (!dev_priv)
|
||||
return;
|
||||
|
||||
intel_hpd_irq_uninstall(dev_priv);
|
||||
|
||||
gen8_irq_reset(dev);
|
||||
}
|
||||
|
||||
|
|
@ -3908,8 +3901,6 @@ static void valleyview_irq_uninstall(struct drm_device *dev)
|
|||
|
||||
I915_WRITE(VLV_MASTER_IER, 0);
|
||||
|
||||
intel_hpd_irq_uninstall(dev_priv);
|
||||
|
||||
for_each_pipe(pipe)
|
||||
I915_WRITE(PIPESTAT(pipe), 0xffff);
|
||||
|
||||
|
|
@ -3988,8 +3979,6 @@ static void ironlake_irq_uninstall(struct drm_device *dev)
|
|||
if (!dev_priv)
|
||||
return;
|
||||
|
||||
intel_hpd_irq_uninstall(dev_priv);
|
||||
|
||||
ironlake_irq_reset(dev);
|
||||
}
|
||||
|
||||
|
|
@ -4360,8 +4349,6 @@ static void i915_irq_uninstall(struct drm_device * dev)
|
|||
struct drm_i915_private *dev_priv = dev->dev_private;
|
||||
int pipe;
|
||||
|
||||
intel_hpd_irq_uninstall(dev_priv);
|
||||
|
||||
if (I915_HAS_HOTPLUG(dev)) {
|
||||
I915_WRITE(PORT_HOTPLUG_EN, 0);
|
||||
I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
|
||||
|
|
@ -4598,8 +4585,6 @@ static void i965_irq_uninstall(struct drm_device * dev)
|
|||
if (!dev_priv)
|
||||
return;
|
||||
|
||||
intel_hpd_irq_uninstall(dev_priv);
|
||||
|
||||
I915_WRITE(PORT_HOTPLUG_EN, 0);
|
||||
I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
|
||||
|
||||
|
|
@ -4615,14 +4600,18 @@ static void i965_irq_uninstall(struct drm_device * dev)
|
|||
I915_WRITE(IIR, I915_READ(IIR));
|
||||
}
|
||||
|
||||
static void intel_hpd_irq_reenable(unsigned long data)
|
||||
static void intel_hpd_irq_reenable(struct work_struct *work)
|
||||
{
|
||||
struct drm_i915_private *dev_priv = (struct drm_i915_private *)data;
|
||||
struct drm_i915_private *dev_priv =
|
||||
container_of(work, typeof(*dev_priv),
|
||||
hotplug_reenable_work.work);
|
||||
struct drm_device *dev = dev_priv->dev;
|
||||
struct drm_mode_config *mode_config = &dev->mode_config;
|
||||
unsigned long irqflags;
|
||||
int i;
|
||||
|
||||
intel_runtime_pm_get(dev_priv);
|
||||
|
||||
spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
|
||||
for (i = (HPD_NONE + 1); i < HPD_NUM_PINS; i++) {
|
||||
struct drm_connector *connector;
|
||||
|
|
@ -4648,6 +4637,8 @@ static void intel_hpd_irq_reenable(unsigned long data)
|
|||
if (dev_priv->display.hpd_irq_setup)
|
||||
dev_priv->display.hpd_irq_setup(dev);
|
||||
spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
|
||||
|
||||
intel_runtime_pm_put(dev_priv);
|
||||
}
|
||||
|
||||
void intel_irq_init(struct drm_device *dev)
|
||||
|
|
@ -4670,8 +4661,8 @@ void intel_irq_init(struct drm_device *dev)
|
|||
setup_timer(&dev_priv->gpu_error.hangcheck_timer,
|
||||
i915_hangcheck_elapsed,
|
||||
(unsigned long) dev);
|
||||
setup_timer(&dev_priv->hotplug_reenable_timer, intel_hpd_irq_reenable,
|
||||
(unsigned long) dev_priv);
|
||||
INIT_DELAYED_WORK(&dev_priv->hotplug_reenable_work,
|
||||
intel_hpd_irq_reenable);
|
||||
|
||||
pm_qos_add_request(&dev_priv->pm_qos, PM_QOS_CPU_DMA_LATENCY, PM_QOS_DEFAULT_VALUE);
|
||||
|
||||
|
|
|
|||
|
|
@ -699,16 +699,21 @@ intel_crt_detect(struct drm_connector *connector, bool force)
|
|||
goto out;
|
||||
}
|
||||
|
||||
drm_modeset_acquire_init(&ctx, 0);
|
||||
|
||||
/* for pre-945g platforms use load detect */
|
||||
if (intel_get_load_detect_pipe(connector, NULL, &tmp, &ctx)) {
|
||||
if (intel_crt_detect_ddc(connector))
|
||||
status = connector_status_connected;
|
||||
else
|
||||
status = intel_crt_load_detect(crt);
|
||||
intel_release_load_detect_pipe(connector, &tmp, &ctx);
|
||||
intel_release_load_detect_pipe(connector, &tmp);
|
||||
} else
|
||||
status = connector_status_unknown;
|
||||
|
||||
drm_modeset_drop_locks(&ctx);
|
||||
drm_modeset_acquire_fini(&ctx);
|
||||
|
||||
out:
|
||||
intel_display_power_put(dev_priv, power_domain);
|
||||
return status;
|
||||
|
|
|
|||
|
|
@ -8462,8 +8462,6 @@ bool intel_get_load_detect_pipe(struct drm_connector *connector,
|
|||
connector->base.id, connector->name,
|
||||
encoder->base.id, encoder->name);
|
||||
|
||||
drm_modeset_acquire_init(ctx, 0);
|
||||
|
||||
retry:
|
||||
ret = drm_modeset_lock(&config->connection_mutex, ctx);
|
||||
if (ret)
|
||||
|
|
@ -8502,11 +8500,15 @@ retry:
|
|||
i++;
|
||||
if (!(encoder->possible_crtcs & (1 << i)))
|
||||
continue;
|
||||
if (!possible_crtc->enabled) {
|
||||
if (possible_crtc->enabled)
|
||||
continue;
|
||||
/* This can occur when applying the pipe A quirk on resume. */
|
||||
if (to_intel_crtc(possible_crtc)->new_enabled)
|
||||
continue;
|
||||
|
||||
crtc = possible_crtc;
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
/*
|
||||
* If we didn't find an unused CRTC, don't use any.
|
||||
|
|
@ -8574,15 +8576,11 @@ fail_unlock:
|
|||
goto retry;
|
||||
}
|
||||
|
||||
drm_modeset_drop_locks(ctx);
|
||||
drm_modeset_acquire_fini(ctx);
|
||||
|
||||
return false;
|
||||
}
|
||||
|
||||
void intel_release_load_detect_pipe(struct drm_connector *connector,
|
||||
struct intel_load_detect_pipe *old,
|
||||
struct drm_modeset_acquire_ctx *ctx)
|
||||
struct intel_load_detect_pipe *old)
|
||||
{
|
||||
struct intel_encoder *intel_encoder =
|
||||
intel_attached_encoder(connector);
|
||||
|
|
@ -8606,17 +8604,12 @@ void intel_release_load_detect_pipe(struct drm_connector *connector,
|
|||
drm_framebuffer_unreference(old->release_fb);
|
||||
}
|
||||
|
||||
goto unlock;
|
||||
return;
|
||||
}
|
||||
|
||||
/* Switch crtc and encoder back off if necessary */
|
||||
if (old->dpms_mode != DRM_MODE_DPMS_ON)
|
||||
connector->funcs->dpms(connector, old->dpms_mode);
|
||||
|
||||
unlock:
|
||||
drm_modeset_drop_locks(ctx);
|
||||
drm_modeset_acquire_fini(ctx);
|
||||
}
|
||||
|
||||
static int i9xx_pll_refclk(struct drm_device *dev,
|
||||
|
|
@ -11700,8 +11693,8 @@ intel_cursor_plane_update(struct drm_plane *plane, struct drm_crtc *crtc,
|
|||
};
|
||||
const struct drm_rect clip = {
|
||||
/* integer pixels */
|
||||
.x2 = intel_crtc->config.pipe_src_w,
|
||||
.y2 = intel_crtc->config.pipe_src_h,
|
||||
.x2 = intel_crtc->active ? intel_crtc->config.pipe_src_w : 0,
|
||||
.y2 = intel_crtc->active ? intel_crtc->config.pipe_src_h : 0,
|
||||
};
|
||||
bool visible;
|
||||
int ret;
|
||||
|
|
@ -12659,7 +12652,7 @@ static void intel_enable_pipe_a(struct drm_device *dev)
|
|||
struct intel_connector *connector;
|
||||
struct drm_connector *crt = NULL;
|
||||
struct intel_load_detect_pipe load_detect_temp;
|
||||
struct drm_modeset_acquire_ctx ctx;
|
||||
struct drm_modeset_acquire_ctx *ctx = dev->mode_config.acquire_ctx;
|
||||
|
||||
/* We can't just switch on the pipe A, we need to set things up with a
|
||||
* proper mode and output configuration. As a gross hack, enable pipe A
|
||||
|
|
@ -12676,10 +12669,8 @@ static void intel_enable_pipe_a(struct drm_device *dev)
|
|||
if (!crt)
|
||||
return;
|
||||
|
||||
if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp, &ctx))
|
||||
intel_release_load_detect_pipe(crt, &load_detect_temp, &ctx);
|
||||
|
||||
|
||||
if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp, ctx))
|
||||
intel_release_load_detect_pipe(crt, &load_detect_temp);
|
||||
}
|
||||
|
||||
static bool
|
||||
|
|
@ -13112,7 +13103,7 @@ void intel_modeset_cleanup(struct drm_device *dev)
|
|||
* experience fancy races otherwise.
|
||||
*/
|
||||
drm_irq_uninstall(dev);
|
||||
cancel_work_sync(&dev_priv->hotplug_work);
|
||||
intel_hpd_cancel_work(dev_priv);
|
||||
dev_priv->pm._irqs_disabled = true;
|
||||
|
||||
/*
|
||||
|
|
|
|||
|
|
@ -3553,6 +3553,9 @@ intel_dp_check_link_status(struct intel_dp *intel_dp)
|
|||
if (WARN_ON(!intel_encoder->base.crtc))
|
||||
return;
|
||||
|
||||
if (!to_intel_crtc(intel_encoder->base.crtc)->active)
|
||||
return;
|
||||
|
||||
/* Try to read receiver status if the link appears to be up */
|
||||
if (!intel_dp_get_link_status(intel_dp, link_status)) {
|
||||
return;
|
||||
|
|
@ -4003,6 +4006,16 @@ void intel_dp_encoder_destroy(struct drm_encoder *encoder)
|
|||
kfree(intel_dig_port);
|
||||
}
|
||||
|
||||
static void intel_dp_encoder_suspend(struct intel_encoder *intel_encoder)
|
||||
{
|
||||
struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
|
||||
|
||||
if (!is_edp(intel_dp))
|
||||
return;
|
||||
|
||||
edp_panel_vdd_off_sync(intel_dp);
|
||||
}
|
||||
|
||||
static void intel_dp_encoder_reset(struct drm_encoder *encoder)
|
||||
{
|
||||
intel_edp_panel_vdd_sanitize(to_intel_encoder(encoder));
|
||||
|
|
@ -4037,15 +4050,21 @@ bool
|
|||
intel_dp_hpd_pulse(struct intel_digital_port *intel_dig_port, bool long_hpd)
|
||||
{
|
||||
struct intel_dp *intel_dp = &intel_dig_port->dp;
|
||||
struct intel_encoder *intel_encoder = &intel_dig_port->base;
|
||||
struct drm_device *dev = intel_dig_port->base.base.dev;
|
||||
struct drm_i915_private *dev_priv = dev->dev_private;
|
||||
int ret;
|
||||
enum intel_display_power_domain power_domain;
|
||||
bool ret = true;
|
||||
|
||||
if (intel_dig_port->base.type != INTEL_OUTPUT_EDP)
|
||||
intel_dig_port->base.type = INTEL_OUTPUT_DISPLAYPORT;
|
||||
|
||||
DRM_DEBUG_KMS("got hpd irq on port %d - %s\n", intel_dig_port->port,
|
||||
long_hpd ? "long" : "short");
|
||||
|
||||
power_domain = intel_display_port_power_domain(intel_encoder);
|
||||
intel_display_power_get(dev_priv, power_domain);
|
||||
|
||||
if (long_hpd) {
|
||||
if (!ibx_digital_port_connected(dev_priv, intel_dig_port))
|
||||
goto mst_fail;
|
||||
|
|
@ -4061,8 +4080,7 @@ intel_dp_hpd_pulse(struct intel_digital_port *intel_dig_port, bool long_hpd)
|
|||
|
||||
} else {
|
||||
if (intel_dp->is_mst) {
|
||||
ret = intel_dp_check_mst_status(intel_dp);
|
||||
if (ret == -EINVAL)
|
||||
if (intel_dp_check_mst_status(intel_dp) == -EINVAL)
|
||||
goto mst_fail;
|
||||
}
|
||||
|
||||
|
|
@ -4076,7 +4094,8 @@ intel_dp_hpd_pulse(struct intel_digital_port *intel_dig_port, bool long_hpd)
|
|||
drm_modeset_unlock(&dev->mode_config.connection_mutex);
|
||||
}
|
||||
}
|
||||
return false;
|
||||
ret = false;
|
||||
goto put_power;
|
||||
mst_fail:
|
||||
/* if we were in MST mode, and device is not there get out of MST mode */
|
||||
if (intel_dp->is_mst) {
|
||||
|
|
@ -4084,7 +4103,10 @@ mst_fail:
|
|||
intel_dp->is_mst = false;
|
||||
drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr, intel_dp->is_mst);
|
||||
}
|
||||
return true;
|
||||
put_power:
|
||||
intel_display_power_put(dev_priv, power_domain);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
/* Return which DP Port should be selected for Transcoder DP control */
|
||||
|
|
@ -4722,6 +4744,7 @@ intel_dp_init(struct drm_device *dev, int output_reg, enum port port)
|
|||
intel_encoder->disable = intel_disable_dp;
|
||||
intel_encoder->get_hw_state = intel_dp_get_hw_state;
|
||||
intel_encoder->get_config = intel_dp_get_config;
|
||||
intel_encoder->suspend = intel_dp_encoder_suspend;
|
||||
if (IS_CHERRYVIEW(dev)) {
|
||||
intel_encoder->pre_pll_enable = chv_dp_pre_pll_enable;
|
||||
intel_encoder->pre_enable = chv_pre_enable_dp;
|
||||
|
|
|
|||
|
|
@ -153,6 +153,12 @@ struct intel_encoder {
|
|||
* be set correctly before calling this function. */
|
||||
void (*get_config)(struct intel_encoder *,
|
||||
struct intel_crtc_config *pipe_config);
|
||||
/*
|
||||
* Called during system suspend after all pending requests for the
|
||||
* encoder are flushed (for example for DP AUX transactions) and
|
||||
* device interrupts are disabled.
|
||||
*/
|
||||
void (*suspend)(struct intel_encoder *);
|
||||
int crtc_mask;
|
||||
enum hpd_pin hpd_pin;
|
||||
};
|
||||
|
|
@ -830,8 +836,7 @@ bool intel_get_load_detect_pipe(struct drm_connector *connector,
|
|||
struct intel_load_detect_pipe *old,
|
||||
struct drm_modeset_acquire_ctx *ctx);
|
||||
void intel_release_load_detect_pipe(struct drm_connector *connector,
|
||||
struct intel_load_detect_pipe *old,
|
||||
struct drm_modeset_acquire_ctx *ctx);
|
||||
struct intel_load_detect_pipe *old);
|
||||
int intel_pin_and_fence_fb_obj(struct drm_device *dev,
|
||||
struct drm_i915_gem_object *obj,
|
||||
struct intel_engine_cs *pipelined);
|
||||
|
|
|
|||
|
|
@ -1323,11 +1323,16 @@ intel_tv_detect(struct drm_connector *connector, bool force)
|
|||
struct intel_load_detect_pipe tmp;
|
||||
struct drm_modeset_acquire_ctx ctx;
|
||||
|
||||
drm_modeset_acquire_init(&ctx, 0);
|
||||
|
||||
if (intel_get_load_detect_pipe(connector, &mode, &tmp, &ctx)) {
|
||||
type = intel_tv_detect_type(intel_tv, connector);
|
||||
intel_release_load_detect_pipe(connector, &tmp, &ctx);
|
||||
intel_release_load_detect_pipe(connector, &tmp);
|
||||
} else
|
||||
return connector_status_unknown;
|
||||
|
||||
drm_modeset_drop_locks(&ctx);
|
||||
drm_modeset_acquire_fini(&ctx);
|
||||
} else
|
||||
return connector->status;
|
||||
|
||||
|
|
|
|||
|
|
@ -76,7 +76,7 @@ radeon-y += radeon_device.o radeon_asic.o radeon_kms.o \
|
|||
evergreen.o evergreen_cs.o evergreen_blit_shaders.o \
|
||||
evergreen_hdmi.o radeon_trace_points.o ni.o cayman_blit_shaders.o \
|
||||
atombios_encoders.o radeon_semaphore.o radeon_sa.o atombios_i2c.o si.o \
|
||||
si_blit_shaders.o radeon_prime.o radeon_uvd.o cik.o cik_blit_shaders.o \
|
||||
si_blit_shaders.o radeon_prime.o cik.o cik_blit_shaders.o \
|
||||
r600_dpm.o rs780_dpm.o rv6xx_dpm.o rv770_dpm.o rv730_dpm.o rv740_dpm.o \
|
||||
rv770_smc.o cypress_dpm.o btc_dpm.o sumo_dpm.o sumo_smc.o trinity_dpm.o \
|
||||
trinity_smc.o ni_dpm.o si_smc.o si_dpm.o kv_smc.o kv_dpm.o ci_smc.o \
|
||||
|
|
|
|||
|
|
@ -869,6 +869,9 @@ static int ci_set_thermal_temperature_range(struct radeon_device *rdev,
|
|||
WREG32_SMC(CG_THERMAL_CTRL, tmp);
|
||||
#endif
|
||||
|
||||
rdev->pm.dpm.thermal.min_temp = low_temp;
|
||||
rdev->pm.dpm.thermal.max_temp = high_temp;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -3483,7 +3483,7 @@ static void cik_gpu_init(struct radeon_device *rdev)
|
|||
u32 mc_shared_chmap, mc_arb_ramcfg;
|
||||
u32 hdp_host_path_cntl;
|
||||
u32 tmp;
|
||||
int i, j, k;
|
||||
int i, j;
|
||||
|
||||
switch (rdev->family) {
|
||||
case CHIP_BONAIRE:
|
||||
|
|
@ -3544,6 +3544,7 @@ static void cik_gpu_init(struct radeon_device *rdev)
|
|||
(rdev->pdev->device == 0x130B) ||
|
||||
(rdev->pdev->device == 0x130E) ||
|
||||
(rdev->pdev->device == 0x1315) ||
|
||||
(rdev->pdev->device == 0x1318) ||
|
||||
(rdev->pdev->device == 0x131B)) {
|
||||
rdev->config.cik.max_cu_per_sh = 4;
|
||||
rdev->config.cik.max_backends_per_se = 1;
|
||||
|
|
@ -3672,14 +3673,13 @@ static void cik_gpu_init(struct radeon_device *rdev)
|
|||
rdev->config.cik.max_sh_per_se,
|
||||
rdev->config.cik.max_backends_per_se);
|
||||
|
||||
rdev->config.cik.active_cus = 0;
|
||||
for (i = 0; i < rdev->config.cik.max_shader_engines; i++) {
|
||||
for (j = 0; j < rdev->config.cik.max_sh_per_se; j++) {
|
||||
for (k = 0; k < rdev->config.cik.max_cu_per_sh; k++) {
|
||||
rdev->config.cik.active_cus +=
|
||||
hweight32(cik_get_cu_active_bitmap(rdev, i, j));
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
/* set HW defaults for 3D engine */
|
||||
WREG32(CP_MEQ_THRESHOLDS, MEQ1_START(0x30) | MEQ2_START(0x60));
|
||||
|
|
@ -3801,7 +3801,7 @@ int cik_ring_test(struct radeon_device *rdev, struct radeon_ring *ring)
|
|||
radeon_ring_write(ring, PACKET3(PACKET3_SET_UCONFIG_REG, 1));
|
||||
radeon_ring_write(ring, ((scratch - PACKET3_SET_UCONFIG_REG_START) >> 2));
|
||||
radeon_ring_write(ring, 0xDEADBEEF);
|
||||
radeon_ring_unlock_commit(rdev, ring);
|
||||
radeon_ring_unlock_commit(rdev, ring, false);
|
||||
|
||||
for (i = 0; i < rdev->usec_timeout; i++) {
|
||||
tmp = RREG32(scratch);
|
||||
|
|
@ -3920,6 +3920,17 @@ void cik_fence_compute_ring_emit(struct radeon_device *rdev,
|
|||
radeon_ring_write(ring, 0);
|
||||
}
|
||||
|
||||
/**
|
||||
* cik_semaphore_ring_emit - emit a semaphore on the CP ring
|
||||
*
|
||||
* @rdev: radeon_device pointer
|
||||
* @ring: radeon ring buffer object
|
||||
* @semaphore: radeon semaphore object
|
||||
* @emit_wait: Is this a sempahore wait?
|
||||
*
|
||||
* Emits a semaphore signal/wait packet to the CP ring and prevents the PFP
|
||||
* from running ahead of semaphore waits.
|
||||
*/
|
||||
bool cik_semaphore_ring_emit(struct radeon_device *rdev,
|
||||
struct radeon_ring *ring,
|
||||
struct radeon_semaphore *semaphore,
|
||||
|
|
@ -3932,6 +3943,12 @@ bool cik_semaphore_ring_emit(struct radeon_device *rdev,
|
|||
radeon_ring_write(ring, lower_32_bits(addr));
|
||||
radeon_ring_write(ring, (upper_32_bits(addr) & 0xffff) | sel);
|
||||
|
||||
if (emit_wait && ring->idx == RADEON_RING_TYPE_GFX_INDEX) {
|
||||
/* Prevent the PFP from running ahead of the semaphore wait */
|
||||
radeon_ring_write(ring, PACKET3(PACKET3_PFP_SYNC_ME, 0));
|
||||
radeon_ring_write(ring, 0x0);
|
||||
}
|
||||
|
||||
return true;
|
||||
}
|
||||
|
||||
|
|
@ -4004,7 +4021,7 @@ int cik_copy_cpdma(struct radeon_device *rdev,
|
|||
return r;
|
||||
}
|
||||
|
||||
radeon_ring_unlock_commit(rdev, ring);
|
||||
radeon_ring_unlock_commit(rdev, ring, false);
|
||||
radeon_semaphore_free(rdev, &sem, *fence);
|
||||
|
||||
return r;
|
||||
|
|
@ -4103,7 +4120,7 @@ int cik_ib_test(struct radeon_device *rdev, struct radeon_ring *ring)
|
|||
ib.ptr[1] = ((scratch - PACKET3_SET_UCONFIG_REG_START) >> 2);
|
||||
ib.ptr[2] = 0xDEADBEEF;
|
||||
ib.length_dw = 3;
|
||||
r = radeon_ib_schedule(rdev, &ib, NULL);
|
||||
r = radeon_ib_schedule(rdev, &ib, NULL, false);
|
||||
if (r) {
|
||||
radeon_scratch_free(rdev, scratch);
|
||||
radeon_ib_free(rdev, &ib);
|
||||
|
|
@ -4324,7 +4341,7 @@ static int cik_cp_gfx_start(struct radeon_device *rdev)
|
|||
radeon_ring_write(ring, 0x0000000e); /* VGT_VERTEX_REUSE_BLOCK_CNTL */
|
||||
radeon_ring_write(ring, 0x00000010); /* VGT_OUT_DEALLOC_CNTL */
|
||||
|
||||
radeon_ring_unlock_commit(rdev, ring);
|
||||
radeon_ring_unlock_commit(rdev, ring, false);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
|
@ -5958,14 +5975,14 @@ void cik_vm_flush(struct radeon_device *rdev, int ridx, struct radeon_vm *vm)
|
|||
|
||||
/* update SH_MEM_* regs */
|
||||
radeon_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
|
||||
radeon_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
|
||||
radeon_ring_write(ring, (WRITE_DATA_ENGINE_SEL(usepfp) |
|
||||
WRITE_DATA_DST_SEL(0)));
|
||||
radeon_ring_write(ring, SRBM_GFX_CNTL >> 2);
|
||||
radeon_ring_write(ring, 0);
|
||||
radeon_ring_write(ring, VMID(vm->id));
|
||||
|
||||
radeon_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 6));
|
||||
radeon_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
|
||||
radeon_ring_write(ring, (WRITE_DATA_ENGINE_SEL(usepfp) |
|
||||
WRITE_DATA_DST_SEL(0)));
|
||||
radeon_ring_write(ring, SH_MEM_BASES >> 2);
|
||||
radeon_ring_write(ring, 0);
|
||||
|
|
@ -5976,7 +5993,7 @@ void cik_vm_flush(struct radeon_device *rdev, int ridx, struct radeon_vm *vm)
|
|||
radeon_ring_write(ring, 0); /* SH_MEM_APE1_LIMIT */
|
||||
|
||||
radeon_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
|
||||
radeon_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
|
||||
radeon_ring_write(ring, (WRITE_DATA_ENGINE_SEL(usepfp) |
|
||||
WRITE_DATA_DST_SEL(0)));
|
||||
radeon_ring_write(ring, SRBM_GFX_CNTL >> 2);
|
||||
radeon_ring_write(ring, 0);
|
||||
|
|
@ -5987,7 +6004,7 @@ void cik_vm_flush(struct radeon_device *rdev, int ridx, struct radeon_vm *vm)
|
|||
|
||||
/* bits 0-15 are the VM contexts0-15 */
|
||||
radeon_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
|
||||
radeon_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
|
||||
radeon_ring_write(ring, (WRITE_DATA_ENGINE_SEL(usepfp) |
|
||||
WRITE_DATA_DST_SEL(0)));
|
||||
radeon_ring_write(ring, VM_INVALIDATE_REQUEST >> 2);
|
||||
radeon_ring_write(ring, 0);
|
||||
|
|
|
|||
|
|
@ -596,7 +596,7 @@ int cik_copy_dma(struct radeon_device *rdev,
|
|||
return r;
|
||||
}
|
||||
|
||||
radeon_ring_unlock_commit(rdev, ring);
|
||||
radeon_ring_unlock_commit(rdev, ring, false);
|
||||
radeon_semaphore_free(rdev, &sem, *fence);
|
||||
|
||||
return r;
|
||||
|
|
@ -638,7 +638,7 @@ int cik_sdma_ring_test(struct radeon_device *rdev,
|
|||
radeon_ring_write(ring, upper_32_bits(rdev->vram_scratch.gpu_addr));
|
||||
radeon_ring_write(ring, 1); /* number of DWs to follow */
|
||||
radeon_ring_write(ring, 0xDEADBEEF);
|
||||
radeon_ring_unlock_commit(rdev, ring);
|
||||
radeon_ring_unlock_commit(rdev, ring, false);
|
||||
|
||||
for (i = 0; i < rdev->usec_timeout; i++) {
|
||||
tmp = readl(ptr);
|
||||
|
|
@ -695,7 +695,7 @@ int cik_sdma_ib_test(struct radeon_device *rdev, struct radeon_ring *ring)
|
|||
ib.ptr[4] = 0xDEADBEEF;
|
||||
ib.length_dw = 5;
|
||||
|
||||
r = radeon_ib_schedule(rdev, &ib, NULL);
|
||||
r = radeon_ib_schedule(rdev, &ib, NULL, false);
|
||||
if (r) {
|
||||
radeon_ib_free(rdev, &ib);
|
||||
DRM_ERROR("radeon: failed to schedule ib (%d).\n", r);
|
||||
|
|
|
|||
|
|
@ -2869,7 +2869,7 @@ static int evergreen_cp_start(struct radeon_device *rdev)
|
|||
radeon_ring_write(ring, PACKET3_ME_INITIALIZE_DEVICE_ID(1));
|
||||
radeon_ring_write(ring, 0);
|
||||
radeon_ring_write(ring, 0);
|
||||
radeon_ring_unlock_commit(rdev, ring);
|
||||
radeon_ring_unlock_commit(rdev, ring, false);
|
||||
|
||||
cp_me = 0xff;
|
||||
WREG32(CP_ME_CNTL, cp_me);
|
||||
|
|
@ -2912,7 +2912,7 @@ static int evergreen_cp_start(struct radeon_device *rdev)
|
|||
radeon_ring_write(ring, 0x0000000e); /* VGT_VERTEX_REUSE_BLOCK_CNTL */
|
||||
radeon_ring_write(ring, 0x00000010); /* */
|
||||
|
||||
radeon_ring_unlock_commit(rdev, ring);
|
||||
radeon_ring_unlock_commit(rdev, ring, false);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
|
|
|||
|
|
@ -155,7 +155,7 @@ int evergreen_copy_dma(struct radeon_device *rdev,
|
|||
return r;
|
||||
}
|
||||
|
||||
radeon_ring_unlock_commit(rdev, ring);
|
||||
radeon_ring_unlock_commit(rdev, ring, false);
|
||||
radeon_semaphore_free(rdev, &sem, *fence);
|
||||
|
||||
return r;
|
||||
|
|
|
|||
|
|
@ -1438,14 +1438,14 @@ static int kv_update_uvd_dpm(struct radeon_device *rdev, bool gate)
|
|||
return kv_enable_uvd_dpm(rdev, !gate);
|
||||
}
|
||||
|
||||
static u8 kv_get_vce_boot_level(struct radeon_device *rdev)
|
||||
static u8 kv_get_vce_boot_level(struct radeon_device *rdev, u32 evclk)
|
||||
{
|
||||
u8 i;
|
||||
struct radeon_vce_clock_voltage_dependency_table *table =
|
||||
&rdev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table;
|
||||
|
||||
for (i = 0; i < table->count; i++) {
|
||||
if (table->entries[i].evclk >= 0) /* XXX */
|
||||
if (table->entries[i].evclk >= evclk)
|
||||
break;
|
||||
}
|
||||
|
||||
|
|
@ -1468,7 +1468,7 @@ static int kv_update_vce_dpm(struct radeon_device *rdev,
|
|||
if (pi->caps_stable_p_state)
|
||||
pi->vce_boot_level = table->count - 1;
|
||||
else
|
||||
pi->vce_boot_level = kv_get_vce_boot_level(rdev);
|
||||
pi->vce_boot_level = kv_get_vce_boot_level(rdev, radeon_new_state->evclk);
|
||||
|
||||
ret = kv_copy_bytes_to_smc(rdev,
|
||||
pi->dpm_table_start +
|
||||
|
|
@ -2726,6 +2726,9 @@ int kv_dpm_init(struct radeon_device *rdev)
|
|||
pi->caps_sclk_ds = true;
|
||||
pi->enable_auto_thermal_throttling = true;
|
||||
pi->disable_nb_ps3_in_battery = false;
|
||||
if (radeon_bapm == 0)
|
||||
pi->bapm_enable = false;
|
||||
else
|
||||
pi->bapm_enable = true;
|
||||
pi->voltage_drop_t = 0;
|
||||
pi->caps_sclk_throttle_low_notification = false;
|
||||
|
|
|
|||
|
|
@ -1505,7 +1505,7 @@ static int cayman_cp_start(struct radeon_device *rdev)
|
|||
radeon_ring_write(ring, PACKET3_ME_INITIALIZE_DEVICE_ID(1));
|
||||
radeon_ring_write(ring, 0);
|
||||
radeon_ring_write(ring, 0);
|
||||
radeon_ring_unlock_commit(rdev, ring);
|
||||
radeon_ring_unlock_commit(rdev, ring, false);
|
||||
|
||||
cayman_cp_enable(rdev, true);
|
||||
|
||||
|
|
@ -1547,7 +1547,7 @@ static int cayman_cp_start(struct radeon_device *rdev)
|
|||
radeon_ring_write(ring, 0x0000000e); /* VGT_VERTEX_REUSE_BLOCK_CNTL */
|
||||
radeon_ring_write(ring, 0x00000010); /* */
|
||||
|
||||
radeon_ring_unlock_commit(rdev, ring);
|
||||
radeon_ring_unlock_commit(rdev, ring, false);
|
||||
|
||||
/* XXX init other rings */
|
||||
|
||||
|
|
|
|||
|
|
@ -925,7 +925,7 @@ int r100_copy_blit(struct radeon_device *rdev,
|
|||
if (fence) {
|
||||
r = radeon_fence_emit(rdev, fence, RADEON_RING_TYPE_GFX_INDEX);
|
||||
}
|
||||
radeon_ring_unlock_commit(rdev, ring);
|
||||
radeon_ring_unlock_commit(rdev, ring, false);
|
||||
return r;
|
||||
}
|
||||
|
||||
|
|
@ -958,7 +958,7 @@ void r100_ring_start(struct radeon_device *rdev, struct radeon_ring *ring)
|
|||
RADEON_ISYNC_ANY3D_IDLE2D |
|
||||
RADEON_ISYNC_WAIT_IDLEGUI |
|
||||
RADEON_ISYNC_CPSCRATCH_IDLEGUI);
|
||||
radeon_ring_unlock_commit(rdev, ring);
|
||||
radeon_ring_unlock_commit(rdev, ring, false);
|
||||
}
|
||||
|
||||
|
||||
|
|
@ -3638,7 +3638,7 @@ int r100_ring_test(struct radeon_device *rdev, struct radeon_ring *ring)
|
|||
}
|
||||
radeon_ring_write(ring, PACKET0(scratch, 0));
|
||||
radeon_ring_write(ring, 0xDEADBEEF);
|
||||
radeon_ring_unlock_commit(rdev, ring);
|
||||
radeon_ring_unlock_commit(rdev, ring, false);
|
||||
for (i = 0; i < rdev->usec_timeout; i++) {
|
||||
tmp = RREG32(scratch);
|
||||
if (tmp == 0xDEADBEEF) {
|
||||
|
|
@ -3700,7 +3700,7 @@ int r100_ib_test(struct radeon_device *rdev, struct radeon_ring *ring)
|
|||
ib.ptr[6] = PACKET2(0);
|
||||
ib.ptr[7] = PACKET2(0);
|
||||
ib.length_dw = 8;
|
||||
r = radeon_ib_schedule(rdev, &ib, NULL);
|
||||
r = radeon_ib_schedule(rdev, &ib, NULL, false);
|
||||
if (r) {
|
||||
DRM_ERROR("radeon: failed to schedule ib (%d).\n", r);
|
||||
goto free_ib;
|
||||
|
|
|
|||
|
|
@ -121,7 +121,7 @@ int r200_copy_dma(struct radeon_device *rdev,
|
|||
if (fence) {
|
||||
r = radeon_fence_emit(rdev, fence, RADEON_RING_TYPE_GFX_INDEX);
|
||||
}
|
||||
radeon_ring_unlock_commit(rdev, ring);
|
||||
radeon_ring_unlock_commit(rdev, ring, false);
|
||||
return r;
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -295,7 +295,7 @@ void r300_ring_start(struct radeon_device *rdev, struct radeon_ring *ring)
|
|||
radeon_ring_write(ring,
|
||||
R300_GEOMETRY_ROUND_NEAREST |
|
||||
R300_COLOR_ROUND_NEAREST);
|
||||
radeon_ring_unlock_commit(rdev, ring);
|
||||
radeon_ring_unlock_commit(rdev, ring, false);
|
||||
}
|
||||
|
||||
static void r300_errata(struct radeon_device *rdev)
|
||||
|
|
|
|||
|
|
@ -219,7 +219,7 @@ static void r420_cp_errata_init(struct radeon_device *rdev)
|
|||
radeon_ring_write(ring, PACKET0(R300_CP_RESYNC_ADDR, 1));
|
||||
radeon_ring_write(ring, rdev->config.r300.resync_scratch);
|
||||
radeon_ring_write(ring, 0xDEADBEEF);
|
||||
radeon_ring_unlock_commit(rdev, ring);
|
||||
radeon_ring_unlock_commit(rdev, ring, false);
|
||||
}
|
||||
|
||||
static void r420_cp_errata_fini(struct radeon_device *rdev)
|
||||
|
|
@ -232,7 +232,7 @@ static void r420_cp_errata_fini(struct radeon_device *rdev)
|
|||
radeon_ring_lock(rdev, ring, 8);
|
||||
radeon_ring_write(ring, PACKET0(R300_RB3D_DSTCACHE_CTLSTAT, 0));
|
||||
radeon_ring_write(ring, R300_RB3D_DC_FINISH);
|
||||
radeon_ring_unlock_commit(rdev, ring);
|
||||
radeon_ring_unlock_commit(rdev, ring, false);
|
||||
radeon_scratch_free(rdev, rdev->config.r300.resync_scratch);
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -2547,7 +2547,7 @@ int r600_cp_start(struct radeon_device *rdev)
|
|||
radeon_ring_write(ring, PACKET3_ME_INITIALIZE_DEVICE_ID(1));
|
||||
radeon_ring_write(ring, 0);
|
||||
radeon_ring_write(ring, 0);
|
||||
radeon_ring_unlock_commit(rdev, ring);
|
||||
radeon_ring_unlock_commit(rdev, ring, false);
|
||||
|
||||
cp_me = 0xff;
|
||||
WREG32(R_0086D8_CP_ME_CNTL, cp_me);
|
||||
|
|
@ -2683,7 +2683,7 @@ int r600_ring_test(struct radeon_device *rdev, struct radeon_ring *ring)
|
|||
radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1));
|
||||
radeon_ring_write(ring, ((scratch - PACKET3_SET_CONFIG_REG_OFFSET) >> 2));
|
||||
radeon_ring_write(ring, 0xDEADBEEF);
|
||||
radeon_ring_unlock_commit(rdev, ring);
|
||||
radeon_ring_unlock_commit(rdev, ring, false);
|
||||
for (i = 0; i < rdev->usec_timeout; i++) {
|
||||
tmp = RREG32(scratch);
|
||||
if (tmp == 0xDEADBEEF)
|
||||
|
|
@ -2753,6 +2753,17 @@ void r600_fence_ring_emit(struct radeon_device *rdev,
|
|||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* r600_semaphore_ring_emit - emit a semaphore on the CP ring
|
||||
*
|
||||
* @rdev: radeon_device pointer
|
||||
* @ring: radeon ring buffer object
|
||||
* @semaphore: radeon semaphore object
|
||||
* @emit_wait: Is this a sempahore wait?
|
||||
*
|
||||
* Emits a semaphore signal/wait packet to the CP ring and prevents the PFP
|
||||
* from running ahead of semaphore waits.
|
||||
*/
|
||||
bool r600_semaphore_ring_emit(struct radeon_device *rdev,
|
||||
struct radeon_ring *ring,
|
||||
struct radeon_semaphore *semaphore,
|
||||
|
|
@ -2768,6 +2779,13 @@ bool r600_semaphore_ring_emit(struct radeon_device *rdev,
|
|||
radeon_ring_write(ring, lower_32_bits(addr));
|
||||
radeon_ring_write(ring, (upper_32_bits(addr) & 0xff) | sel);
|
||||
|
||||
/* PFP_SYNC_ME packet only exists on 7xx+ */
|
||||
if (emit_wait && (rdev->family >= CHIP_RV770)) {
|
||||
/* Prevent the PFP from running ahead of the semaphore wait */
|
||||
radeon_ring_write(ring, PACKET3(PACKET3_PFP_SYNC_ME, 0));
|
||||
radeon_ring_write(ring, 0x0);
|
||||
}
|
||||
|
||||
return true;
|
||||
}
|
||||
|
||||
|
|
@ -2845,7 +2863,7 @@ int r600_copy_cpdma(struct radeon_device *rdev,
|
|||
return r;
|
||||
}
|
||||
|
||||
radeon_ring_unlock_commit(rdev, ring);
|
||||
radeon_ring_unlock_commit(rdev, ring, false);
|
||||
radeon_semaphore_free(rdev, &sem, *fence);
|
||||
|
||||
return r;
|
||||
|
|
@ -3165,7 +3183,7 @@ int r600_ib_test(struct radeon_device *rdev, struct radeon_ring *ring)
|
|||
ib.ptr[1] = ((scratch - PACKET3_SET_CONFIG_REG_OFFSET) >> 2);
|
||||
ib.ptr[2] = 0xDEADBEEF;
|
||||
ib.length_dw = 3;
|
||||
r = radeon_ib_schedule(rdev, &ib, NULL);
|
||||
r = radeon_ib_schedule(rdev, &ib, NULL, false);
|
||||
if (r) {
|
||||
DRM_ERROR("radeon: failed to schedule ib (%d).\n", r);
|
||||
goto free_ib;
|
||||
|
|
|
|||
|
|
@ -261,7 +261,7 @@ int r600_dma_ring_test(struct radeon_device *rdev,
|
|||
radeon_ring_write(ring, rdev->vram_scratch.gpu_addr & 0xfffffffc);
|
||||
radeon_ring_write(ring, upper_32_bits(rdev->vram_scratch.gpu_addr) & 0xff);
|
||||
radeon_ring_write(ring, 0xDEADBEEF);
|
||||
radeon_ring_unlock_commit(rdev, ring);
|
||||
radeon_ring_unlock_commit(rdev, ring, false);
|
||||
|
||||
for (i = 0; i < rdev->usec_timeout; i++) {
|
||||
tmp = readl(ptr);
|
||||
|
|
@ -368,7 +368,7 @@ int r600_dma_ib_test(struct radeon_device *rdev, struct radeon_ring *ring)
|
|||
ib.ptr[3] = 0xDEADBEEF;
|
||||
ib.length_dw = 4;
|
||||
|
||||
r = radeon_ib_schedule(rdev, &ib, NULL);
|
||||
r = radeon_ib_schedule(rdev, &ib, NULL, false);
|
||||
if (r) {
|
||||
radeon_ib_free(rdev, &ib);
|
||||
DRM_ERROR("radeon: failed to schedule ib (%d).\n", r);
|
||||
|
|
@ -493,7 +493,7 @@ int r600_copy_dma(struct radeon_device *rdev,
|
|||
return r;
|
||||
}
|
||||
|
||||
radeon_ring_unlock_commit(rdev, ring);
|
||||
radeon_ring_unlock_commit(rdev, ring, false);
|
||||
radeon_semaphore_free(rdev, &sem, *fence);
|
||||
|
||||
return r;
|
||||
|
|
|
|||
|
|
@ -1597,6 +1597,7 @@
|
|||
*/
|
||||
# define PACKET3_CP_DMA_CMD_SAIC (1 << 28)
|
||||
# define PACKET3_CP_DMA_CMD_DAIC (1 << 29)
|
||||
#define PACKET3_PFP_SYNC_ME 0x42 /* r7xx+ only */
|
||||
#define PACKET3_SURFACE_SYNC 0x43
|
||||
# define PACKET3_CB0_DEST_BASE_ENA (1 << 6)
|
||||
# define PACKET3_FULL_CACHE_ENA (1 << 20) /* r7xx+ only */
|
||||
|
|
|
|||
|
|
@ -105,6 +105,7 @@ extern int radeon_vm_size;
|
|||
extern int radeon_vm_block_size;
|
||||
extern int radeon_deep_color;
|
||||
extern int radeon_use_pflipirq;
|
||||
extern int radeon_bapm;
|
||||
|
||||
/*
|
||||
* Copy from radeon_drv.h so we don't have to include both and have conflicting
|
||||
|
|
@ -967,7 +968,7 @@ int radeon_ib_get(struct radeon_device *rdev, int ring,
|
|||
unsigned size);
|
||||
void radeon_ib_free(struct radeon_device *rdev, struct radeon_ib *ib);
|
||||
int radeon_ib_schedule(struct radeon_device *rdev, struct radeon_ib *ib,
|
||||
struct radeon_ib *const_ib);
|
||||
struct radeon_ib *const_ib, bool hdp_flush);
|
||||
int radeon_ib_pool_init(struct radeon_device *rdev);
|
||||
void radeon_ib_pool_fini(struct radeon_device *rdev);
|
||||
int radeon_ib_ring_tests(struct radeon_device *rdev);
|
||||
|
|
@ -977,8 +978,10 @@ bool radeon_ring_supports_scratch_reg(struct radeon_device *rdev,
|
|||
void radeon_ring_free_size(struct radeon_device *rdev, struct radeon_ring *cp);
|
||||
int radeon_ring_alloc(struct radeon_device *rdev, struct radeon_ring *cp, unsigned ndw);
|
||||
int radeon_ring_lock(struct radeon_device *rdev, struct radeon_ring *cp, unsigned ndw);
|
||||
void radeon_ring_commit(struct radeon_device *rdev, struct radeon_ring *cp);
|
||||
void radeon_ring_unlock_commit(struct radeon_device *rdev, struct radeon_ring *cp);
|
||||
void radeon_ring_commit(struct radeon_device *rdev, struct radeon_ring *cp,
|
||||
bool hdp_flush);
|
||||
void radeon_ring_unlock_commit(struct radeon_device *rdev, struct radeon_ring *cp,
|
||||
bool hdp_flush);
|
||||
void radeon_ring_undo(struct radeon_ring *ring);
|
||||
void radeon_ring_unlock_undo(struct radeon_device *rdev, struct radeon_ring *cp);
|
||||
int radeon_ring_test(struct radeon_device *rdev, struct radeon_ring *cp);
|
||||
|
|
|
|||
|
|
@ -132,7 +132,8 @@ static int radeon_cs_parser_relocs(struct radeon_cs_parser *p)
|
|||
* the buffers used for read only, which doubles the range
|
||||
* to 0 to 31. 32 is reserved for the kernel driver.
|
||||
*/
|
||||
priority = (r->flags & 0xf) * 2 + !!r->write_domain;
|
||||
priority = (r->flags & RADEON_RELOC_PRIO_MASK) * 2
|
||||
+ !!r->write_domain;
|
||||
|
||||
/* the first reloc of an UVD job is the msg and that must be in
|
||||
VRAM, also but everything into VRAM on AGP cards to avoid
|
||||
|
|
@ -450,7 +451,7 @@ static int radeon_cs_ib_chunk(struct radeon_device *rdev,
|
|||
radeon_vce_note_usage(rdev);
|
||||
|
||||
radeon_cs_sync_rings(parser);
|
||||
r = radeon_ib_schedule(rdev, &parser->ib, NULL);
|
||||
r = radeon_ib_schedule(rdev, &parser->ib, NULL, true);
|
||||
if (r) {
|
||||
DRM_ERROR("Failed to schedule IB !\n");
|
||||
}
|
||||
|
|
@ -541,9 +542,9 @@ static int radeon_cs_ib_vm_chunk(struct radeon_device *rdev,
|
|||
|
||||
if ((rdev->family >= CHIP_TAHITI) &&
|
||||
(parser->chunk_const_ib_idx != -1)) {
|
||||
r = radeon_ib_schedule(rdev, &parser->ib, &parser->const_ib);
|
||||
r = radeon_ib_schedule(rdev, &parser->ib, &parser->const_ib, true);
|
||||
} else {
|
||||
r = radeon_ib_schedule(rdev, &parser->ib, NULL);
|
||||
r = radeon_ib_schedule(rdev, &parser->ib, NULL, true);
|
||||
}
|
||||
|
||||
out:
|
||||
|
|
|
|||
|
|
@ -1680,8 +1680,8 @@ int radeon_gpu_reset(struct radeon_device *rdev)
|
|||
radeon_save_bios_scratch_regs(rdev);
|
||||
/* block TTM */
|
||||
resched = ttm_bo_lock_delayed_workqueue(&rdev->mman.bdev);
|
||||
radeon_pm_suspend(rdev);
|
||||
radeon_suspend(rdev);
|
||||
radeon_hpd_fini(rdev);
|
||||
|
||||
for (i = 0; i < RADEON_NUM_RINGS; ++i) {
|
||||
ring_sizes[i] = radeon_ring_backup(rdev, &rdev->ring[i],
|
||||
|
|
@ -1726,9 +1726,39 @@ retry:
|
|||
}
|
||||
}
|
||||
|
||||
if ((rdev->pm.pm_method == PM_METHOD_DPM) && rdev->pm.dpm_enabled) {
|
||||
/* do dpm late init */
|
||||
r = radeon_pm_late_init(rdev);
|
||||
if (r) {
|
||||
rdev->pm.dpm_enabled = false;
|
||||
DRM_ERROR("radeon_pm_late_init failed, disabling dpm\n");
|
||||
}
|
||||
} else {
|
||||
/* resume old pm late */
|
||||
radeon_pm_resume(rdev);
|
||||
}
|
||||
|
||||
/* init dig PHYs, disp eng pll */
|
||||
if (rdev->is_atom_bios) {
|
||||
radeon_atom_encoder_init(rdev);
|
||||
radeon_atom_disp_eng_pll_init(rdev);
|
||||
/* turn on the BL */
|
||||
if (rdev->mode_info.bl_encoder) {
|
||||
u8 bl_level = radeon_get_backlight_level(rdev,
|
||||
rdev->mode_info.bl_encoder);
|
||||
radeon_set_backlight_level(rdev, rdev->mode_info.bl_encoder,
|
||||
bl_level);
|
||||
}
|
||||
}
|
||||
/* reset hpd state */
|
||||
radeon_hpd_init(rdev);
|
||||
|
||||
drm_helper_resume_force_mode(rdev->ddev);
|
||||
|
||||
/* set the power state here in case we are a PX system or headless */
|
||||
if ((rdev->pm.pm_method == PM_METHOD_DPM) && rdev->pm.dpm_enabled)
|
||||
radeon_pm_compute_clocks(rdev);
|
||||
|
||||
ttm_bo_unlock_delayed_workqueue(&rdev->mman.bdev, resched);
|
||||
if (r) {
|
||||
/* bad news, how to tell it to userspace ? */
|
||||
|
|
|
|||
|
|
@ -180,6 +180,7 @@ int radeon_vm_size = 8;
|
|||
int radeon_vm_block_size = -1;
|
||||
int radeon_deep_color = 0;
|
||||
int radeon_use_pflipirq = 2;
|
||||
int radeon_bapm = -1;
|
||||
|
||||
MODULE_PARM_DESC(no_wb, "Disable AGP writeback for scratch registers");
|
||||
module_param_named(no_wb, radeon_no_wb, int, 0444);
|
||||
|
|
@ -259,6 +260,9 @@ module_param_named(deep_color, radeon_deep_color, int, 0444);
|
|||
MODULE_PARM_DESC(use_pflipirq, "Pflip irqs for pageflip completion (0 = disable, 1 = as fallback, 2 = exclusive (default))");
|
||||
module_param_named(use_pflipirq, radeon_use_pflipirq, int, 0444);
|
||||
|
||||
MODULE_PARM_DESC(bapm, "BAPM support (1 = enable, 0 = disable, -1 = auto)");
|
||||
module_param_named(bapm, radeon_bapm, int, 0444);
|
||||
|
||||
static struct pci_device_id pciidlist[] = {
|
||||
radeon_PCI_IDS
|
||||
};
|
||||
|
|
|
|||
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