phy: qcom: Add QCOM SNPS eUSB2 driver
The SM8550 SoC uses Synopsis eUSB2 PHY for USB 2.0. Add a new driver for it. The driver is based on a downstream implementation. Signed-off-by: Abel Vesa <abel.vesa@linaro.org> Link: https://lore.kernel.org/r/20230208183421.2874423-3-abel.vesa@linaro.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
This commit is contained in:
Abel Vesa
Vinod Koul
Родитель
5ccacdbed4
Коммит
80090810f5
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@ -112,6 +112,15 @@ config PHY_QCOM_QUSB2
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PHY which is usually paired with either the ChipIdea or Synopsys DWC3
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USB IPs on MSM SOCs.
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config PHY_QCOM_SNPS_EUSB2
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tristate "Qualcomm SNPS eUSB2 PHY Driver"
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depends on OF && (ARCH_QCOM || COMPILE_TEST)
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select GENERIC_PHY
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help
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Enable support for the USB high-speed SNPS eUSB2 phy on Qualcomm
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chipsets. The PHY is paired with a Synopsys DWC3 USB controller
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on Qualcomm SOCs.
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config PHY_QCOM_USB_HS
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tristate "Qualcomm USB HS PHY module"
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depends on USB_ULPI_BUS
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@ -13,6 +13,7 @@ obj-$(CONFIG_PHY_QCOM_QMP_UFS) += phy-qcom-qmp-ufs.o
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obj-$(CONFIG_PHY_QCOM_QMP_USB) += phy-qcom-qmp-usb.o
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obj-$(CONFIG_PHY_QCOM_QUSB2) += phy-qcom-qusb2.o
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obj-$(CONFIG_PHY_QCOM_SNPS_EUSB2) += phy-qcom-snps-eusb2.o
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obj-$(CONFIG_PHY_QCOM_USB_HS) += phy-qcom-usb-hs.o
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obj-$(CONFIG_PHY_QCOM_USB_HSIC) += phy-qcom-usb-hsic.o
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obj-$(CONFIG_PHY_QCOM_USB_HS_28NM) += phy-qcom-usb-hs-28nm.o
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@ -0,0 +1,422 @@
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// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (c) 2023, Linaro Limited
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*/
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#include <linux/clk.h>
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#include <linux/delay.h>
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#include <linux/phy/phy.h>
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#include <linux/platform_device.h>
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#include <linux/regulator/consumer.h>
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#include <linux/reset.h>
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#define USB_PHY_UTMI_CTRL0 (0x3c)
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#define SLEEPM BIT(0)
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#define OPMODE_MASK GENMASK(4, 3)
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#define OPMODE_NONDRIVING BIT(3)
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#define USB_PHY_UTMI_CTRL5 (0x50)
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#define POR BIT(1)
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#define USB_PHY_HS_PHY_CTRL_COMMON0 (0x54)
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#define PHY_ENABLE BIT(0)
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#define SIDDQ_SEL BIT(1)
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#define SIDDQ BIT(2)
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#define RETENABLEN BIT(3)
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#define FSEL_MASK GENMASK(6, 4)
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#define FSEL_19_2_MHZ_VAL (0x0)
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#define FSEL_38_4_MHZ_VAL (0x4)
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#define USB_PHY_CFG_CTRL_1 (0x58)
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#define PHY_CFG_PLL_CPBIAS_CNTRL_MASK GENMASK(7, 1)
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#define USB_PHY_CFG_CTRL_2 (0x5c)
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#define PHY_CFG_PLL_FB_DIV_7_0_MASK GENMASK(7, 0)
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#define DIV_7_0_19_2_MHZ_VAL (0x90)
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#define DIV_7_0_38_4_MHZ_VAL (0xc8)
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#define USB_PHY_CFG_CTRL_3 (0x60)
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#define PHY_CFG_PLL_FB_DIV_11_8_MASK GENMASK(3, 0)
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#define DIV_11_8_19_2_MHZ_VAL (0x1)
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#define DIV_11_8_38_4_MHZ_VAL (0x0)
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#define PHY_CFG_PLL_REF_DIV GENMASK(7, 4)
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#define PLL_REF_DIV_VAL (0x0)
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#define USB_PHY_HS_PHY_CTRL2 (0x64)
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#define VBUSVLDEXT0 BIT(0)
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#define USB2_SUSPEND_N BIT(2)
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#define USB2_SUSPEND_N_SEL BIT(3)
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#define VBUS_DET_EXT_SEL BIT(4)
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#define USB_PHY_CFG_CTRL_4 (0x68)
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#define PHY_CFG_PLL_GMP_CNTRL_MASK GENMASK(1, 0)
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#define PHY_CFG_PLL_INT_CNTRL_MASK GENMASK(7, 2)
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#define USB_PHY_CFG_CTRL_5 (0x6c)
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#define PHY_CFG_PLL_PROP_CNTRL_MASK GENMASK(4, 0)
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#define PHY_CFG_PLL_VREF_TUNE_MASK GENMASK(7, 6)
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#define USB_PHY_CFG_CTRL_6 (0x70)
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#define PHY_CFG_PLL_VCO_CNTRL_MASK GENMASK(2, 0)
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#define USB_PHY_CFG_CTRL_7 (0x74)
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#define USB_PHY_CFG_CTRL_8 (0x78)
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#define PHY_CFG_TX_FSLS_VREF_TUNE_MASK GENMASK(1, 0)
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#define PHY_CFG_TX_FSLS_VREG_BYPASS BIT(2)
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#define PHY_CFG_TX_HS_VREF_TUNE_MASK GENMASK(5, 3)
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#define PHY_CFG_TX_HS_XV_TUNE_MASK GENMASK(7, 6)
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#define USB_PHY_CFG_CTRL_9 (0x7c)
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#define PHY_CFG_TX_PREEMP_TUNE_MASK GENMASK(2, 0)
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#define PHY_CFG_TX_RES_TUNE_MASK GENMASK(4, 3)
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#define PHY_CFG_TX_RISE_TUNE_MASK GENMASK(6, 5)
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#define PHY_CFG_RCAL_BYPASS BIT(7)
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#define USB_PHY_CFG_CTRL_10 (0x80)
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#define USB_PHY_CFG0 (0x94)
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#define DATAPATH_CTRL_OVERRIDE_EN BIT(0)
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#define CMN_CTRL_OVERRIDE_EN BIT(1)
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#define UTMI_PHY_CMN_CTRL0 (0x98)
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#define TESTBURNIN BIT(6)
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#define USB_PHY_FSEL_SEL (0xb8)
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#define FSEL_SEL BIT(0)
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#define USB_PHY_APB_ACCESS_CMD (0x130)
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#define RW_ACCESS BIT(0)
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#define APB_START_CMD BIT(1)
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#define APB_LOGIC_RESET BIT(2)
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#define USB_PHY_APB_ACCESS_STATUS (0x134)
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#define ACCESS_DONE BIT(0)
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#define TIMED_OUT BIT(1)
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#define ACCESS_ERROR BIT(2)
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#define ACCESS_IN_PROGRESS BIT(3)
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#define USB_PHY_APB_ADDRESS (0x138)
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#define APB_REG_ADDR_MASK GENMASK(7, 0)
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#define USB_PHY_APB_WRDATA_LSB (0x13c)
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#define APB_REG_WRDATA_7_0_MASK GENMASK(3, 0)
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#define USB_PHY_APB_WRDATA_MSB (0x140)
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#define APB_REG_WRDATA_15_8_MASK GENMASK(7, 4)
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#define USB_PHY_APB_RDDATA_LSB (0x144)
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#define APB_REG_RDDATA_7_0_MASK GENMASK(3, 0)
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#define USB_PHY_APB_RDDATA_MSB (0x148)
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#define APB_REG_RDDATA_15_8_MASK GENMASK(7, 4)
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static const char * const eusb2_hsphy_vreg_names[] = {
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"vdd", "vdda12",
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};
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#define EUSB2_NUM_VREGS ARRAY_SIZE(eusb2_hsphy_vreg_names)
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struct qcom_snps_eusb2_hsphy {
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struct phy *phy;
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void __iomem *base;
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struct clk *ref_clk;
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struct reset_control *phy_reset;
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struct regulator_bulk_data vregs[EUSB2_NUM_VREGS];
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enum phy_mode mode;
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};
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static int qcom_snps_eusb2_hsphy_set_mode(struct phy *p, enum phy_mode mode, int submode)
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{
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struct qcom_snps_eusb2_hsphy *phy = phy_get_drvdata(p);
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phy->mode = mode;
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return 0;
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}
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static void qcom_snps_eusb2_hsphy_write_mask(void __iomem *base, u32 offset,
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u32 mask, u32 val)
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{
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u32 reg;
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reg = readl_relaxed(base + offset);
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reg &= ~mask;
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reg |= val & mask;
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writel_relaxed(reg, base + offset);
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/* Ensure above write is completed */
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readl_relaxed(base + offset);
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}
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static void qcom_eusb2_default_parameters(struct qcom_snps_eusb2_hsphy *phy)
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{
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/* default parameters: tx pre-emphasis */
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qcom_snps_eusb2_hsphy_write_mask(phy->base, USB_PHY_CFG_CTRL_9,
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PHY_CFG_TX_PREEMP_TUNE_MASK,
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FIELD_PREP(PHY_CFG_TX_PREEMP_TUNE_MASK, 0));
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/* tx rise/fall time */
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qcom_snps_eusb2_hsphy_write_mask(phy->base, USB_PHY_CFG_CTRL_9,
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PHY_CFG_TX_RISE_TUNE_MASK,
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FIELD_PREP(PHY_CFG_TX_RISE_TUNE_MASK, 0x2));
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/* source impedance adjustment */
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qcom_snps_eusb2_hsphy_write_mask(phy->base, USB_PHY_CFG_CTRL_9,
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PHY_CFG_TX_RES_TUNE_MASK,
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FIELD_PREP(PHY_CFG_TX_RES_TUNE_MASK, 0x1));
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/* dc voltage level adjustement */
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qcom_snps_eusb2_hsphy_write_mask(phy->base, USB_PHY_CFG_CTRL_8,
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PHY_CFG_TX_HS_VREF_TUNE_MASK,
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FIELD_PREP(PHY_CFG_TX_HS_VREF_TUNE_MASK, 0x3));
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/* transmitter HS crossover adjustement */
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qcom_snps_eusb2_hsphy_write_mask(phy->base, USB_PHY_CFG_CTRL_8,
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PHY_CFG_TX_HS_XV_TUNE_MASK,
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FIELD_PREP(PHY_CFG_TX_HS_XV_TUNE_MASK, 0x0));
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}
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static int qcom_eusb2_ref_clk_init(struct qcom_snps_eusb2_hsphy *phy)
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{
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unsigned long ref_clk_freq = clk_get_rate(phy->ref_clk);
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switch (ref_clk_freq) {
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case 19200000:
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qcom_snps_eusb2_hsphy_write_mask(phy->base, USB_PHY_HS_PHY_CTRL_COMMON0,
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FSEL_MASK,
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FIELD_PREP(FSEL_MASK, FSEL_19_2_MHZ_VAL));
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qcom_snps_eusb2_hsphy_write_mask(phy->base, USB_PHY_CFG_CTRL_2,
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PHY_CFG_PLL_FB_DIV_7_0_MASK,
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DIV_7_0_19_2_MHZ_VAL);
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qcom_snps_eusb2_hsphy_write_mask(phy->base, USB_PHY_CFG_CTRL_3,
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PHY_CFG_PLL_FB_DIV_11_8_MASK,
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DIV_11_8_19_2_MHZ_VAL);
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break;
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case 38400000:
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qcom_snps_eusb2_hsphy_write_mask(phy->base, USB_PHY_HS_PHY_CTRL_COMMON0,
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FSEL_MASK,
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FIELD_PREP(FSEL_MASK, FSEL_38_4_MHZ_VAL));
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qcom_snps_eusb2_hsphy_write_mask(phy->base, USB_PHY_CFG_CTRL_2,
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PHY_CFG_PLL_FB_DIV_7_0_MASK,
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DIV_7_0_38_4_MHZ_VAL);
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qcom_snps_eusb2_hsphy_write_mask(phy->base, USB_PHY_CFG_CTRL_3,
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PHY_CFG_PLL_FB_DIV_11_8_MASK,
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DIV_11_8_38_4_MHZ_VAL);
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break;
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default:
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dev_err(&phy->phy->dev, "unsupported ref_clk_freq:%lu\n", ref_clk_freq);
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return -EINVAL;
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}
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qcom_snps_eusb2_hsphy_write_mask(phy->base, USB_PHY_CFG_CTRL_3,
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PHY_CFG_PLL_REF_DIV, PLL_REF_DIV_VAL);
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return 0;
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}
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static int qcom_snps_eusb2_hsphy_init(struct phy *p)
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{
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struct qcom_snps_eusb2_hsphy *phy = phy_get_drvdata(p);
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int ret;
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ret = regulator_bulk_enable(ARRAY_SIZE(phy->vregs), phy->vregs);
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if (ret)
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return ret;
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ret = clk_prepare_enable(phy->ref_clk);
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if (ret) {
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dev_err(&p->dev, "failed to enable ref clock, %d\n", ret);
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goto disable_vreg;
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}
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ret = reset_control_assert(phy->phy_reset);
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if (ret) {
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dev_err(&p->dev, "failed to assert phy_reset, %d\n", ret);
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goto disable_ref_clk;
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}
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usleep_range(100, 150);
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ret = reset_control_deassert(phy->phy_reset);
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if (ret) {
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dev_err(&p->dev, "failed to de-assert phy_reset, %d\n", ret);
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goto disable_ref_clk;
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}
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qcom_snps_eusb2_hsphy_write_mask(phy->base, USB_PHY_CFG0,
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CMN_CTRL_OVERRIDE_EN, CMN_CTRL_OVERRIDE_EN);
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qcom_snps_eusb2_hsphy_write_mask(phy->base, USB_PHY_UTMI_CTRL5, POR, POR);
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qcom_snps_eusb2_hsphy_write_mask(phy->base, USB_PHY_HS_PHY_CTRL_COMMON0,
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PHY_ENABLE | RETENABLEN, PHY_ENABLE | RETENABLEN);
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qcom_snps_eusb2_hsphy_write_mask(phy->base, USB_PHY_APB_ACCESS_CMD,
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APB_LOGIC_RESET, APB_LOGIC_RESET);
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qcom_snps_eusb2_hsphy_write_mask(phy->base, UTMI_PHY_CMN_CTRL0, TESTBURNIN, 0);
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qcom_snps_eusb2_hsphy_write_mask(phy->base, USB_PHY_FSEL_SEL,
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FSEL_SEL, FSEL_SEL);
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/* update ref_clk related registers */
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ret = qcom_eusb2_ref_clk_init(phy);
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if (ret)
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goto disable_ref_clk;
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qcom_snps_eusb2_hsphy_write_mask(phy->base, USB_PHY_CFG_CTRL_1,
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PHY_CFG_PLL_CPBIAS_CNTRL_MASK,
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FIELD_PREP(PHY_CFG_PLL_CPBIAS_CNTRL_MASK, 0x1));
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qcom_snps_eusb2_hsphy_write_mask(phy->base, USB_PHY_CFG_CTRL_4,
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PHY_CFG_PLL_INT_CNTRL_MASK,
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FIELD_PREP(PHY_CFG_PLL_INT_CNTRL_MASK, 0x8));
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qcom_snps_eusb2_hsphy_write_mask(phy->base, USB_PHY_CFG_CTRL_4,
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PHY_CFG_PLL_GMP_CNTRL_MASK,
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FIELD_PREP(PHY_CFG_PLL_GMP_CNTRL_MASK, 0x1));
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qcom_snps_eusb2_hsphy_write_mask(phy->base, USB_PHY_CFG_CTRL_5,
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PHY_CFG_PLL_PROP_CNTRL_MASK,
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FIELD_PREP(PHY_CFG_PLL_PROP_CNTRL_MASK, 0x10));
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qcom_snps_eusb2_hsphy_write_mask(phy->base, USB_PHY_CFG_CTRL_6,
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PHY_CFG_PLL_VCO_CNTRL_MASK,
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FIELD_PREP(PHY_CFG_PLL_VCO_CNTRL_MASK, 0x0));
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qcom_snps_eusb2_hsphy_write_mask(phy->base, USB_PHY_CFG_CTRL_5,
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PHY_CFG_PLL_VREF_TUNE_MASK,
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FIELD_PREP(PHY_CFG_PLL_VREF_TUNE_MASK, 0x1));
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qcom_snps_eusb2_hsphy_write_mask(phy->base, USB_PHY_HS_PHY_CTRL2,
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VBUS_DET_EXT_SEL, VBUS_DET_EXT_SEL);
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/* set default parameters */
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qcom_eusb2_default_parameters(phy);
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qcom_snps_eusb2_hsphy_write_mask(phy->base, USB_PHY_HS_PHY_CTRL2,
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USB2_SUSPEND_N_SEL | USB2_SUSPEND_N,
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USB2_SUSPEND_N_SEL | USB2_SUSPEND_N);
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qcom_snps_eusb2_hsphy_write_mask(phy->base, USB_PHY_UTMI_CTRL0, SLEEPM, SLEEPM);
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qcom_snps_eusb2_hsphy_write_mask(phy->base, USB_PHY_HS_PHY_CTRL_COMMON0,
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SIDDQ_SEL, SIDDQ_SEL);
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qcom_snps_eusb2_hsphy_write_mask(phy->base, USB_PHY_HS_PHY_CTRL_COMMON0,
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SIDDQ, 0);
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qcom_snps_eusb2_hsphy_write_mask(phy->base, USB_PHY_UTMI_CTRL5, POR, 0);
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qcom_snps_eusb2_hsphy_write_mask(phy->base, USB_PHY_HS_PHY_CTRL2,
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USB2_SUSPEND_N_SEL, 0);
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return 0;
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disable_ref_clk:
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clk_disable_unprepare(phy->ref_clk);
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disable_vreg:
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regulator_bulk_disable(ARRAY_SIZE(phy->vregs), phy->vregs);
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return ret;
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}
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static int qcom_snps_eusb2_hsphy_exit(struct phy *p)
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{
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struct qcom_snps_eusb2_hsphy *phy = phy_get_drvdata(p);
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clk_disable_unprepare(phy->ref_clk);
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regulator_bulk_disable(ARRAY_SIZE(phy->vregs), phy->vregs);
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return 0;
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}
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static const struct phy_ops qcom_snps_eusb2_hsphy_ops = {
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.init = qcom_snps_eusb2_hsphy_init,
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.exit = qcom_snps_eusb2_hsphy_exit,
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.set_mode = qcom_snps_eusb2_hsphy_set_mode,
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.owner = THIS_MODULE,
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};
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static int qcom_snps_eusb2_hsphy_probe(struct platform_device *pdev)
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{
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struct device *dev = &pdev->dev;
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struct qcom_snps_eusb2_hsphy *phy;
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struct phy_provider *phy_provider;
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struct phy *generic_phy;
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int ret, i;
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int num;
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|
||||
phy = devm_kzalloc(dev, sizeof(*phy), GFP_KERNEL);
|
||||
if (!phy)
|
||||
return -ENOMEM;
|
||||
|
||||
phy->base = devm_platform_ioremap_resource(pdev, 0);
|
||||
if (IS_ERR(phy->base))
|
||||
return PTR_ERR(phy->base);
|
||||
|
||||
phy->phy_reset = devm_reset_control_get_exclusive(dev, NULL);
|
||||
if (IS_ERR(phy->phy_reset))
|
||||
return PTR_ERR(phy->phy_reset);
|
||||
|
||||
phy->ref_clk = devm_clk_get(dev, "ref");
|
||||
if (IS_ERR(phy->ref_clk))
|
||||
return dev_err_probe(dev, PTR_ERR(phy->ref_clk),
|
||||
"failed to get ref clk\n");
|
||||
|
||||
num = ARRAY_SIZE(phy->vregs);
|
||||
for (i = 0; i < num; i++)
|
||||
phy->vregs[i].supply = eusb2_hsphy_vreg_names[i];
|
||||
|
||||
ret = devm_regulator_bulk_get(dev, num, phy->vregs);
|
||||
if (ret)
|
||||
return dev_err_probe(dev, ret,
|
||||
"failed to get regulator supplies\n");
|
||||
generic_phy = devm_phy_create(dev, NULL, &qcom_snps_eusb2_hsphy_ops);
|
||||
if (IS_ERR(generic_phy)) {
|
||||
dev_err(dev, "failed to create phy %d\n", ret);
|
||||
return PTR_ERR(generic_phy);
|
||||
}
|
||||
|
||||
dev_set_drvdata(dev, phy);
|
||||
phy_set_drvdata(generic_phy, phy);
|
||||
|
||||
phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);
|
||||
if (IS_ERR(phy_provider))
|
||||
return PTR_ERR(phy_provider);
|
||||
|
||||
dev_info(dev, "Registered Qcom-eUSB2 phy\n");
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static const struct of_device_id qcom_snps_eusb2_hsphy_of_match_table[] = {
|
||||
{ .compatible = "qcom,sm8550-snps-eusb2-phy", },
|
||||
{ },
|
||||
};
|
||||
MODULE_DEVICE_TABLE(of, qcom_snps_eusb2_hsphy_of_match_table);
|
||||
|
||||
static struct platform_driver qcom_snps_eusb2_hsphy_driver = {
|
||||
.probe = qcom_snps_eusb2_hsphy_probe,
|
||||
.driver = {
|
||||
.name = "qcom-snps-eusb2-hsphy",
|
||||
.of_match_table = qcom_snps_eusb2_hsphy_of_match_table,
|
||||
},
|
||||
};
|
||||
|
||||
module_platform_driver(qcom_snps_eusb2_hsphy_driver);
|
||||
MODULE_DESCRIPTION("Qualcomm SNPS eUSB2 HS PHY driver");
|
||||
MODULE_LICENSE("GPL");
|
||||
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