KVM: SVM: Add intercept checks for remaining twobyte instructions
This patch adds intercepts checks for the remaining twobyte instructions to the KVM instruction emulator. Signed-off-by: Joerg Roedel <joerg.roedel@amd.com> Signed-off-by: Avi Kivity <avi@redhat.com>
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d7eb820306
Коммит
8061252ee0
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@ -344,6 +344,8 @@ enum x86_intercept {
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x86_intercept_wbinvd,
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x86_intercept_monitor,
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x86_intercept_mwait,
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x86_intercept_rdmsr,
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x86_intercept_wrmsr,
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nr_x86_intercepts
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};
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@ -2425,12 +2425,9 @@ static int em_cwd(struct x86_emulate_ctxt *ctxt)
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static int em_rdtsc(struct x86_emulate_ctxt *ctxt)
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{
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unsigned cpl = ctxt->ops->cpl(ctxt->vcpu);
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struct decode_cache *c = &ctxt->decode;
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u64 tsc = 0;
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if (cpl > 0 && (ctxt->ops->get_cr(4, ctxt->vcpu) & X86_CR4_TSD))
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return emulate_gp(ctxt, 0);
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ctxt->ops->get_msr(ctxt->vcpu, MSR_IA32_TSC, &tsc);
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c->regs[VCPU_REGS_RAX] = (u32)tsc;
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c->regs[VCPU_REGS_RDX] = tsc >> 32;
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@ -2614,6 +2611,18 @@ static int check_rdtsc(struct x86_emulate_ctxt *ctxt)
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return X86EMUL_CONTINUE;
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}
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static int check_rdpmc(struct x86_emulate_ctxt *ctxt)
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{
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u64 cr4 = ctxt->ops->get_cr(4, ctxt->vcpu);
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u64 rcx = kvm_register_read(ctxt->vcpu, VCPU_REGS_RCX);
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if ((!(cr4 & X86_CR4_PCE) && ctxt->ops->cpl(ctxt->vcpu)) ||
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(rcx > 3))
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return emulate_gp(ctxt, 0);
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return X86EMUL_CONTINUE;
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}
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#define D(_y) { .flags = (_y) }
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#define DI(_y, _i) { .flags = (_y), .intercept = x86_intercept_##_i }
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#define DIP(_y, _i, _p) { .flags = (_y), .intercept = x86_intercept_##_i, \
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@ -2846,8 +2855,10 @@ static struct opcode twobyte_table[256] = {
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N, N, N, N,
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N, N, N, N, N, N, N, N,
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/* 0x30 - 0x3F */
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D(ImplicitOps | Priv), II(ImplicitOps, em_rdtsc, rdtsc),
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D(ImplicitOps | Priv), N,
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DI(ImplicitOps | Priv, wrmsr),
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IIP(ImplicitOps, em_rdtsc, rdtsc, check_rdtsc),
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DI(ImplicitOps | Priv, rdmsr),
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DIP(ImplicitOps | Priv, rdpmc, check_rdpmc),
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D(ImplicitOps | VendorSpecific), D(ImplicitOps | Priv | VendorSpecific),
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N, N,
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N, N, N, N, N, N, N, N,
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@ -2871,12 +2882,12 @@ static struct opcode twobyte_table[256] = {
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X16(D(ByteOp | DstMem | SrcNone | ModRM| Mov)),
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/* 0xA0 - 0xA7 */
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D(ImplicitOps | Stack), D(ImplicitOps | Stack),
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N, D(DstMem | SrcReg | ModRM | BitOp),
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DI(ImplicitOps, cpuid), D(DstMem | SrcReg | ModRM | BitOp),
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D(DstMem | SrcReg | Src2ImmByte | ModRM),
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D(DstMem | SrcReg | Src2CL | ModRM), N, N,
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/* 0xA8 - 0xAF */
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D(ImplicitOps | Stack), D(ImplicitOps | Stack),
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N, D(DstMem | SrcReg | ModRM | BitOp | Lock),
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DI(ImplicitOps, rsm), D(DstMem | SrcReg | ModRM | BitOp | Lock),
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D(DstMem | SrcReg | Src2ImmByte | ModRM),
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D(DstMem | SrcReg | Src2CL | ModRM),
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D(ModRM), I(DstReg | SrcMem | ModRM, em_imul),
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@ -3868,6 +3868,9 @@ static void svm_fpu_deactivate(struct kvm_vcpu *vcpu)
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update_cr0_intercept(svm);
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}
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#define PRE_EX(exit) { .exit_code = (exit), \
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.stage = X86_ICPT_PRE_EXCEPT, \
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.valid = true }
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#define POST_EX(exit) { .exit_code = (exit), \
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.stage = X86_ICPT_POST_EXCEPT, \
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.valid = true }
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@ -3906,8 +3909,18 @@ static struct __x86_intercept {
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[x86_intercept_rdtscp] = POST_EX(SVM_EXIT_RDTSCP),
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[x86_intercept_monitor] = POST_MEM(SVM_EXIT_MONITOR),
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[x86_intercept_mwait] = POST_EX(SVM_EXIT_MWAIT),
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[x86_intercept_invlpg] = POST_EX(SVM_EXIT_INVLPG),
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[x86_intercept_invd] = POST_EX(SVM_EXIT_INVD),
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[x86_intercept_wbinvd] = POST_EX(SVM_EXIT_WBINVD),
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[x86_intercept_wrmsr] = POST_EX(SVM_EXIT_MSR),
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[x86_intercept_rdtsc] = POST_EX(SVM_EXIT_RDTSC),
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[x86_intercept_rdmsr] = POST_EX(SVM_EXIT_MSR),
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[x86_intercept_rdpmc] = POST_EX(SVM_EXIT_RDPMC),
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[x86_intercept_cpuid] = PRE_EX(SVM_EXIT_CPUID),
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[x86_intercept_rsm] = PRE_EX(SVM_EXIT_RSM),
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};
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#undef PRE_EX
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#undef POST_EX
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#undef POST_MEM
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@ -3968,6 +3981,12 @@ static int svm_check_intercept(struct kvm_vcpu *vcpu,
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case SVM_EXIT_WRITE_DR0:
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icpt_info.exit_code += info->modrm_reg;
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break;
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case SVM_EXIT_MSR:
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if (info->intercept == x86_intercept_wrmsr)
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vmcb->control.exit_info_1 = 1;
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else
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vmcb->control.exit_info_1 = 0;
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break;
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default:
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break;
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}
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