spi: pxa2xx: Fix style of and typos in the comments and messages
Fix style of the comments and messages along with typos in them. While at it, update Intel Copyright year. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Link: https://lore.kernel.org/r/20210517140351.901-8-andriy.shevchenko@linux.intel.com Signed-off-by: Mark Brown <broonie@kernel.org>
This commit is contained in:
Andy Shevchenko
Mark Brown
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684a3ac720
Коммит
8083d6b812
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@ -2,7 +2,7 @@
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/*
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* PXA2xx SPI DMA engine support.
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*
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* Copyright (C) 2013, Intel Corporation
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* Copyright (C) 2013, 2021 Intel Corporation
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* Author: Mika Westerberg <mika.westerberg@linux.intel.com>
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*/
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@ -26,7 +26,7 @@ static void pxa2xx_spi_dma_transfer_complete(struct driver_data *drv_data,
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* It is possible that one CPU is handling ROR interrupt and other
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* just gets DMA completion. Calling pump_transfers() twice for the
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* same transfer leads to problems thus we prevent concurrent calls
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* by using ->dma_running.
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* by using dma_running.
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*/
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if (atomic_dec_and_test(&drv_data->dma_running)) {
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/*
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@ -1,8 +1,9 @@
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// SPDX-License-Identifier: GPL-2.0-only
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/*
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* CE4100's SPI device is more or less the same one as found on PXA
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* PCI glue driver for SPI PXA2xx compatible controllers.
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* CE4100's SPI device is more or less the same one as found on PXA.
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*
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* Copyright (C) 2016, Intel Corporation
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* Copyright (C) 2016, 2021 Intel Corporation
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*/
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#include <linux/clk-provider.h>
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#include <linux/module.h>
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@ -1,7 +1,7 @@
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// SPDX-License-Identifier: GPL-2.0-or-later
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/*
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* Copyright (C) 2005 Stephen Street / StreetFire Sound Labs
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* Copyright (C) 2013, Intel Corporation
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* Copyright (C) 2013, 2021 Intel Corporation
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*/
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#include <linux/acpi.h>
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@ -40,11 +40,11 @@ MODULE_ALIAS("platform:pxa2xx-spi");
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#define TIMOUT_DFLT 1000
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/*
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* for testing SSCR1 changes that require SSP restart, basically
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* everything except the service and interrupt enables, the pxa270 developer
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* For testing SSCR1 changes that require SSP restart, basically
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* everything except the service and interrupt enables, the PXA270 developer
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* manual says only SSCR1_SCFR, SSCR1_SPH, SSCR1_SPO need to be in this
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* list, but the PXA255 dev man says all bits without really meaning the
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* service and interrupt enables
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* list, but the PXA255 developer manual says all bits without really meaning
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* the service and interrupt enables.
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*/
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#define SSCR1_CHANGE_MASK (SSCR1_TTELP | SSCR1_TTE | SSCR1_SCFR \
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| SSCR1_ECRA | SSCR1_ECRB | SSCR1_SCLKDIR \
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@ -653,12 +653,12 @@ static irqreturn_t interrupt_transfer(struct driver_data *drv_data)
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irq_status &= ~SSSR_TFS;
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if (irq_status & SSSR_ROR) {
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int_error_stop(drv_data, "interrupt_transfer: fifo overrun", -EIO);
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int_error_stop(drv_data, "interrupt_transfer: FIFO overrun", -EIO);
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return IRQ_HANDLED;
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}
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if (irq_status & SSSR_TUR) {
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int_error_stop(drv_data, "interrupt_transfer: fifo underrun", -EIO);
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int_error_stop(drv_data, "interrupt_transfer: FIFO underrun", -EIO);
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return IRQ_HANDLED;
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}
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@ -670,7 +670,7 @@ static irqreturn_t interrupt_transfer(struct driver_data *drv_data)
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}
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}
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/* Drain rx fifo, Fill tx fifo and prevent overruns */
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/* Drain Rx FIFO, Fill Tx FIFO and prevent overruns */
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do {
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if (drv_data->read(drv_data)) {
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int_transfer_complete(drv_data);
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@ -691,8 +691,8 @@ static irqreturn_t interrupt_transfer(struct driver_data *drv_data)
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sccr1_reg &= ~SSCR1_TIE;
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/*
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* PXA25x_SSP has no timeout, set up rx threshould for the
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* remaining RX bytes.
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* PXA25x_SSP has no timeout, set up Rx threshold for
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* the remaining Rx bytes.
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*/
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if (pxa25x_ssp_comp(drv_data)) {
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u32 rx_thre;
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@ -914,7 +914,7 @@ static unsigned int ssp_get_clk_div(struct driver_data *drv_data, int rate)
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/*
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* Calculate the divisor for the SCR (Serial Clock Rate), avoiding
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* that the SSP transmission rate can be greater than the device rate
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* that the SSP transmission rate can be greater than the device rate.
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*/
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if (ssp->type == PXA25x_SSP || ssp->type == CE4100_SSP)
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return (DIV_ROUND_UP(ssp_clk, 2 * rate) - 1) & 0xff;
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@ -972,7 +972,7 @@ static int pxa2xx_spi_transfer_one(struct spi_controller *controller,
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/* Check if we can DMA this transfer */
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if (transfer->len > MAX_DMA_LEN && chip->enable_dma) {
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/* reject already-mapped transfers; PIO won't always work */
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/* Reject already-mapped transfers; PIO won't always work */
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if (message->is_dma_mapped
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|| transfer->rx_dma || transfer->tx_dma) {
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dev_err(&spi->dev,
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@ -981,7 +981,7 @@ static int pxa2xx_spi_transfer_one(struct spi_controller *controller,
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return -EINVAL;
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}
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/* warn ... we force this to PIO mode */
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/* Warn ... we force this to PIO mode */
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dev_warn_ratelimited(&spi->dev,
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"DMA disabled for transfer length %u greater than %d\n",
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transfer->len, MAX_DMA_LEN);
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@ -1026,8 +1026,8 @@ static int pxa2xx_spi_transfer_one(struct spi_controller *controller,
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u32_writer : null_writer;
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}
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/*
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* if bits/word is changed in dma mode, then must check the
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* thresholds and burst also
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* If bits per word is changed in DMA mode, then must check
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* the thresholds and burst also.
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*/
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if (chip->enable_dma) {
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if (pxa2xx_spi_set_dma_burst_and_threshold(chip,
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@ -1101,10 +1101,10 @@ static int pxa2xx_spi_transfer_one(struct spi_controller *controller,
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if (!pxa25x_ssp_comp(drv_data))
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pxa2xx_spi_write(drv_data, SSTO, chip->timeout);
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/* first set CR1 without interrupt and service enables */
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/* First set CR1 without interrupt and service enables */
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pxa2xx_spi_update(drv_data, SSCR1, change_mask, cr1);
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/* see if we need to reload the config registers */
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/* See if we need to reload the configuration registers */
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pxa2xx_spi_update(drv_data, SSCR0, GENMASK(31, 0), cr0);
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/* Restart the SSP */
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@ -1114,7 +1114,7 @@ static int pxa2xx_spi_transfer_one(struct spi_controller *controller,
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u8 tx_level = read_SSSR_bits(drv_data, SSSR_TFL_MASK) >> 8;
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if (tx_level) {
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/* On MMP2, flipping SSE doesn't to empty TXFIFO. */
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/* On MMP2, flipping SSE doesn't to empty Tx FIFO. */
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dev_warn(&spi->dev, "%u bytes of garbage in Tx FIFO!\n", tx_level);
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if (tx_level > transfer->len)
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tx_level = transfer->len;
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@ -1134,7 +1134,7 @@ static int pxa2xx_spi_transfer_one(struct spi_controller *controller,
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/*
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* Release the data by enabling service requests and interrupts,
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* without changing any mode bits
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* without changing any mode bits.
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*/
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pxa2xx_spi_write(drv_data, SSCR1, cr1);
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@ -1207,12 +1207,13 @@ static int setup_cs(struct spi_device *spi, struct chip_data *chip,
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if (drv_data->ssp_type == CE4100_SSP)
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return 0;
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/* NOTE: setup() can be called multiple times, possibly with
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* different chip_info, release previously requested GPIO
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/*
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* NOTE: setup() can be called multiple times, possibly with
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* different chip_info, release previously requested GPIO.
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*/
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cleanup_cs(spi);
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/* If (*cs_control) is provided, ignore GPIO chip select */
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/* If ->cs_control() is provided, ignore GPIO chip select */
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if (chip_info->cs_control) {
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chip->cs_control = chip_info->cs_control;
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return 0;
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@ -1288,7 +1289,7 @@ static int setup(struct spi_device *spi)
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break;
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}
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/* Only alloc on first setup */
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/* Only allocate on the first setup */
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chip = spi_get_ctldata(spi);
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if (!chip) {
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chip = kzalloc(sizeof(struct chip_data), GFP_KERNEL);
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@ -1307,8 +1308,10 @@ static int setup(struct spi_device *spi)
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chip->timeout = TIMOUT_DFLT;
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}
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/* protocol drivers may change the chip settings, so...
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* if chip_info exists, use it */
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/*
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* Protocol drivers may change the chip settings, so...
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* if chip_info exists, use it.
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*/
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chip_info = spi->controller_data;
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/* chip_info isn't always needed */
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@ -1344,11 +1347,13 @@ static int setup(struct spi_device *spi)
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chip->lpss_tx_threshold = tx_thres;
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}
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/* set dma burst and threshold outside of chip_info path so that if
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* chip_info goes away after setting chip->enable_dma, the
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* burst and threshold can still respond to changes in bits_per_word */
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/*
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* Set DMA burst and threshold outside of chip_info path so that if
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* chip_info goes away after setting chip->enable_dma, the burst and
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* threshold can still respond to changes in bits_per_word.
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*/
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if (chip->enable_dma) {
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/* set up legal burst and threshold for dma */
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/* Set up legal burst and threshold for DMA */
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if (pxa2xx_spi_set_dma_burst_and_threshold(chip, spi,
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spi->bits_per_word,
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&chip->dma_burst_size,
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@ -1677,7 +1682,7 @@ static int pxa2xx_spi_probe(struct platform_device *pdev)
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ssp = &platform_info->ssp;
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if (!ssp->mmio_base) {
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dev_err(&pdev->dev, "failed to get ssp\n");
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dev_err(&pdev->dev, "failed to get SSP\n");
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return -ENODEV;
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}
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@ -1699,7 +1704,7 @@ static int pxa2xx_spi_probe(struct platform_device *pdev)
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controller->dev.of_node = dev->of_node;
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controller->dev.fwnode = dev->fwnode;
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/* the spi->mode bits understood by this driver: */
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/* The spi->mode bits understood by this driver: */
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controller->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH | SPI_LOOP;
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controller->bus_num = ssp->port_id;
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@ -1787,7 +1792,7 @@ static int pxa2xx_spi_probe(struct platform_device *pdev)
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QUARK_X1000_SSCR1_TxTresh(TX_THRESH_QUARK_X1000_DFLT);
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pxa2xx_spi_write(drv_data, SSCR1, tmp);
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/* using the Motorola SPI protocol and use 8 bit frame */
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/* Using the Motorola SPI protocol and use 8 bit frame */
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tmp = QUARK_X1000_SSCR0_Motorola | QUARK_X1000_SSCR0_DataSize(8);
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pxa2xx_spi_write(drv_data, SSCR0, tmp);
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break;
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@ -1859,7 +1864,7 @@ static int pxa2xx_spi_probe(struct platform_device *pdev)
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platform_set_drvdata(pdev, drv_data);
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status = spi_register_controller(controller);
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if (status) {
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dev_err(&pdev->dev, "problem registering spi controller\n");
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dev_err(&pdev->dev, "problem registering SPI controller\n");
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goto out_error_pm_runtime_enabled;
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}
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@ -1,7 +1,7 @@
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/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* Copyright (C) 2005 Stephen Street / StreetFire Sound Labs
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* Copyright (C) 2013, Intel Corporation
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* Copyright (C) 2013, 2021 Intel Corporation
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*/
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#ifndef SPI_PXA2XX_H
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@ -1,6 +1,6 @@
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/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* Copyright (C) 2003 Russell King, All Rights Reserved.
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* Copyright (C) 2003 Russell King, All Rights Reserved.
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*
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* This driver supports the following PXA CPU/SSP ports:-
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*
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@ -59,7 +59,7 @@ struct device_node;
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/* PXA27x, PXA3xx */
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#define SSCR0_EDSS BIT(20) /* Extended data size select */
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#define SSCR0_NCS BIT(21) /* Network clock select */
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#define SSCR0_RIM BIT(22) /* Receive FIFO overrrun interrupt mask */
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#define SSCR0_RIM BIT(22) /* Receive FIFO overrun interrupt mask */
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#define SSCR0_TUM BIT(23) /* Transmit FIFO underrun interrupt mask */
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#define SSCR0_FRDC GENMASK(26, 24) /* Frame rate divider control (mask) */
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#define SSCR0_SlotsPerFrm(x) (((x) - 1) << 24) /* Time slots per frame [1..8] */
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@ -126,7 +126,7 @@ struct device_node;
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#define QUARK_X1000_SSCR1_EFWR BIT(16) /* Enable FIFO Write/Read */
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#define QUARK_X1000_SSCR1_STRF BIT(17) /* Select FIFO or EFWR */
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/* extra bits in PXA255, PXA26x and PXA27x SSP ports */
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/* Extra bits in PXA255, PXA26x and PXA27x SSP ports */
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#define SSCR0_TISSP (1 << 4) /* TI Sync Serial Protocol */
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#define SSCR0_PSP (3 << 4) /* PSP - Programmable Serial Protocol */
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@ -222,7 +222,8 @@ enum pxa_ssp_type {
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CE4100_SSP,
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MRFLD_SSP,
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QUARK_X1000_SSP,
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LPSS_LPT_SSP, /* Keep LPSS types sorted with lpss_platforms[] */
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/* Keep LPSS types sorted with lpss_platforms[] */
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LPSS_LPT_SSP,
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LPSS_BYT_SSP,
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LPSS_BSW_SSP,
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LPSS_SPT_SSP,
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@ -14,7 +14,10 @@
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struct dma_chan;
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/* device.platform_data for SSP controller devices */
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/*
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* The platform data for SSP controller devices
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* (resides in device.platform_data).
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*/
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struct pxa2xx_spi_controller {
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u16 num_chipselect;
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u8 enable_dma;
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@ -30,8 +33,11 @@ struct pxa2xx_spi_controller {
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struct ssp_device ssp;
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};
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/* spi_board_info.controller_data for SPI slave devices,
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* copied to spi_device.platform_data ... mostly for dma tuning
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/*
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* The controller specific data for SPI slave devices
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* (resides in spi_board_info.controller_data),
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* copied to spi_device.platform_data ... mostly for
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* DMA tuning.
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*/
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struct pxa2xx_spi_chip {
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u8 tx_threshold;
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