irqchip update for 5.0-rc6
- Another GICv3 ITS fix for devices sharing the same DevID - Don't return invalid data on exhaustion of the GICv3 LPI pool - Fix a GICv3 field decoding bug leading to memory over-allocation - Init GICv4 at boot time instead of lazy init - Fix interrupt masking on PJ4 -----BEGIN PGP SIGNATURE----- iQJJBAABCgAzFiEEn9UcU+C1Yxj9lZw9I9DQutE9ekMFAlxaspYVHG1hcmMuenlu Z2llckBhcm0uY29tAAoJECPQ0LrRPXpDMS8QAIUNTdbpgtCc/3Lr4n1qHlzGCR1N n4FHYgpR1txcPcVyu92jLxEwnlzSw2zjexuqUNaUYVUKe6wzEAXpDba+dDhvLrW5 JfT1RE7cDMWu34iKAorGg1sqAb3yl67d6Oi88abbNdv3zSa9EVyVBRp3eTWotNzg EAtVorirI41CZNirt3ZU0TRMX0wAc5g7HTq0AwBcQSsg0P6ZCyVqZU5w/JNsPzWH VIpYue8XlDNQ8SDJHRppHhyrghVHG0tpSHKo9I8cA9+4CK6CMd8OwZhdNsf2ISiL vcEOyuOQfIIyTry59F11eiwlMNa4nmsLlmzezOZUeb3NafxsqMmDsbjbOiDMIkzh WUt8BlWOSyy2sWlokX3Qu9CLlWxa+QydGokNdUufLYOAVQG+VDUD5lpaposUSNAe 0thGXenlBO43NqTdldZu2L6E0Wb0M0CTuILOSg6M+6olTR5hsGJiUaV+3WLJHQi3 gLzbAFu5JRzpJWqOPh/9pF5dQQIZ8Ls/C2oJlYt+CTiYA3je4pzWzEsmP2CBTYUy WZEq/mhcze0kFu2b7FnYNhvYkSPool4t5GajwoBYb34N2rnJa7KVYsBDAV0gUJ1t MZbTTzWUeWpsm31uZlvKiPSDHqpUPucZ9HtqBH8OKef6IZz4tMK7v9qx1yZ/C2ZL dSNbXHBEI7X44Ea2 =Crvb -----END PGP SIGNATURE----- Merge tag 'irqchip-5.0-3' of git://git.kernel.org/pub/scm/linux/kernel/git/maz/arm-platforms into irq/urgent Pull irqchip updates from Marc Zyngier: - Another GICv3 ITS fix for devices sharing the same DevID - Don't return invalid data on exhaustion of the GICv3 LPI pool - Fix a GICv3 field decoding bug leading to memory over-allocation - Init GICv4 at boot time instead of lazy init - Fix interrupt masking on PJ4
This commit is contained in:
Thomas Gleixner
Коммит
8087f40736
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@ -97,9 +97,14 @@ struct its_device;
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* The ITS structure - contains most of the infrastructure, with the
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* top-level MSI domain, the command queue, the collections, and the
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* list of devices writing to it.
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*
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* dev_alloc_lock has to be taken for device allocations, while the
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* spinlock must be taken to parse data structures such as the device
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* list.
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*/
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struct its_node {
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raw_spinlock_t lock;
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struct mutex dev_alloc_lock;
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struct list_head entry;
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void __iomem *base;
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phys_addr_t phys_base;
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@ -156,6 +161,7 @@ struct its_device {
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void *itt;
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u32 nr_ites;
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u32 device_id;
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bool shared;
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};
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static struct {
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@ -1580,6 +1586,9 @@ static unsigned long *its_lpi_alloc(int nr_irqs, u32 *base, int *nr_ids)
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nr_irqs /= 2;
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} while (nr_irqs > 0);
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if (!nr_irqs)
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err = -ENOSPC;
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if (err)
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goto out;
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@ -2059,6 +2068,29 @@ static int __init allocate_lpi_tables(void)
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return 0;
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}
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static u64 its_clear_vpend_valid(void __iomem *vlpi_base)
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{
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u32 count = 1000000; /* 1s! */
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bool clean;
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u64 val;
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val = gits_read_vpendbaser(vlpi_base + GICR_VPENDBASER);
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val &= ~GICR_VPENDBASER_Valid;
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gits_write_vpendbaser(val, vlpi_base + GICR_VPENDBASER);
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do {
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val = gits_read_vpendbaser(vlpi_base + GICR_VPENDBASER);
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clean = !(val & GICR_VPENDBASER_Dirty);
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if (!clean) {
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count--;
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cpu_relax();
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udelay(1);
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}
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} while (!clean && count);
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return val;
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}
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static void its_cpu_init_lpis(void)
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{
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void __iomem *rbase = gic_data_rdist_rd_base();
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@ -2144,6 +2176,30 @@ static void its_cpu_init_lpis(void)
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val |= GICR_CTLR_ENABLE_LPIS;
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writel_relaxed(val, rbase + GICR_CTLR);
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if (gic_rdists->has_vlpis) {
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void __iomem *vlpi_base = gic_data_rdist_vlpi_base();
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/*
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* It's possible for CPU to receive VLPIs before it is
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* sheduled as a vPE, especially for the first CPU, and the
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* VLPI with INTID larger than 2^(IDbits+1) will be considered
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* as out of range and dropped by GIC.
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* So we initialize IDbits to known value to avoid VLPI drop.
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*/
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val = (LPI_NRBITS - 1) & GICR_VPROPBASER_IDBITS_MASK;
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pr_debug("GICv4: CPU%d: Init IDbits to 0x%llx for GICR_VPROPBASER\n",
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smp_processor_id(), val);
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gits_write_vpropbaser(val, vlpi_base + GICR_VPROPBASER);
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/*
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* Also clear Valid bit of GICR_VPENDBASER, in case some
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* ancient programming gets left in and has possibility of
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* corrupting memory.
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*/
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val = its_clear_vpend_valid(vlpi_base);
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WARN_ON(val & GICR_VPENDBASER_Dirty);
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}
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/* Make sure the GIC has seen the above */
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dsb(sy);
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out:
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@ -2422,6 +2478,7 @@ static int its_msi_prepare(struct irq_domain *domain, struct device *dev,
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struct its_device *its_dev;
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struct msi_domain_info *msi_info;
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u32 dev_id;
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int err = 0;
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/*
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* We ignore "dev" entierely, and rely on the dev_id that has
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@ -2444,6 +2501,7 @@ static int its_msi_prepare(struct irq_domain *domain, struct device *dev,
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return -EINVAL;
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}
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mutex_lock(&its->dev_alloc_lock);
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its_dev = its_find_device(its, dev_id);
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if (its_dev) {
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/*
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@ -2451,18 +2509,22 @@ static int its_msi_prepare(struct irq_domain *domain, struct device *dev,
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* another alias (PCI bridge of some sort). No need to
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* create the device.
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*/
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its_dev->shared = true;
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pr_debug("Reusing ITT for devID %x\n", dev_id);
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goto out;
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}
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its_dev = its_create_device(its, dev_id, nvec, true);
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if (!its_dev)
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return -ENOMEM;
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if (!its_dev) {
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err = -ENOMEM;
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goto out;
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}
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pr_debug("ITT %d entries, %d bits\n", nvec, ilog2(nvec));
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out:
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mutex_unlock(&its->dev_alloc_lock);
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info->scratchpad[0].ptr = its_dev;
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return 0;
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return err;
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}
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static struct msi_domain_ops its_msi_domain_ops = {
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@ -2566,6 +2628,7 @@ static void its_irq_domain_free(struct irq_domain *domain, unsigned int virq,
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{
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struct irq_data *d = irq_domain_get_irq_data(domain, virq);
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struct its_device *its_dev = irq_data_get_irq_chip_data(d);
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struct its_node *its = its_dev->its;
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int i;
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for (i = 0; i < nr_irqs; i++) {
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@ -2580,8 +2643,14 @@ static void its_irq_domain_free(struct irq_domain *domain, unsigned int virq,
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irq_domain_reset_irq_data(data);
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}
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/* If all interrupts have been freed, start mopping the floor */
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if (bitmap_empty(its_dev->event_map.lpi_map,
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mutex_lock(&its->dev_alloc_lock);
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/*
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* If all interrupts have been freed, start mopping the
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* floor. This is conditionned on the device not being shared.
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*/
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if (!its_dev->shared &&
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bitmap_empty(its_dev->event_map.lpi_map,
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its_dev->event_map.nr_lpis)) {
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its_lpi_free(its_dev->event_map.lpi_map,
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its_dev->event_map.lpi_base,
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@ -2593,6 +2662,8 @@ static void its_irq_domain_free(struct irq_domain *domain, unsigned int virq,
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its_free_device(its_dev);
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}
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mutex_unlock(&its->dev_alloc_lock);
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irq_domain_free_irqs_parent(domain, virq, nr_irqs);
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}
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@ -2755,26 +2826,11 @@ static void its_vpe_schedule(struct its_vpe *vpe)
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static void its_vpe_deschedule(struct its_vpe *vpe)
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{
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void __iomem *vlpi_base = gic_data_rdist_vlpi_base();
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u32 count = 1000000; /* 1s! */
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bool clean;
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u64 val;
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/* We're being scheduled out */
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val = gits_read_vpendbaser(vlpi_base + GICR_VPENDBASER);
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val &= ~GICR_VPENDBASER_Valid;
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gits_write_vpendbaser(val, vlpi_base + GICR_VPENDBASER);
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val = its_clear_vpend_valid(vlpi_base);
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do {
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val = gits_read_vpendbaser(vlpi_base + GICR_VPENDBASER);
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clean = !(val & GICR_VPENDBASER_Dirty);
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if (!clean) {
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count--;
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cpu_relax();
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udelay(1);
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}
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} while (!clean && count);
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if (unlikely(!clean && !count)) {
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if (unlikely(val & GICR_VPENDBASER_Dirty)) {
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pr_err_ratelimited("ITS virtual pending table not cleaning\n");
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vpe->idai = false;
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vpe->pending_last = true;
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@ -3517,6 +3573,7 @@ static int __init its_probe_one(struct resource *res,
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}
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raw_spin_lock_init(&its->lock);
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mutex_init(&its->dev_alloc_lock);
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INIT_LIST_HEAD(&its->entry);
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INIT_LIST_HEAD(&its->its_device_list);
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typer = gic_read_typer(its_base + GITS_TYPER);
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@ -34,6 +34,9 @@
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#define SEL_INT_PENDING (1 << 6)
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#define SEL_INT_NUM_MASK 0x3f
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#define MMP2_ICU_INT_ROUTE_PJ4_IRQ (1 << 5)
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#define MMP2_ICU_INT_ROUTE_PJ4_FIQ (1 << 6)
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struct icu_chip_data {
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int nr_irqs;
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unsigned int virq_base;
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@ -190,7 +193,8 @@ static const struct mmp_intc_conf mmp_conf = {
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static const struct mmp_intc_conf mmp2_conf = {
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.conf_enable = 0x20,
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.conf_disable = 0x0,
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.conf_mask = 0x7f,
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.conf_mask = MMP2_ICU_INT_ROUTE_PJ4_IRQ |
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MMP2_ICU_INT_ROUTE_PJ4_FIQ,
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};
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static void __exception_irq_entry mmp_handle_irq(struct pt_regs *regs)
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@ -319,7 +319,7 @@
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#define GITS_TYPER_PLPIS (1UL << 0)
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#define GITS_TYPER_VLPIS (1UL << 1)
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#define GITS_TYPER_ITT_ENTRY_SIZE_SHIFT 4
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#define GITS_TYPER_ITT_ENTRY_SIZE(r) ((((r) >> GITS_TYPER_ITT_ENTRY_SIZE_SHIFT) & 0x1f) + 1)
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#define GITS_TYPER_ITT_ENTRY_SIZE(r) ((((r) >> GITS_TYPER_ITT_ENTRY_SIZE_SHIFT) & 0xf) + 1)
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#define GITS_TYPER_IDBITS_SHIFT 8
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#define GITS_TYPER_DEVBITS_SHIFT 13
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#define GITS_TYPER_DEVBITS(r) ((((r) >> GITS_TYPER_DEVBITS_SHIFT) & 0x1f) + 1)
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