pinctrl/at91: convert driver to use gpiolib irqchip
This converts the AT91 pin control driver to register its chained irq handler and irqchip using the helpers in the gpiolib core. Signed-off-by: Alexander Stein <alexanders83@web.de> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
This commit is contained in:
Alexander Stein
Linus Walleij
Родитель
443ac95302
Коммит
80cc37329d
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@ -84,6 +84,9 @@ config PINCTRL_AT91
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depends on ARCH_AT91
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select PINMUX
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select PINCONF
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select GPIOLIB
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select OF_GPIO
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select GPIOLIB_IRQCHIP
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help
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Say Y here to enable the at91 pinctrl driver
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@ -16,9 +16,6 @@
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#include <linux/of_irq.h>
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#include <linux/slab.h>
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#include <linux/interrupt.h>
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#include <linux/irq.h>
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#include <linux/irqdomain.h>
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#include <linux/irqchip/chained_irq.h>
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#include <linux/io.h>
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#include <linux/gpio.h>
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#include <linux/pinctrl/machine.h>
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@ -47,7 +44,6 @@ struct at91_gpio_chip {
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int pioc_idx; /* PIO bank index */
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void __iomem *regbase; /* PIO bank virtual address */
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struct clk *clock; /* associated clock */
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struct irq_domain *domain; /* associated irq domain */
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struct at91_pinctrl_mux_ops *ops; /* ops */
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};
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@ -1192,21 +1188,6 @@ static int at91_gpio_direction_output(struct gpio_chip *chip, unsigned offset,
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return 0;
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}
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static int at91_gpio_to_irq(struct gpio_chip *chip, unsigned offset)
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{
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struct at91_gpio_chip *at91_gpio = to_at91_gpio_chip(chip);
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int virq;
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if (offset < chip->ngpio)
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virq = irq_create_mapping(at91_gpio->domain, offset);
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else
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virq = -ENXIO;
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dev_dbg(chip->dev, "%s: request IRQ for GPIO %d, return %d\n",
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chip->label, offset + chip->base, virq);
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return virq;
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}
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#ifdef CONFIG_DEBUG_FS
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static void at91_gpio_dbg_show(struct seq_file *s, struct gpio_chip *chip)
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{
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@ -1336,6 +1317,11 @@ static int alt_gpio_irq_type(struct irq_data *d, unsigned type)
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return 0;
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}
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static void gpio_irq_ack(struct irq_data *d)
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{
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/* the interrupt is already cleared before by reading ISR */
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}
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static unsigned int gpio_irq_startup(struct irq_data *d)
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{
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struct at91_gpio_chip *at91_gpio = irq_data_get_irq_chip_data(d);
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@ -1435,6 +1421,7 @@ void at91_pinctrl_gpio_resume(void)
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static struct irq_chip gpio_irqchip = {
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.name = "GPIO",
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.irq_ack = gpio_irq_ack,
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.irq_startup = gpio_irq_startup,
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.irq_shutdown = gpio_irq_shutdown,
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.irq_disable = gpio_irq_mask,
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@ -1446,9 +1433,11 @@ static struct irq_chip gpio_irqchip = {
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static void gpio_irq_handler(unsigned irq, struct irq_desc *desc)
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{
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struct irq_chip *chip = irq_desc_get_chip(desc);
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struct irq_data *idata = irq_desc_get_irq_data(desc);
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struct at91_gpio_chip *at91_gpio = irq_data_get_irq_chip_data(idata);
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struct irq_chip *chip = irq_get_chip(irq);
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struct gpio_chip *gpio_chip = irq_desc_get_handler_data(desc);
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struct at91_gpio_chip *at91_gpio = container_of(gpio_chip,
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struct at91_gpio_chip, chip);
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void __iomem *pio = at91_gpio->regbase;
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unsigned long isr;
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int n;
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@ -1469,81 +1458,19 @@ static void gpio_irq_handler(unsigned irq, struct irq_desc *desc)
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}
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for_each_set_bit(n, &isr, BITS_PER_LONG) {
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generic_handle_irq(irq_find_mapping(at91_gpio->domain, n));
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generic_handle_irq(irq_find_mapping(
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gpio_chip->irqdomain, n));
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}
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}
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chained_irq_exit(chip, desc);
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/* now it may re-trigger */
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}
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/*
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* This lock class tells lockdep that GPIO irqs are in a different
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* category than their parents, so it won't report false recursion.
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*/
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static struct lock_class_key gpio_lock_class;
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static int at91_gpio_irq_map(struct irq_domain *h, unsigned int virq,
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irq_hw_number_t hw)
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{
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struct at91_gpio_chip *at91_gpio = h->host_data;
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void __iomem *pio = at91_gpio->regbase;
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u32 mask = 1 << hw;
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irq_set_lockdep_class(virq, &gpio_lock_class);
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/*
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* Can use the "simple" and not "edge" handler since it's
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* shorter, and the AIC handles interrupts sanely.
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*/
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irq_set_chip(virq, &gpio_irqchip);
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if ((at91_gpio->ops == &at91sam9x5_ops) &&
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(readl_relaxed(pio + PIO_AIMMR) & mask) &&
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(readl_relaxed(pio + PIO_ELSR) & mask))
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irq_set_handler(virq, handle_level_irq);
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else
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irq_set_handler(virq, handle_simple_irq);
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set_irq_flags(virq, IRQF_VALID);
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irq_set_chip_data(virq, at91_gpio);
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return 0;
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}
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static int at91_gpio_irq_domain_xlate(struct irq_domain *d,
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struct device_node *ctrlr,
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const u32 *intspec, unsigned int intsize,
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irq_hw_number_t *out_hwirq,
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unsigned int *out_type)
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{
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struct at91_gpio_chip *at91_gpio = d->host_data;
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int ret;
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int pin = at91_gpio->chip.base + intspec[0];
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if (WARN_ON(intsize < 2))
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return -EINVAL;
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*out_hwirq = intspec[0];
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*out_type = intspec[1] & IRQ_TYPE_SENSE_MASK;
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ret = gpio_request(pin, ctrlr->full_name);
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if (ret)
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return ret;
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ret = gpio_direction_input(pin);
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if (ret)
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return ret;
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return 0;
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}
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static struct irq_domain_ops at91_gpio_ops = {
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.map = at91_gpio_irq_map,
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.xlate = at91_gpio_irq_domain_xlate,
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};
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static int at91_gpio_of_irq_setup(struct device_node *node,
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struct at91_gpio_chip *at91_gpio)
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{
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struct at91_gpio_chip *prev = NULL;
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struct irq_data *d = irq_get_irq_data(at91_gpio->pioc_virq);
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int ret;
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at91_gpio->pioc_hwirq = irqd_to_hwirq(d);
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@ -1553,26 +1480,25 @@ static int at91_gpio_of_irq_setup(struct device_node *node,
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/* Disable irqs of this PIO controller */
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writel_relaxed(~0, at91_gpio->regbase + PIO_IDR);
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/* Setup irq domain */
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at91_gpio->domain = irq_domain_add_linear(node, at91_gpio->chip.ngpio,
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&at91_gpio_ops, at91_gpio);
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if (!at91_gpio->domain)
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/*
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* Let the generic code handle this edge IRQ, the the chained
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* handler will perform the actual work of handling the parent
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* interrupt.
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*/
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ret = gpiochip_irqchip_add(&at91_gpio->chip,
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&gpio_irqchip,
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0,
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handle_edge_irq,
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IRQ_TYPE_EDGE_BOTH);
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if (ret)
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panic("at91_gpio.%d: couldn't allocate irq domain (DT).\n",
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at91_gpio->pioc_idx);
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/* Setup chained handler */
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if (at91_gpio->pioc_idx)
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prev = gpio_chips[at91_gpio->pioc_idx - 1];
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/* The top level handler handles one bank of GPIOs, except
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* on some SoC it can handle up to three...
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* We only set up the handler for the first of the list.
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*/
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if (prev && prev->next == at91_gpio)
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return 0;
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irq_set_chip_data(at91_gpio->pioc_virq, at91_gpio);
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irq_set_chained_handler(at91_gpio->pioc_virq, gpio_irq_handler);
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/* Then register the chain on the parent IRQ */
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gpiochip_set_chained_irqchip(&at91_gpio->chip,
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&gpio_irqchip,
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at91_gpio->pioc_virq,
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gpio_irq_handler);
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return 0;
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}
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@ -1586,7 +1512,6 @@ static struct gpio_chip at91_gpio_template = {
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.get = at91_gpio_get,
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.direction_output = at91_gpio_direction_output,
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.set = at91_gpio_set,
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.to_irq = at91_gpio_to_irq,
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.dbg_show = at91_gpio_dbg_show,
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.can_sleep = false,
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.ngpio = MAX_NB_GPIO_PER_BANK,
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