This includes addition of some missing clock tree definitions
(UART, MMC2 clocks) for exynos3250 SoC and exporting of IDs for exynos543x SoC AMBA AXI bus clocks needed for bus frequency scaling. -----BEGIN PGP SIGNATURE----- Version: GnuPG v1 iQIcBAABCAAGBQJXER7wAAoJEE1bIKeAnHqLkJIP/3QZKFAg94HtNPzmqvS8ZcyN DADbg2V3VAWSwWz3jwXz+NQOK5IDKmCnvxHQJdnm/0HpbXRW1C413KC+f84xq0zL Us4j7BvXemEyw2Gnv5VAiaEZ6iD/tj6HkCvq5Y12fWPFc1Bqpgf6ghxcADngc22j wj8V1RjJ5iXjGmlqYTEPDA7OXVA4sC2HLuWiUvehW56KAlzL6UfThXweiChBiDOh fockxKiYWVuxiFqd3GkhJGXjzK9RHzUGJSqCNjruIjyG0dekADZnm12nYjFjxym2 kL5sPI8Fo2UgzvAV8ax6Ln62uIqtzFhkZAeqkKZSJjEBryYHzAq8QVXS9iP+Ky+E 8VxZ6IGL1scoVU7g094LjyX9mP2p2PnZWvzCGdvK1qNjYzVO0ZjfXkoU71+JKoat JxjUQ2rZTNQGb3KeqfV5SJtE8ffP+9BE+y8K4EaczdYRMqf08pKuhY9c2IHuCEs3 mpPALIVOHMSh1s58gF26tMyY3vo/04Few63S9YH/mB7LEXeH6Xs7oHHsnMvsPu3N CVZwuQ8V/u1W4H7dCU2b9HzgqpxUfM97DbX5NtJH/1zdmpuzWVJxv8K5kT7cHRfi IKEjhqRuNAytXojXEL1HElgsPw0THtz+qdBOAxaNwPHZCE3kBLgL4U9hKMBWewx4 oPH4MjN6xv4sbezGaas7 =Sl7j -----END PGP SIGNATURE----- Merge tag 'clk-v4.7-samsung' of git://linuxtv.org/snawrocki/samsung into clk-next Pull samsung clk updates from Sylwester Nawrocki: This includes addition of some missing clock tree definitions (UART, MMC2 clocks) for exynos3250 SoC and exporting of IDs for exynos543x SoC AMBA AXI bus clocks needed for bus frequency scaling. * tag 'clk-v4.7-samsung' of git://linuxtv.org/snawrocki/samsung: clk: samsung: exynos542x: Add the clock id for ACLK dt-bindings: clock: Add the clock id for ACLK clock of Exynos542x SoC clk: samsung: exynos3250: Add MMC2 clock clk: samsung: exynos3250: Add UART2 clock dt-bindings: Add the clock id of UART2 and MMC2 for Exynos3250
This commit is contained in:
Stephen Boyd
Коммит
811a087c55
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@ -302,10 +302,12 @@ static struct samsung_mux_clock mux_clks[] __initdata = {
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/* SRC_FSYS */
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MUX(CLK_MOUT_TSADC, "mout_tsadc", group_sclk_p, SRC_FSYS, 28, 4),
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MUX(CLK_MOUT_MMC2, "mout_mmc2", group_sclk_p, SRC_FSYS, 8, 4),
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MUX(CLK_MOUT_MMC1, "mout_mmc1", group_sclk_p, SRC_FSYS, 4, 4),
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MUX(CLK_MOUT_MMC0, "mout_mmc0", group_sclk_p, SRC_FSYS, 0, 4),
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/* SRC_PERIL0 */
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MUX(CLK_MOUT_UART2, "mout_uart2", group_sclk_p, SRC_PERIL0, 8, 4),
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MUX(CLK_MOUT_UART1, "mout_uart1", group_sclk_p, SRC_PERIL0, 4, 4),
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MUX(CLK_MOUT_UART0, "mout_uart0", group_sclk_p, SRC_PERIL0, 0, 4),
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@ -389,7 +391,13 @@ static struct samsung_div_clock div_clks[] __initdata = {
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CLK_SET_RATE_PARENT, 0),
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DIV(CLK_DIV_MMC0, "div_mmc0", "mout_mmc0", DIV_FSYS1, 0, 4),
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/* DIV_FSYS2 */
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DIV_F(CLK_DIV_MMC2_PRE, "div_mmc2_pre", "div_mmc2", DIV_FSYS2, 8, 8,
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CLK_SET_RATE_PARENT, 0),
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DIV(CLK_DIV_MMC2, "div_mmc2", "mout_mmc2", DIV_FSYS2, 0, 4),
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/* DIV_PERIL0 */
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DIV(CLK_DIV_UART2, "div_uart2", "mout_uart2", DIV_PERIL0, 8, 4),
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DIV(CLK_DIV_UART1, "div_uart1", "mout_uart1", DIV_PERIL0, 4, 4),
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DIV(CLK_DIV_UART0, "div_uart0", "mout_uart0", DIV_PERIL0, 0, 4),
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@ -538,6 +546,8 @@ static struct samsung_gate_clock gate_clks[] __initdata = {
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GATE_SCLK_FSYS, 9, CLK_SET_RATE_PARENT, 0),
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GATE(CLK_SCLK_EBI, "sclk_ebi", "div_ebi",
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GATE_SCLK_FSYS, 6, CLK_SET_RATE_PARENT, 0),
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GATE(CLK_SCLK_MMC2, "sclk_mmc2", "div_mmc2_pre",
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GATE_SCLK_FSYS, 2, CLK_SET_RATE_PARENT, 0),
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GATE(CLK_SCLK_MMC1, "sclk_mmc1", "div_mmc1_pre",
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GATE_SCLK_FSYS, 1, CLK_SET_RATE_PARENT, 0),
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GATE(CLK_SCLK_MMC0, "sclk_mmc0", "div_mmc0_pre",
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@ -552,6 +562,9 @@ static struct samsung_gate_clock gate_clks[] __initdata = {
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GATE_SCLK_PERIL, 7, CLK_SET_RATE_PARENT, 0),
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GATE(CLK_SCLK_SPI0, "sclk_spi0", "div_spi0_pre",
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GATE_SCLK_PERIL, 6, CLK_SET_RATE_PARENT, 0),
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GATE(CLK_SCLK_UART2, "sclk_uart2", "div_uart2",
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GATE_SCLK_PERIL, 2, CLK_SET_RATE_PARENT, 0),
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GATE(CLK_SCLK_UART1, "sclk_uart1", "div_uart1",
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GATE_SCLK_PERIL, 1, CLK_SET_RATE_PARENT, 0),
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GATE(CLK_SCLK_UART0, "sclk_uart0", "div_uart0",
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@ -630,6 +643,7 @@ static struct samsung_gate_clock gate_clks[] __initdata = {
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GATE(CLK_USBOTG, "usbotg", "div_aclk_200", GATE_IP_FSYS, 13, 0, 0),
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GATE(CLK_USBHOST, "usbhost", "div_aclk_200", GATE_IP_FSYS, 12, 0, 0),
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GATE(CLK_SROMC, "sromc", "div_aclk_200", GATE_IP_FSYS, 11, 0, 0),
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GATE(CLK_SDMMC2, "sdmmc2", "div_aclk_200", GATE_IP_FSYS, 7, 0, 0),
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GATE(CLK_SDMMC1, "sdmmc1", "div_aclk_200", GATE_IP_FSYS, 6, 0, 0),
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GATE(CLK_SDMMC0, "sdmmc0", "div_aclk_200", GATE_IP_FSYS, 5, 0, 0),
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GATE(CLK_PDMA1, "pdma1", "div_aclk_200", GATE_IP_FSYS, 1, 0, 0),
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@ -649,6 +663,7 @@ static struct samsung_gate_clock gate_clks[] __initdata = {
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GATE(CLK_I2C2, "i2c2", "div_aclk_100", GATE_IP_PERIL, 8, 0, 0),
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GATE(CLK_I2C1, "i2c1", "div_aclk_100", GATE_IP_PERIL, 7, 0, 0),
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GATE(CLK_I2C0, "i2c0", "div_aclk_100", GATE_IP_PERIL, 6, 0, 0),
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GATE(CLK_UART2, "uart2", "div_aclk_100", GATE_IP_PERIL, 2, 0, 0),
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GATE(CLK_UART1, "uart1", "div_aclk_100", GATE_IP_PERIL, 1, 0, 0),
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GATE(CLK_UART0, "uart0", "div_aclk_100", GATE_IP_PERIL, 0, 0, 0),
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};
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@ -554,8 +554,8 @@ static struct samsung_mux_clock exynos5800_mux_clks[] __initdata = {
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};
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static struct samsung_div_clock exynos5800_div_clks[] __initdata = {
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DIV(0, "dout_aclk400_wcore", "mout_aclk400_wcore", DIV_TOP0, 16, 3),
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DIV(CLK_DOUT_ACLK400_WCORE, "dout_aclk400_wcore",
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"mout_aclk400_wcore", DIV_TOP0, 16, 3),
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DIV(0, "dout_aclk550_cam", "mout_aclk550_cam",
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DIV_TOP8, 16, 3),
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DIV(0, "dout_aclkfl1_550_cam", "mout_aclkfl1_550_cam",
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@ -607,8 +607,8 @@ static struct samsung_mux_clock exynos5420_mux_clks[] __initdata = {
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};
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static struct samsung_div_clock exynos5420_div_clks[] __initdata = {
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DIV(0, "dout_aclk400_wcore", "mout_aclk400_wcore_bpll",
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DIV_TOP0, 16, 3),
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DIV(CLK_DOUT_ACLK400_WCORE, "dout_aclk400_wcore",
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"mout_aclk400_wcore_bpll", DIV_TOP0, 16, 3),
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};
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static struct samsung_mux_clock exynos5x_mux_clks[] __initdata = {
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@ -785,31 +785,47 @@ static struct samsung_div_clock exynos5x_div_clks[] __initdata = {
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DIV(0, "div_kfc", "mout_kfc", DIV_KFC0, 0, 3),
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DIV(0, "sclk_kpll", "mout_kpll", DIV_KFC0, 24, 3),
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DIV(0, "dout_aclk400_isp", "mout_aclk400_isp", DIV_TOP0, 0, 3),
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DIV(0, "dout_aclk400_mscl", "mout_aclk400_mscl", DIV_TOP0, 4, 3),
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DIV(0, "dout_aclk200", "mout_aclk200", DIV_TOP0, 8, 3),
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DIV(0, "dout_aclk200_fsys2", "mout_aclk200_fsys2", DIV_TOP0, 12, 3),
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DIV(0, "dout_aclk100_noc", "mout_aclk100_noc", DIV_TOP0, 20, 3),
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DIV(0, "dout_pclk200_fsys", "mout_pclk200_fsys", DIV_TOP0, 24, 3),
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DIV(0, "dout_aclk200_fsys", "mout_aclk200_fsys", DIV_TOP0, 28, 3),
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DIV(CLK_DOUT_ACLK400_ISP, "dout_aclk400_isp", "mout_aclk400_isp",
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DIV_TOP0, 0, 3),
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DIV(CLK_DOUT_ACLK400_MSCL, "dout_aclk400_mscl", "mout_aclk400_mscl",
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DIV_TOP0, 4, 3),
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DIV(CLK_DOUT_ACLK200, "dout_aclk200", "mout_aclk200",
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DIV_TOP0, 8, 3),
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DIV(CLK_DOUT_ACLK200_FSYS2, "dout_aclk200_fsys2", "mout_aclk200_fsys2",
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DIV_TOP0, 12, 3),
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DIV(CLK_DOUT_ACLK100_NOC, "dout_aclk100_noc", "mout_aclk100_noc",
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DIV_TOP0, 20, 3),
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DIV(CLK_DOUT_PCLK200_FSYS, "dout_pclk200_fsys", "mout_pclk200_fsys",
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DIV_TOP0, 24, 3),
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DIV(CLK_DOUT_ACLK200_FSYS, "dout_aclk200_fsys", "mout_aclk200_fsys",
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DIV_TOP0, 28, 3),
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DIV(CLK_DOUT_ACLK333_432_GSCL, "dout_aclk333_432_gscl",
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"mout_aclk333_432_gscl", DIV_TOP1, 0, 3),
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DIV(CLK_DOUT_ACLK333_432_ISP, "dout_aclk333_432_isp",
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"mout_aclk333_432_isp", DIV_TOP1, 4, 3),
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DIV(CLK_DOUT_ACLK66, "dout_aclk66", "mout_aclk66",
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DIV_TOP1, 8, 6),
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DIV(CLK_DOUT_ACLK333_432_ISP0, "dout_aclk333_432_isp0",
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"mout_aclk333_432_isp0", DIV_TOP1, 16, 3),
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DIV(CLK_DOUT_ACLK266, "dout_aclk266", "mout_aclk266",
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DIV_TOP1, 20, 3),
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DIV(CLK_DOUT_ACLK166, "dout_aclk166", "mout_aclk166",
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DIV_TOP1, 24, 3),
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DIV(CLK_DOUT_ACLK333, "dout_aclk333", "mout_aclk333",
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DIV_TOP1, 28, 3),
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DIV(0, "dout_aclk333_432_gscl", "mout_aclk333_432_gscl",
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DIV_TOP1, 0, 3),
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DIV(0, "dout_aclk333_432_isp", "mout_aclk333_432_isp",
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DIV_TOP1, 4, 3),
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DIV(0, "dout_aclk66", "mout_aclk66", DIV_TOP1, 8, 6),
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DIV(0, "dout_aclk333_432_isp0", "mout_aclk333_432_isp0",
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DIV_TOP1, 16, 3),
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DIV(0, "dout_aclk266", "mout_aclk266", DIV_TOP1, 20, 3),
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DIV(0, "dout_aclk166", "mout_aclk166", DIV_TOP1, 24, 3),
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DIV(0, "dout_aclk333", "mout_aclk333", DIV_TOP1, 28, 3),
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DIV(0, "dout_aclk333_g2d", "mout_aclk333_g2d", DIV_TOP2, 8, 3),
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DIV(0, "dout_aclk266_g2d", "mout_aclk266_g2d", DIV_TOP2, 12, 3),
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DIV(0, "dout_aclk_g3d", "mout_aclk_g3d", DIV_TOP2, 16, 3),
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DIV(0, "dout_aclk300_jpeg", "mout_aclk300_jpeg", DIV_TOP2, 20, 3),
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DIV(0, "dout_aclk300_disp1", "mout_aclk300_disp1", DIV_TOP2, 24, 3),
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DIV(0, "dout_aclk300_gscl", "mout_aclk300_gscl", DIV_TOP2, 28, 3),
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DIV(CLK_DOUT_ACLK333_G2D, "dout_aclk333_g2d", "mout_aclk333_g2d",
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DIV_TOP2, 8, 3),
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DIV(CLK_DOUT_ACLK266_G2D, "dout_aclk266_g2d", "mout_aclk266_g2d",
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DIV_TOP2, 12, 3),
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DIV(CLK_DOUT_ACLK_G3D, "dout_aclk_g3d", "mout_aclk_g3d", DIV_TOP2,
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16, 3),
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DIV(CLK_DOUT_ACLK300_JPEG, "dout_aclk300_jpeg", "mout_aclk300_jpeg",
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DIV_TOP2, 20, 3),
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DIV(CLK_DOUT_ACLK300_DISP1, "dout_aclk300_disp1",
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"mout_aclk300_disp1", DIV_TOP2, 24, 3),
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DIV(CLK_DOUT_ACLK300_GSCL, "dout_aclk300_gscl", "mout_aclk300_gscl",
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DIV_TOP2, 28, 3),
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/* DISP1 Block */
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DIV(0, "dout_fimd1", "mout_fimd1_final", DIV_DISP10, 0, 4),
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@ -817,7 +833,8 @@ static struct samsung_div_clock exynos5x_div_clks[] __initdata = {
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DIV(0, "dout_dp1", "mout_dp1", DIV_DISP10, 24, 4),
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DIV(CLK_DOUT_PIXEL, "dout_hdmi_pixel", "mout_pixel", DIV_DISP10, 28, 4),
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DIV(0, "dout_disp1_blk", "aclk200_disp1", DIV2_RATIO0, 16, 2),
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DIV(0, "dout_aclk400_disp1", "mout_aclk400_disp1", DIV_TOP2, 4, 3),
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DIV(CLK_DOUT_ACLK400_DISP1, "dout_aclk400_disp1",
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"mout_aclk400_disp1", DIV_TOP2, 4, 3),
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/* Audio Block */
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DIV(0, "dout_maudio0", "mout_maudio0", DIV_MAU, 20, 4),
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@ -79,6 +79,8 @@
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#define CLK_MOUT_CORE 58
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#define CLK_MOUT_APLL 59
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#define CLK_MOUT_ACLK_266_SUB 60
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#define CLK_MOUT_UART2 61
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#define CLK_MOUT_MMC2 62
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/* Dividers */
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#define CLK_DIV_GPL 64
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@ -127,6 +129,9 @@
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#define CLK_DIV_CORE 107
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#define CLK_DIV_HPM 108
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#define CLK_DIV_COPY 109
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#define CLK_DIV_UART2 110
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#define CLK_DIV_MMC2_PRE 111
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#define CLK_DIV_MMC2 112
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/* Gates */
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#define CLK_ASYNC_G3D 128
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@ -223,6 +228,8 @@
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#define CLK_BLOCK_MFC 219
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#define CLK_BLOCK_CAM 220
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#define CLK_SMIES 221
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#define CLK_UART2 222
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#define CLK_SDMMC2 223
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/* Special clocks */
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#define CLK_SCLK_JPEG 224
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@ -249,12 +256,14 @@
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#define CLK_SCLK_SPI0 245
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#define CLK_SCLK_UART1 246
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#define CLK_SCLK_UART0 247
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#define CLK_SCLK_UART2 248
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#define CLK_SCLK_MMC2 249
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/*
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* Total number of clocks of main CMU.
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* NOTE: Must be equal to last clock ID increased by one.
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*/
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#define CLK_NR_CLKS 248
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#define CLK_NR_CLKS 250
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/*
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* CMU DMC
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@ -217,8 +217,30 @@
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/* divider clocks */
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#define CLK_DOUT_PIXEL 768
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#define CLK_DOUT_ACLK400_WCORE 769
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#define CLK_DOUT_ACLK400_ISP 770
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#define CLK_DOUT_ACLK400_MSCL 771
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#define CLK_DOUT_ACLK200 772
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#define CLK_DOUT_ACLK200_FSYS2 773
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#define CLK_DOUT_ACLK100_NOC 774
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#define CLK_DOUT_PCLK200_FSYS 775
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#define CLK_DOUT_ACLK200_FSYS 776
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#define CLK_DOUT_ACLK333_432_GSCL 777
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#define CLK_DOUT_ACLK333_432_ISP 778
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#define CLK_DOUT_ACLK66 779
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#define CLK_DOUT_ACLK333_432_ISP0 780
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#define CLK_DOUT_ACLK266 781
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#define CLK_DOUT_ACLK166 782
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#define CLK_DOUT_ACLK333 783
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#define CLK_DOUT_ACLK333_G2D 784
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#define CLK_DOUT_ACLK266_G2D 785
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#define CLK_DOUT_ACLK_G3D 786
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#define CLK_DOUT_ACLK300_JPEG 787
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#define CLK_DOUT_ACLK300_DISP1 788
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#define CLK_DOUT_ACLK300_GSCL 789
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#define CLK_DOUT_ACLK400_DISP1 790
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/* must be greater than maximal clock id */
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#define CLK_NR_CLKS 769
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#define CLK_NR_CLKS 791
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#endif /* _DT_BINDINGS_CLOCK_EXYNOS_5420_H */
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