x86/mce: Get rid of msr_ops
Avoid having indirect calls and use a normal function which returns the proper MSR address based on ->smca setting. No functional changes. Signed-off-by: Borislav Petkov <bp@suse.de> Reviewed-by: Tony Luck <tony.luck@intel.com> Link: https://lkml.kernel.org/r/20210922165101.18951-4-bp@alien8.de
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Родитель
cbe1de162d
Коммит
8121b8f947
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@ -526,7 +526,7 @@ static u32 get_block_address(u32 current_addr, u32 low, u32 high,
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/* Fall back to method we used for older processors: */
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switch (block) {
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case 0:
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addr = msr_ops.misc(bank);
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addr = mca_msr_reg(bank, MCA_MISC);
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break;
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case 1:
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offset = ((low & MASK_BLKPTR_LO) >> 21);
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@ -978,8 +978,8 @@ static void log_error_deferred(unsigned int bank)
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{
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bool defrd;
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defrd = _log_error_bank(bank, msr_ops.status(bank),
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msr_ops.addr(bank), 0);
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defrd = _log_error_bank(bank, mca_msr_reg(bank, MCA_STATUS),
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mca_msr_reg(bank, MCA_ADDR), 0);
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if (!mce_flags.smca)
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return;
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@ -1009,7 +1009,7 @@ static void amd_deferred_error_interrupt(void)
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static void log_error_thresholding(unsigned int bank, u64 misc)
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{
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_log_error_bank(bank, msr_ops.status(bank), msr_ops.addr(bank), misc);
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_log_error_bank(bank, mca_msr_reg(bank, MCA_STATUS), mca_msr_reg(bank, MCA_ADDR), misc);
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}
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static void log_and_reset_block(struct threshold_block *block)
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@ -1397,7 +1397,7 @@ static int threshold_create_bank(struct threshold_bank **bp, unsigned int cpu,
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}
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}
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err = allocate_threshold_blocks(cpu, b, bank, 0, msr_ops.misc(bank));
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err = allocate_threshold_blocks(cpu, b, bank, 0, mca_msr_reg(bank, MCA_MISC));
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if (err)
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goto out_kobj;
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@ -176,53 +176,27 @@ void mce_unregister_decode_chain(struct notifier_block *nb)
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}
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EXPORT_SYMBOL_GPL(mce_unregister_decode_chain);
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static inline u32 ctl_reg(int bank)
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u32 mca_msr_reg(int bank, enum mca_msr reg)
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{
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return MSR_IA32_MCx_CTL(bank);
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}
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if (mce_flags.smca) {
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switch (reg) {
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case MCA_CTL: return MSR_AMD64_SMCA_MCx_CTL(bank);
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case MCA_ADDR: return MSR_AMD64_SMCA_MCx_ADDR(bank);
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case MCA_MISC: return MSR_AMD64_SMCA_MCx_MISC(bank);
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case MCA_STATUS: return MSR_AMD64_SMCA_MCx_STATUS(bank);
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}
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}
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static inline u32 status_reg(int bank)
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{
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return MSR_IA32_MCx_STATUS(bank);
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}
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switch (reg) {
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case MCA_CTL: return MSR_IA32_MCx_CTL(bank);
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case MCA_ADDR: return MSR_IA32_MCx_ADDR(bank);
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case MCA_MISC: return MSR_IA32_MCx_MISC(bank);
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case MCA_STATUS: return MSR_IA32_MCx_STATUS(bank);
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}
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static inline u32 addr_reg(int bank)
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{
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return MSR_IA32_MCx_ADDR(bank);
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return 0;
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}
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static inline u32 misc_reg(int bank)
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{
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return MSR_IA32_MCx_MISC(bank);
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}
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static inline u32 smca_ctl_reg(int bank)
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{
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return MSR_AMD64_SMCA_MCx_CTL(bank);
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}
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static inline u32 smca_status_reg(int bank)
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{
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return MSR_AMD64_SMCA_MCx_STATUS(bank);
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}
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static inline u32 smca_addr_reg(int bank)
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{
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return MSR_AMD64_SMCA_MCx_ADDR(bank);
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}
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static inline u32 smca_misc_reg(int bank)
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{
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return MSR_AMD64_SMCA_MCx_MISC(bank);
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}
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struct mca_msr_regs msr_ops = {
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.ctl = ctl_reg,
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.status = status_reg,
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.addr = addr_reg,
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.misc = misc_reg
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};
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static void __print_mce(struct mce *m)
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{
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pr_emerg(HW_ERR "CPU %d: Machine Check%s: %Lx Bank %d: %016Lx\n",
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@ -362,11 +336,11 @@ static int msr_to_offset(u32 msr)
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if (msr == mca_cfg.rip_msr)
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return offsetof(struct mce, ip);
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if (msr == msr_ops.status(bank))
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if (msr == mca_msr_reg(bank, MCA_STATUS))
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return offsetof(struct mce, status);
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if (msr == msr_ops.addr(bank))
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if (msr == mca_msr_reg(bank, MCA_ADDR))
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return offsetof(struct mce, addr);
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if (msr == msr_ops.misc(bank))
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if (msr == mca_msr_reg(bank, MCA_MISC))
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return offsetof(struct mce, misc);
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if (msr == MSR_IA32_MCG_STATUS)
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return offsetof(struct mce, mcgstatus);
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@ -685,10 +659,10 @@ static struct notifier_block mce_default_nb = {
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static void mce_read_aux(struct mce *m, int i)
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{
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if (m->status & MCI_STATUS_MISCV)
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m->misc = mce_rdmsrl(msr_ops.misc(i));
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m->misc = mce_rdmsrl(mca_msr_reg(i, MCA_MISC));
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if (m->status & MCI_STATUS_ADDRV) {
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m->addr = mce_rdmsrl(msr_ops.addr(i));
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m->addr = mce_rdmsrl(mca_msr_reg(i, MCA_ADDR));
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/*
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* Mask the reported address by the reported granularity.
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@ -758,7 +732,7 @@ bool machine_check_poll(enum mcp_flags flags, mce_banks_t *b)
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m.bank = i;
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barrier();
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m.status = mce_rdmsrl(msr_ops.status(i));
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m.status = mce_rdmsrl(mca_msr_reg(i, MCA_STATUS));
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/* If this entry is not valid, ignore it */
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if (!(m.status & MCI_STATUS_VAL))
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@ -826,7 +800,7 @@ clear_it:
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/*
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* Clear state for this bank.
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*/
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mce_wrmsrl(msr_ops.status(i), 0);
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mce_wrmsrl(mca_msr_reg(i, MCA_STATUS), 0);
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}
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/*
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@ -851,7 +825,7 @@ static int mce_no_way_out(struct mce *m, char **msg, unsigned long *validp,
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int i;
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for (i = 0; i < this_cpu_read(mce_num_banks); i++) {
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m->status = mce_rdmsrl(msr_ops.status(i));
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m->status = mce_rdmsrl(mca_msr_reg(i, MCA_STATUS));
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if (!(m->status & MCI_STATUS_VAL))
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continue;
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@ -1144,7 +1118,7 @@ static void mce_clear_state(unsigned long *toclear)
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for (i = 0; i < this_cpu_read(mce_num_banks); i++) {
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if (test_bit(i, toclear))
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mce_wrmsrl(msr_ops.status(i), 0);
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mce_wrmsrl(mca_msr_reg(i, MCA_STATUS), 0);
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}
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}
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@ -1203,7 +1177,7 @@ static void __mc_scan_banks(struct mce *m, struct pt_regs *regs, struct mce *fin
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m->addr = 0;
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m->bank = i;
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m->status = mce_rdmsrl(msr_ops.status(i));
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m->status = mce_rdmsrl(mca_msr_reg(i, MCA_STATUS));
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if (!(m->status & MCI_STATUS_VAL))
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continue;
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@ -1708,8 +1682,8 @@ static void __mcheck_cpu_init_clear_banks(void)
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if (!b->init)
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continue;
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wrmsrl(msr_ops.ctl(i), b->ctl);
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wrmsrl(msr_ops.status(i), 0);
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wrmsrl(mca_msr_reg(i, MCA_CTL), b->ctl);
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wrmsrl(mca_msr_reg(i, MCA_STATUS), 0);
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}
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}
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@ -1735,7 +1709,7 @@ static void __mcheck_cpu_check_banks(void)
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if (!b->init)
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continue;
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rdmsrl(msr_ops.ctl(i), msrval);
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rdmsrl(mca_msr_reg(i, MCA_CTL), msrval);
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b->init = !!msrval;
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}
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}
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@ -1894,13 +1868,6 @@ static void __mcheck_cpu_init_early(struct cpuinfo_x86 *c)
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mce_flags.succor = !!cpu_has(c, X86_FEATURE_SUCCOR);
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mce_flags.smca = !!cpu_has(c, X86_FEATURE_SMCA);
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mce_flags.amd_threshold = 1;
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if (mce_flags.smca) {
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msr_ops.ctl = smca_ctl_reg;
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msr_ops.status = smca_status_reg;
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msr_ops.addr = smca_addr_reg;
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msr_ops.misc = smca_misc_reg;
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}
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}
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}
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@ -2254,7 +2221,7 @@ static void mce_disable_error_reporting(void)
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struct mce_bank *b = &mce_banks[i];
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if (b->init)
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wrmsrl(msr_ops.ctl(i), 0);
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wrmsrl(mca_msr_reg(i, MCA_CTL), 0);
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}
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return;
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}
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@ -2606,7 +2573,7 @@ static void mce_reenable_cpu(void)
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struct mce_bank *b = &mce_banks[i];
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if (b->init)
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wrmsrl(msr_ops.ctl(i), b->ctl);
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wrmsrl(mca_msr_reg(i, MCA_CTL), b->ctl);
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}
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}
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@ -172,14 +172,14 @@ struct mce_vendor_flags {
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extern struct mce_vendor_flags mce_flags;
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struct mca_msr_regs {
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u32 (*ctl) (int bank);
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u32 (*status) (int bank);
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u32 (*addr) (int bank);
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u32 (*misc) (int bank);
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enum mca_msr {
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MCA_CTL,
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MCA_STATUS,
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MCA_ADDR,
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MCA_MISC,
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};
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extern struct mca_msr_regs msr_ops;
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u32 mca_msr_reg(int bank, enum mca_msr reg);
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/* Decide whether to add MCE record to MCE event pool or filter it out. */
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extern bool filter_mce(struct mce *m);
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