gpio/mvebu: Use irq_domain_add_linear
This fixes the irq allocation in this driver to not print:
irq: Cannot allocate irq_descs @ IRQ34, assuming pre-allocated
irq: Cannot allocate irq_descs @ IRQ66, assuming pre-allocated
Which happens because the driver already called irq_alloc_descs()
and so the change to use irq_domain_add_simple resulted in calling
irq_alloc_descs() twice.
Modernize the irq allocation in this driver to use the
irq_domain_add_linear flow directly and eliminate the use of
irq_domain_add_simple/legacy
Fixes: ce931f571b ("gpio/mvebu: convert to use irq_domain_add_simple()")
Signed-off-by: Jason Gunthorpe <jgunthorpe@obsidianresearch.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
This commit is contained in:
Jason Gunthorpe
Linus Walleij
Родитель
c7e9d39831
Коммит
812d47889a
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@ -293,10 +293,10 @@ static void mvebu_gpio_irq_ack(struct irq_data *d)
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{
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struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
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struct mvebu_gpio_chip *mvchip = gc->private;
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u32 mask = ~(1 << (d->irq - gc->irq_base));
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u32 mask = d->mask;
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irq_gc_lock(gc);
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writel_relaxed(mask, mvebu_gpioreg_edge_cause(mvchip));
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writel_relaxed(~mask, mvebu_gpioreg_edge_cause(mvchip));
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irq_gc_unlock(gc);
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}
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@ -305,7 +305,7 @@ static void mvebu_gpio_edge_irq_mask(struct irq_data *d)
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struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
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struct mvebu_gpio_chip *mvchip = gc->private;
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struct irq_chip_type *ct = irq_data_get_chip_type(d);
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u32 mask = 1 << (d->irq - gc->irq_base);
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u32 mask = d->mask;
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irq_gc_lock(gc);
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ct->mask_cache_priv &= ~mask;
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@ -319,8 +319,7 @@ static void mvebu_gpio_edge_irq_unmask(struct irq_data *d)
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struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
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struct mvebu_gpio_chip *mvchip = gc->private;
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struct irq_chip_type *ct = irq_data_get_chip_type(d);
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u32 mask = 1 << (d->irq - gc->irq_base);
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u32 mask = d->mask;
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irq_gc_lock(gc);
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ct->mask_cache_priv |= mask;
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@ -333,8 +332,7 @@ static void mvebu_gpio_level_irq_mask(struct irq_data *d)
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struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
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struct mvebu_gpio_chip *mvchip = gc->private;
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struct irq_chip_type *ct = irq_data_get_chip_type(d);
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u32 mask = 1 << (d->irq - gc->irq_base);
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u32 mask = d->mask;
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irq_gc_lock(gc);
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ct->mask_cache_priv &= ~mask;
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@ -347,8 +345,7 @@ static void mvebu_gpio_level_irq_unmask(struct irq_data *d)
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struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
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struct mvebu_gpio_chip *mvchip = gc->private;
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struct irq_chip_type *ct = irq_data_get_chip_type(d);
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u32 mask = 1 << (d->irq - gc->irq_base);
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u32 mask = d->mask;
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irq_gc_lock(gc);
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ct->mask_cache_priv |= mask;
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@ -462,7 +459,7 @@ static void mvebu_gpio_irq_handler(struct irq_desc *desc)
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for (i = 0; i < mvchip->chip.ngpio; i++) {
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int irq;
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irq = mvchip->irqbase + i;
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irq = irq_find_mapping(mvchip->domain, i);
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if (!(cause & (1 << i)))
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continue;
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@ -655,6 +652,7 @@ static int mvebu_gpio_probe(struct platform_device *pdev)
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struct irq_chip_type *ct;
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struct clk *clk;
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unsigned int ngpios;
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bool have_irqs;
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int soc_variant;
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int i, cpu, id;
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int err;
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@ -665,6 +663,9 @@ static int mvebu_gpio_probe(struct platform_device *pdev)
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else
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soc_variant = MVEBU_GPIO_SOC_VARIANT_ORION;
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/* Some gpio controllers do not provide irq support */
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have_irqs = of_irq_count(np) != 0;
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mvchip = devm_kzalloc(&pdev->dev, sizeof(struct mvebu_gpio_chip),
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GFP_KERNEL);
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if (!mvchip)
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@ -697,7 +698,8 @@ static int mvebu_gpio_probe(struct platform_device *pdev)
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mvchip->chip.get = mvebu_gpio_get;
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mvchip->chip.direction_output = mvebu_gpio_direction_output;
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mvchip->chip.set = mvebu_gpio_set;
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mvchip->chip.to_irq = mvebu_gpio_to_irq;
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if (have_irqs)
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mvchip->chip.to_irq = mvebu_gpio_to_irq;
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mvchip->chip.base = id * MVEBU_MAX_GPIO_PER_BANK;
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mvchip->chip.ngpio = ngpios;
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mvchip->chip.can_sleep = false;
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@ -758,34 +760,30 @@ static int mvebu_gpio_probe(struct platform_device *pdev)
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devm_gpiochip_add_data(&pdev->dev, &mvchip->chip, mvchip);
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/* Some gpio controllers do not provide irq support */
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if (!of_irq_count(np))
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if (!have_irqs)
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return 0;
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/* Setup the interrupt handlers. Each chip can have up to 4
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* interrupt handlers, with each handler dealing with 8 GPIO
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* pins. */
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for (i = 0; i < 4; i++) {
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int irq = platform_get_irq(pdev, i);
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if (irq < 0)
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continue;
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irq_set_chained_handler_and_data(irq, mvebu_gpio_irq_handler,
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mvchip);
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mvchip->domain =
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irq_domain_add_linear(np, ngpios, &irq_generic_chip_ops, NULL);
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if (!mvchip->domain) {
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dev_err(&pdev->dev, "couldn't allocate irq domain %s (DT).\n",
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mvchip->chip.label);
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return -ENODEV;
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}
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mvchip->irqbase = irq_alloc_descs(-1, 0, ngpios, -1);
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if (mvchip->irqbase < 0) {
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dev_err(&pdev->dev, "no irqs\n");
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return mvchip->irqbase;
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}
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gc = irq_alloc_generic_chip("mvebu_gpio_irq", 2, mvchip->irqbase,
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mvchip->membase, handle_level_irq);
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if (!gc) {
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dev_err(&pdev->dev, "Cannot allocate generic irq_chip\n");
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return -ENOMEM;
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err = irq_alloc_domain_generic_chips(
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mvchip->domain, ngpios, 2, np->name, handle_level_irq,
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IRQ_NOREQUEST | IRQ_NOPROBE | IRQ_LEVEL, 0, 0);
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if (err) {
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dev_err(&pdev->dev, "couldn't allocate irq chips %s (DT).\n",
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mvchip->chip.label);
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goto err_domain;
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}
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/* NOTE: The common accessors cannot be used because of the percpu
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* access to the mask registers
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*/
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gc = irq_get_domain_generic_chip(mvchip->domain, 0);
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gc->private = mvchip;
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ct = &gc->chip_types[0];
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ct->type = IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW;
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@ -803,27 +801,23 @@ static int mvebu_gpio_probe(struct platform_device *pdev)
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ct->handler = handle_edge_irq;
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ct->chip.name = mvchip->chip.label;
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irq_setup_generic_chip(gc, IRQ_MSK(ngpios), 0,
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IRQ_NOREQUEST, IRQ_LEVEL | IRQ_NOPROBE);
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/* Setup the interrupt handlers. Each chip can have up to 4
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* interrupt handlers, with each handler dealing with 8 GPIO
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* pins.
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*/
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for (i = 0; i < 4; i++) {
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int irq = platform_get_irq(pdev, i);
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/* Setup irq domain on top of the generic chip. */
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mvchip->domain = irq_domain_add_simple(np, mvchip->chip.ngpio,
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mvchip->irqbase,
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&irq_domain_simple_ops,
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mvchip);
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if (!mvchip->domain) {
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dev_err(&pdev->dev, "couldn't allocate irq domain %s (DT).\n",
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mvchip->chip.label);
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err = -ENODEV;
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goto err_generic_chip;
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if (irq < 0)
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continue;
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irq_set_chained_handler_and_data(irq, mvebu_gpio_irq_handler,
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mvchip);
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}
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return 0;
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err_generic_chip:
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irq_remove_generic_chip(gc, IRQ_MSK(ngpios), IRQ_NOREQUEST,
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IRQ_LEVEL | IRQ_NOPROBE);
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kfree(gc);
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err_domain:
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irq_domain_remove(mvchip->domain);
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return err;
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}
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