Merge remote-tracking branch 'spi/topic/sh-msiof' into spi-next
This commit is contained in:
Mark Brown
Коммит
81306d53da
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@ -30,6 +30,22 @@ Optional properties:
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specifiers, one for transmission, and one for
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reception.
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- dma-names : Must contain a list of two DMA names, "tx" and "rx".
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- renesas,dtdl : delay sync signal (setup) in transmit mode.
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Must contain one of the following values:
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0 (no bit delay)
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50 (0.5-clock-cycle delay)
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100 (1-clock-cycle delay)
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150 (1.5-clock-cycle delay)
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200 (2-clock-cycle delay)
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- renesas,syncdl : delay sync signal (hold) in transmit mode.
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Must contain one of the following values:
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0 (no bit delay)
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50 (0.5-clock-cycle delay)
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100 (1-clock-cycle delay)
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150 (1.5-clock-cycle delay)
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200 (2-clock-cycle delay)
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300 (3-clock-cycle delay)
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Optional properties, deprecated for soctype-specific bindings:
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- renesas,tx-fifo-size : Overrides the default tx fifo size given in words
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@ -82,6 +82,8 @@ struct sh_msiof_spi_priv {
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#define MDR1_SYNCMD_LR 0x30000000 /* L/R mode */
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#define MDR1_SYNCAC_SHIFT 25 /* Sync Polarity (1 = Active-low) */
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#define MDR1_BITLSB_SHIFT 24 /* MSB/LSB First (1 = LSB first) */
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#define MDR1_DTDL_SHIFT 20 /* Data Pin Bit Delay for MSIOF_SYNC */
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#define MDR1_SYNCDL_SHIFT 16 /* Frame Sync Signal Timing Delay */
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#define MDR1_FLD_MASK 0x0000000c /* Frame Sync Signal Interval (0-3) */
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#define MDR1_FLD_SHIFT 2
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#define MDR1_XXSTP 0x00000001 /* Transmission/Reception Stop on FIFO */
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@ -241,42 +243,80 @@ static irqreturn_t sh_msiof_spi_irq(int irq, void *data)
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static struct {
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unsigned short div;
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unsigned short scr;
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} const sh_msiof_spi_clk_table[] = {
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{ 1, SCR_BRPS( 1) | SCR_BRDV_DIV_1 },
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{ 2, SCR_BRPS( 1) | SCR_BRDV_DIV_2 },
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{ 4, SCR_BRPS( 1) | SCR_BRDV_DIV_4 },
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{ 8, SCR_BRPS( 1) | SCR_BRDV_DIV_8 },
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{ 16, SCR_BRPS( 1) | SCR_BRDV_DIV_16 },
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{ 32, SCR_BRPS( 1) | SCR_BRDV_DIV_32 },
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{ 64, SCR_BRPS(32) | SCR_BRDV_DIV_2 },
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{ 128, SCR_BRPS(32) | SCR_BRDV_DIV_4 },
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{ 256, SCR_BRPS(32) | SCR_BRDV_DIV_8 },
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{ 512, SCR_BRPS(32) | SCR_BRDV_DIV_16 },
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{ 1024, SCR_BRPS(32) | SCR_BRDV_DIV_32 },
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unsigned short brdv;
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} const sh_msiof_spi_div_table[] = {
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{ 1, SCR_BRDV_DIV_1 },
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{ 2, SCR_BRDV_DIV_2 },
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{ 4, SCR_BRDV_DIV_4 },
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{ 8, SCR_BRDV_DIV_8 },
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{ 16, SCR_BRDV_DIV_16 },
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{ 32, SCR_BRDV_DIV_32 },
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};
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static void sh_msiof_spi_set_clk_regs(struct sh_msiof_spi_priv *p,
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unsigned long parent_rate, u32 spi_hz)
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{
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unsigned long div = 1024;
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u32 brps, scr;
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size_t k;
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if (!WARN_ON(!spi_hz || !parent_rate))
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div = DIV_ROUND_UP(parent_rate, spi_hz);
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/* TODO: make more fine grained */
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for (k = 0; k < ARRAY_SIZE(sh_msiof_spi_clk_table); k++) {
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if (sh_msiof_spi_clk_table[k].div >= div)
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for (k = 0; k < ARRAY_SIZE(sh_msiof_spi_div_table); k++) {
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brps = DIV_ROUND_UP(div, sh_msiof_spi_div_table[k].div);
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if (brps <= 32) /* max of brdv is 32 */
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break;
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}
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k = min_t(int, k, ARRAY_SIZE(sh_msiof_spi_clk_table) - 1);
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k = min_t(int, k, ARRAY_SIZE(sh_msiof_spi_div_table) - 1);
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sh_msiof_write(p, TSCR, sh_msiof_spi_clk_table[k].scr);
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scr = sh_msiof_spi_div_table[k].brdv | SCR_BRPS(brps);
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sh_msiof_write(p, TSCR, scr);
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if (!(p->chipdata->master_flags & SPI_MASTER_MUST_TX))
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sh_msiof_write(p, RSCR, sh_msiof_spi_clk_table[k].scr);
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sh_msiof_write(p, RSCR, scr);
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}
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static u32 sh_msiof_get_delay_bit(u32 dtdl_or_syncdl)
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{
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/*
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* DTDL/SYNCDL bit : p->info->dtdl or p->info->syncdl
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* b'000 : 0
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* b'001 : 100
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* b'010 : 200
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* b'011 (SYNCDL only) : 300
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* b'101 : 50
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* b'110 : 150
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*/
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if (dtdl_or_syncdl % 100)
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return dtdl_or_syncdl / 100 + 5;
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else
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return dtdl_or_syncdl / 100;
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}
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static u32 sh_msiof_spi_get_dtdl_and_syncdl(struct sh_msiof_spi_priv *p)
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{
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u32 val;
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if (!p->info)
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return 0;
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/* check if DTDL and SYNCDL is allowed value */
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if (p->info->dtdl > 200 || p->info->syncdl > 300) {
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dev_warn(&p->pdev->dev, "DTDL or SYNCDL is too large\n");
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return 0;
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}
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/* check if the sum of DTDL and SYNCDL becomes an integer value */
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if ((p->info->dtdl + p->info->syncdl) % 100) {
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dev_warn(&p->pdev->dev, "the sum of DTDL/SYNCDL is not good\n");
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return 0;
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}
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val = sh_msiof_get_delay_bit(p->info->dtdl) << MDR1_DTDL_SHIFT;
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val |= sh_msiof_get_delay_bit(p->info->syncdl) << MDR1_SYNCDL_SHIFT;
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return val;
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}
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static void sh_msiof_spi_set_pin_regs(struct sh_msiof_spi_priv *p,
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@ -296,6 +336,7 @@ static void sh_msiof_spi_set_pin_regs(struct sh_msiof_spi_priv *p,
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tmp = MDR1_SYNCMD_SPI | 1 << MDR1_FLD_SHIFT | MDR1_XXSTP;
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tmp |= !cs_high << MDR1_SYNCAC_SHIFT;
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tmp |= lsb_first << MDR1_BITLSB_SHIFT;
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tmp |= sh_msiof_spi_get_dtdl_and_syncdl(p);
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sh_msiof_write(p, TMDR1, tmp | MDR1_TRMD | TMDR1_PCON);
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if (p->chipdata->master_flags & SPI_MASTER_MUST_TX) {
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/* These bits are reserved if RX needs TX */
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@ -501,7 +542,7 @@ static int sh_msiof_spi_setup(struct spi_device *spi)
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gpio_set_value(spi->cs_gpio, !(spi->mode & SPI_CS_HIGH));
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pm_runtime_put_sync(&p->pdev->dev);
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pm_runtime_put(&p->pdev->dev);
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return 0;
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}
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@ -595,8 +636,7 @@ static int sh_msiof_spi_txrx_once(struct sh_msiof_spi_priv *p,
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}
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/* wait for tx fifo to be emptied / rx fifo to be filled */
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ret = wait_for_completion_timeout(&p->done, HZ);
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if (!ret) {
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if (!wait_for_completion_timeout(&p->done, HZ)) {
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dev_err(&p->pdev->dev, "PIO timeout\n");
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ret = -ETIMEDOUT;
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goto stop_reset;
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@ -706,8 +746,7 @@ static int sh_msiof_dma_once(struct sh_msiof_spi_priv *p, const void *tx,
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}
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/* wait for tx fifo to be emptied / rx fifo to be filled */
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ret = wait_for_completion_timeout(&p->done, HZ);
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if (!ret) {
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if (!wait_for_completion_timeout(&p->done, HZ)) {
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dev_err(&p->pdev->dev, "DMA timeout\n");
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ret = -ETIMEDOUT;
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goto stop_reset;
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@ -957,6 +996,8 @@ static struct sh_msiof_spi_info *sh_msiof_spi_parse_dt(struct device *dev)
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&info->tx_fifo_override);
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of_property_read_u32(np, "renesas,rx-fifo-size",
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&info->rx_fifo_override);
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of_property_read_u32(np, "renesas,dtdl", &info->dtdl);
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of_property_read_u32(np, "renesas,syncdl", &info->syncdl);
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info->num_chipselect = num_cs;
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@ -7,6 +7,8 @@ struct sh_msiof_spi_info {
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u16 num_chipselect;
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unsigned int dma_tx_id;
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unsigned int dma_rx_id;
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u32 dtdl;
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u32 syncdl;
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};
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#endif /* __SPI_SH_MSIOF_H__ */
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