gpio: ixp4xx: Add driver for the IXP4xx GPIO
This adds a driver for the IXP4xx GPIO block found in the Intel XScale IXP4xx systems. The GPIO part of this block is pretty straight-forward and just uses the generic MMIO GPIO library. The irqchip side of this driver is hierarchical where the main irqchip will receive a processed level trigger in response to the edge detector of the GPIO block, so for this reason the v2 version of the irqdomain API is used (as well as in the parent IXP4xx irqchip) and masking, unmasking and setting up the type on IRQ happens on several levels. Currently this GPIO controller will grab the parent irqdomain using a special function, but as the platform move toward device tree probing, this will not be needed: we can just look up the parent irqdomain from the device tree. Cc: Bartosz Golaszewski <bgolaszewski@baylibre.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
This commit is contained in:
Linus Walleij
Родитель
5b978c1066
Коммит
813e7d36f2
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@ -1691,6 +1691,7 @@ M: Krzysztof Halasa <khalasa@piap.pl>
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L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
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S: Maintained
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F: arch/arm/mach-ixp4xx/
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F: drivers/gpio/gpio-ixp4xx.c
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F: drivers/irqchip/irq-ixp4xx.c
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F: include/linux/irqchip/irq-ixp4xx.h
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@ -287,6 +287,19 @@ config GPIO_IOP
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If unsure, say N.
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config GPIO_IXP4XX
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bool "Intel IXP4xx GPIO"
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depends on ARM # For <asm/mach-types.h>
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depends on ARCH_IXP4XX
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select GPIO_GENERIC
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select IRQ_DOMAIN
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select IRQ_DOMAIN_HIERARCHY
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help
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Say yes here to support the GPIO functionality of a number of Intel
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IXP4xx series of chips.
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If unsure, say N.
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config GPIO_LOONGSON
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bool "Loongson-2/3 GPIO support"
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depends on CPU_LOONGSON2 || CPU_LOONGSON3
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@ -61,6 +61,7 @@ obj-$(CONFIG_GPIO_HLWD) += gpio-hlwd.o
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obj-$(CONFIG_HTC_EGPIO) += gpio-htc-egpio.o
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obj-$(CONFIG_GPIO_ICH) += gpio-ich.o
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obj-$(CONFIG_GPIO_IOP) += gpio-iop.o
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obj-$(CONFIG_GPIO_IXP4XX) += gpio-ixp4xx.o
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obj-$(CONFIG_GPIO_IT87) += gpio-it87.o
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obj-$(CONFIG_GPIO_JANZ_TTL) += gpio-janz-ttl.o
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obj-$(CONFIG_GPIO_KEMPLD) += gpio-kempld.o
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@ -0,0 +1,444 @@
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// SPDX-License-Identifier: GPL-2.0
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//
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// IXP4 GPIO driver
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// Copyright (C) 2019 Linus Walleij <linus.walleij@linaro.org>
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//
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// based on previous work and know-how from:
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// Deepak Saxena <dsaxena@plexity.net>
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#include <linux/gpio/driver.h>
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#include <linux/io.h>
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#include <linux/irq.h>
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#include <linux/irqdomain.h>
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#include <linux/irqchip.h>
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#include <linux/platform_device.h>
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#include <linux/bitops.h>
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/* Include that go away with DT transition */
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#include <linux/irqchip/irq-ixp4xx.h>
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#include <asm/mach-types.h>
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#define IXP4XX_REG_GPOUT 0x00
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#define IXP4XX_REG_GPOE 0x04
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#define IXP4XX_REG_GPIN 0x08
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#define IXP4XX_REG_GPIS 0x0C
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#define IXP4XX_REG_GPIT1 0x10
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#define IXP4XX_REG_GPIT2 0x14
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#define IXP4XX_REG_GPCLK 0x18
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#define IXP4XX_REG_GPDBSEL 0x1C
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/*
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* The hardware uses 3 bits to indicate interrupt "style".
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* we clear and set these three bits accordingly. The lower 24
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* bits in two registers (GPIT1 and GPIT2) are used to set up
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* the style for 8 lines each for a total of 16 GPIO lines.
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*/
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#define IXP4XX_GPIO_STYLE_ACTIVE_HIGH 0x0
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#define IXP4XX_GPIO_STYLE_ACTIVE_LOW 0x1
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#define IXP4XX_GPIO_STYLE_RISING_EDGE 0x2
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#define IXP4XX_GPIO_STYLE_FALLING_EDGE 0x3
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#define IXP4XX_GPIO_STYLE_TRANSITIONAL 0x4
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#define IXP4XX_GPIO_STYLE_MASK GENMASK(2, 0)
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#define IXP4XX_GPIO_STYLE_SIZE 3
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/**
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* struct ixp4xx_gpio - IXP4 GPIO state container
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* @dev: containing device for this instance
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* @fwnode: the fwnode for this GPIO chip
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* @gc: gpiochip for this instance
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* @domain: irqdomain for this chip instance
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* @base: remapped I/O-memory base
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* @irq_edge: Each bit represents an IRQ: 1: edge-triggered,
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* 0: level triggered
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*/
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struct ixp4xx_gpio {
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struct device *dev;
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struct fwnode_handle *fwnode;
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struct gpio_chip gc;
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struct irq_domain *domain;
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void __iomem *base;
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unsigned long long irq_edge;
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};
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/**
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* struct ixp4xx_gpio_map - IXP4 GPIO to parent IRQ map
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* @gpio_offset: offset of the IXP4 GPIO line
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* @parent_hwirq: hwirq on the parent IRQ controller
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*/
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struct ixp4xx_gpio_map {
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int gpio_offset;
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int parent_hwirq;
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};
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/* GPIO lines 0..12 have corresponding IRQs, GPIOs 13..15 have no IRQs */
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const struct ixp4xx_gpio_map ixp4xx_gpiomap[] = {
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{ .gpio_offset = 0, .parent_hwirq = 6 },
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{ .gpio_offset = 1, .parent_hwirq = 7 },
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{ .gpio_offset = 2, .parent_hwirq = 19 },
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{ .gpio_offset = 3, .parent_hwirq = 20 },
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{ .gpio_offset = 4, .parent_hwirq = 21 },
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{ .gpio_offset = 5, .parent_hwirq = 22 },
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{ .gpio_offset = 6, .parent_hwirq = 23 },
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{ .gpio_offset = 7, .parent_hwirq = 24 },
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{ .gpio_offset = 8, .parent_hwirq = 25 },
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{ .gpio_offset = 9, .parent_hwirq = 26 },
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{ .gpio_offset = 10, .parent_hwirq = 27 },
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{ .gpio_offset = 11, .parent_hwirq = 28 },
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{ .gpio_offset = 12, .parent_hwirq = 29 },
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};
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static void ixp4xx_gpio_irq_ack(struct irq_data *d)
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{
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struct ixp4xx_gpio *g = irq_data_get_irq_chip_data(d);
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__raw_writel(BIT(d->hwirq), g->base + IXP4XX_REG_GPIS);
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}
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static void ixp4xx_gpio_irq_unmask(struct irq_data *d)
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{
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struct ixp4xx_gpio *g = irq_data_get_irq_chip_data(d);
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/* ACK when unmasking if not edge-triggered */
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if (!(g->irq_edge & BIT(d->hwirq)))
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ixp4xx_gpio_irq_ack(d);
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irq_chip_unmask_parent(d);
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}
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static int ixp4xx_gpio_irq_set_type(struct irq_data *d, unsigned int type)
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{
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struct ixp4xx_gpio *g = irq_data_get_irq_chip_data(d);
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int line = d->hwirq;
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unsigned long flags;
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u32 int_style;
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u32 int_reg;
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u32 val;
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switch (type) {
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case IRQ_TYPE_EDGE_BOTH:
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irq_set_handler_locked(d, handle_edge_irq);
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int_style = IXP4XX_GPIO_STYLE_TRANSITIONAL;
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g->irq_edge |= BIT(d->hwirq);
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break;
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case IRQ_TYPE_EDGE_RISING:
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irq_set_handler_locked(d, handle_edge_irq);
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int_style = IXP4XX_GPIO_STYLE_RISING_EDGE;
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g->irq_edge |= BIT(d->hwirq);
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break;
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case IRQ_TYPE_EDGE_FALLING:
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irq_set_handler_locked(d, handle_edge_irq);
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int_style = IXP4XX_GPIO_STYLE_FALLING_EDGE;
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g->irq_edge |= BIT(d->hwirq);
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break;
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case IRQ_TYPE_LEVEL_HIGH:
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irq_set_handler_locked(d, handle_level_irq);
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int_style = IXP4XX_GPIO_STYLE_ACTIVE_HIGH;
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g->irq_edge &= ~BIT(d->hwirq);
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break;
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case IRQ_TYPE_LEVEL_LOW:
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irq_set_handler_locked(d, handle_level_irq);
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int_style = IXP4XX_GPIO_STYLE_ACTIVE_LOW;
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g->irq_edge &= ~BIT(d->hwirq);
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break;
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default:
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return -EINVAL;
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}
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if (line >= 8) {
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/* pins 8-15 */
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line -= 8;
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int_reg = IXP4XX_REG_GPIT2;
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} else {
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/* pins 0-7 */
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int_reg = IXP4XX_REG_GPIT1;
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}
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spin_lock_irqsave(&g->gc.bgpio_lock, flags);
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/* Clear the style for the appropriate pin */
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val = __raw_readl(g->base + int_reg);
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val &= ~(IXP4XX_GPIO_STYLE_MASK << (line * IXP4XX_GPIO_STYLE_SIZE));
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__raw_writel(val, g->base + int_reg);
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__raw_writel(BIT(line), g->base + IXP4XX_REG_GPIS);
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/* Set the new style */
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val = __raw_readl(g->base + int_reg);
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val |= (int_style << (line * IXP4XX_GPIO_STYLE_SIZE));
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__raw_writel(val, g->base + int_reg);
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/* Force-configure this line as an input */
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val = __raw_readl(g->base + IXP4XX_REG_GPOE);
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val |= BIT(d->hwirq);
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__raw_writel(val, g->base + IXP4XX_REG_GPOE);
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spin_unlock_irqrestore(&g->gc.bgpio_lock, flags);
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/* This parent only accept level high (asserted) */
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return irq_chip_set_type_parent(d, IRQ_TYPE_LEVEL_HIGH);
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}
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static struct irq_chip ixp4xx_gpio_irqchip = {
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.name = "IXP4GPIO",
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.irq_ack = ixp4xx_gpio_irq_ack,
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.irq_mask = irq_chip_mask_parent,
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.irq_unmask = ixp4xx_gpio_irq_unmask,
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.irq_set_type = ixp4xx_gpio_irq_set_type,
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};
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static int ixp4xx_gpio_to_irq(struct gpio_chip *gc, unsigned int offset)
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{
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struct ixp4xx_gpio *g = gpiochip_get_data(gc);
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struct irq_fwspec fwspec;
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fwspec.fwnode = g->fwnode;
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fwspec.param_count = 2;
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fwspec.param[0] = offset;
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fwspec.param[1] = IRQ_TYPE_NONE;
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return irq_create_fwspec_mapping(&fwspec);
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}
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static int ixp4xx_gpio_irq_domain_translate(struct irq_domain *domain,
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struct irq_fwspec *fwspec,
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unsigned long *hwirq,
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unsigned int *type)
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{
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/* We support standard DT translation */
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if (is_of_node(fwspec->fwnode) && fwspec->param_count == 2) {
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*hwirq = fwspec->param[0];
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*type = fwspec->param[1];
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return 0;
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}
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/* This goes away when we transition to DT */
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if (is_fwnode_irqchip(fwspec->fwnode)) {
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if (fwspec->param_count != 2)
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return -EINVAL;
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*hwirq = fwspec->param[0];
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*type = fwspec->param[1];
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WARN_ON(*type == IRQ_TYPE_NONE);
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return 0;
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}
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return -EINVAL;
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}
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static int ixp4xx_gpio_irq_domain_alloc(struct irq_domain *d,
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unsigned int irq, unsigned int nr_irqs,
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void *data)
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{
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struct ixp4xx_gpio *g = d->host_data;
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irq_hw_number_t hwirq;
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unsigned int type = IRQ_TYPE_NONE;
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struct irq_fwspec *fwspec = data;
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int ret;
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int i;
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ret = ixp4xx_gpio_irq_domain_translate(d, fwspec, &hwirq, &type);
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if (ret)
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return ret;
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dev_dbg(g->dev, "allocate IRQ %d..%d, hwirq %lu..%lu\n",
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irq, irq + nr_irqs - 1,
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hwirq, hwirq + nr_irqs - 1);
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for (i = 0; i < nr_irqs; i++) {
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struct irq_fwspec parent_fwspec;
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const struct ixp4xx_gpio_map *map;
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int j;
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/* Not all lines support IRQs */
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for (j = 0; j < ARRAY_SIZE(ixp4xx_gpiomap); j++) {
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map = &ixp4xx_gpiomap[j];
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if (map->gpio_offset == hwirq)
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break;
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}
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if (j == ARRAY_SIZE(ixp4xx_gpiomap)) {
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dev_err(g->dev, "can't look up hwirq %lu\n", hwirq);
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return -EINVAL;
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}
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dev_dbg(g->dev, "found parent hwirq %u\n", map->parent_hwirq);
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/*
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* We set handle_bad_irq because the .set_type() should
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* always be invoked and set the right type of handler.
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*/
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irq_domain_set_info(d,
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irq + i,
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hwirq + i,
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&ixp4xx_gpio_irqchip,
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g,
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handle_bad_irq,
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NULL, NULL);
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irq_set_probe(irq + i);
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/*
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* Create a IRQ fwspec to send up to the parent irqdomain:
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* specify the hwirq we address on the parent and tie it
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* all together up the chain.
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*/
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parent_fwspec.fwnode = d->parent->fwnode;
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parent_fwspec.param_count = 2;
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parent_fwspec.param[0] = map->parent_hwirq;
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/* This parent only handles asserted level IRQs */
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parent_fwspec.param[1] = IRQ_TYPE_LEVEL_HIGH;
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dev_dbg(g->dev, "alloc_irqs_parent for %d parent hwirq %d\n",
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irq + i, map->parent_hwirq);
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ret = irq_domain_alloc_irqs_parent(d, irq + i, 1,
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&parent_fwspec);
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if (ret)
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dev_err(g->dev,
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"failed to allocate parent hwirq %d for hwirq %lu\n",
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map->parent_hwirq, hwirq);
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}
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return 0;
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}
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static const struct irq_domain_ops ixp4xx_gpio_irqdomain_ops = {
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.translate = ixp4xx_gpio_irq_domain_translate,
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.alloc = ixp4xx_gpio_irq_domain_alloc,
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.free = irq_domain_free_irqs_common,
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};
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static int ixp4xx_gpio_probe(struct platform_device *pdev)
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{
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unsigned long flags;
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struct device *dev = &pdev->dev;
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struct irq_domain *parent;
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struct resource *res;
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struct ixp4xx_gpio *g;
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int ret;
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int i;
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g = devm_kzalloc(dev, sizeof(*g), GFP_KERNEL);
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if (!g)
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return -ENOMEM;
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g->dev = dev;
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res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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g->base = devm_ioremap_resource(dev, res);
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if (IS_ERR(g->base)) {
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dev_err(dev, "ioremap error\n");
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return PTR_ERR(g->base);
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}
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/*
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* Make sure GPIO 14 and 15 are NOT used as clocks but GPIO on
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* specific machines.
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*/
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if (machine_is_dsmg600() || machine_is_nas100d())
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__raw_writel(0x0, g->base + IXP4XX_REG_GPCLK);
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/*
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* This is a very special big-endian ARM issue: when the IXP4xx is
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* run in big endian mode, all registers in the machine are switched
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* around to the CPU-native endianness. As you see mostly in the
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* driver we use __raw_readl()/__raw_writel() to access the registers
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* in the appropriate order. With the GPIO library we need to specify
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* byte order explicitly, so this flag needs to be set when compiling
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* for big endian.
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*/
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#if defined(CONFIG_CPU_BIG_ENDIAN)
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flags = BGPIOF_BIG_ENDIAN_BYTE_ORDER;
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#else
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flags = 0;
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#endif
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/* Populate and register gpio chip */
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ret = bgpio_init(&g->gc, dev, 4,
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g->base + IXP4XX_REG_GPIN,
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g->base + IXP4XX_REG_GPOUT,
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NULL,
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NULL,
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g->base + IXP4XX_REG_GPOE,
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flags);
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if (ret) {
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dev_err(dev, "unable to init generic GPIO\n");
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return ret;
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}
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g->gc.to_irq = ixp4xx_gpio_to_irq;
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g->gc.ngpio = 16;
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g->gc.label = "IXP4XX_GPIO_CHIP";
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/*
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* TODO: when we have migrated to device tree and all GPIOs
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* are fetched using phandles, set this to -1 to get rid of
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* the fixed gpiochip base.
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*/
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g->gc.base = 0;
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g->gc.parent = &pdev->dev;
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g->gc.owner = THIS_MODULE;
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ret = devm_gpiochip_add_data(dev, &g->gc, g);
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if (ret) {
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dev_err(dev, "failed to add SoC gpiochip\n");
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return ret;
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}
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/*
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* When we convert to device tree we will simply look up the
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||||
* parent irqdomain using irq_find_host(parent) as parent comes
|
||||
* from IRQCHIP_DECLARE(), then use of_node_to_fwnode() to get
|
||||
* the fwnode. For now we need this boardfile style code.
|
||||
*/
|
||||
parent = ixp4xx_get_irq_domain();
|
||||
g->fwnode = irq_domain_alloc_fwnode(g->base);
|
||||
if (!g->fwnode) {
|
||||
dev_err(dev, "no domain base\n");
|
||||
return -ENODEV;
|
||||
}
|
||||
g->domain = irq_domain_create_hierarchy(parent,
|
||||
IRQ_DOMAIN_FLAG_HIERARCHY,
|
||||
ARRAY_SIZE(ixp4xx_gpiomap),
|
||||
g->fwnode,
|
||||
&ixp4xx_gpio_irqdomain_ops,
|
||||
g);
|
||||
if (!g->domain) {
|
||||
irq_domain_free_fwnode(g->fwnode);
|
||||
dev_err(dev, "no hierarchical irq domain\n");
|
||||
return ret;
|
||||
}
|
||||
|
||||
/*
|
||||
* After adding OF support, this is no longer needed: irqs
|
||||
* will be allocated for the respective fwnodes.
|
||||
*/
|
||||
for (i = 0; i < ARRAY_SIZE(ixp4xx_gpiomap); i++) {
|
||||
const struct ixp4xx_gpio_map *map = &ixp4xx_gpiomap[i];
|
||||
struct irq_fwspec fwspec;
|
||||
|
||||
fwspec.fwnode = g->fwnode;
|
||||
/* This is the hwirq for the GPIO line side of things */
|
||||
fwspec.param[0] = map->gpio_offset;
|
||||
fwspec.param[1] = IRQ_TYPE_EDGE_RISING;
|
||||
fwspec.param_count = 2;
|
||||
ret = __irq_domain_alloc_irqs(g->domain,
|
||||
-1, /* just pick something */
|
||||
1,
|
||||
NUMA_NO_NODE,
|
||||
&fwspec,
|
||||
false,
|
||||
NULL);
|
||||
if (ret < 0) {
|
||||
irq_domain_free_fwnode(g->fwnode);
|
||||
dev_err(dev,
|
||||
"can not allocate irq for GPIO line %d parent hwirq %d in hierarchy domain: %d\n",
|
||||
map->gpio_offset, map->parent_hwirq, ret);
|
||||
return ret;
|
||||
}
|
||||
}
|
||||
|
||||
platform_set_drvdata(pdev, g);
|
||||
dev_info(dev, "IXP4 GPIO @%p registered\n", g->base);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static struct platform_driver ixp4xx_gpio_driver = {
|
||||
.driver = {
|
||||
.name = "ixp4xx-gpio",
|
||||
},
|
||||
.probe = ixp4xx_gpio_probe,
|
||||
};
|
||||
builtin_platform_driver(ixp4xx_gpio_driver);
|
||||
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