x86: add early quirk for reserving Intel graphics stolen memory v5
Systems with Intel graphics controllers set aside memory exclusively for
gfx driver use. This memory is not always marked in the E820 as
reserved or as RAM, and so is subject to overlap from E820 manipulation
later in the boot process. On some systems, MMIO space is allocated on
top, despite the efforts of the "RAM buffer" approach, which simply
rounds memory boundaries up to 64M to try to catch space that may decode
as RAM and so is not suitable for MMIO.
v2: use read_pci_config for 32 bit reads instead of adding a new one
(Chris)
add gen6 stolen size function (Chris)
v3: use a function pointer (Chris)
drop gen2 bits (Daniel)
v4: call e820_sanitize_map after adding the region
v5: fixup comments (Peter)
simplify loop (Chris)
Acked-by: Ingo Molnar <mingo@kernel.org>
Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Acked-by: H. Peter Anvin <hpa@zytor.com>
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=66726
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=66844
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
This commit is contained in:
Jesse Barnes
Daniel Vetter
Родитель
a0a1807544
Коммит
814c5f1f52
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@ -12,6 +12,7 @@
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#include <linux/pci.h>
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#include <linux/acpi.h>
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#include <linux/pci_ids.h>
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#include <drm/i915_drm.h>
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#include <asm/pci-direct.h>
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#include <asm/dma.h>
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#include <asm/io_apic.h>
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@ -216,6 +217,157 @@ static void __init intel_remapping_check(int num, int slot, int func)
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}
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/*
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* Systems with Intel graphics controllers set aside memory exclusively
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* for gfx driver use. This memory is not marked in the E820 as reserved
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* or as RAM, and so is subject to overlap from E820 manipulation later
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* in the boot process. On some systems, MMIO space is allocated on top,
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* despite the efforts of the "RAM buffer" approach, which simply rounds
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* memory boundaries up to 64M to try to catch space that may decode
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* as RAM and so is not suitable for MMIO.
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*
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* And yes, so far on current devices the base addr is always under 4G.
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*/
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static u32 __init intel_stolen_base(int num, int slot, int func)
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{
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u32 base;
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/*
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* For the PCI IDs in this quirk, the stolen base is always
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* in 0x5c, aka the BDSM register (yes that's really what
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* it's called).
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*/
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base = read_pci_config(num, slot, func, 0x5c);
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base &= ~((1<<20) - 1);
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return base;
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}
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#define KB(x) ((x) * 1024)
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#define MB(x) (KB (KB (x)))
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#define GB(x) (MB (KB (x)))
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static size_t __init gen3_stolen_size(int num, int slot, int func)
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{
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size_t stolen_size;
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u16 gmch_ctrl;
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gmch_ctrl = read_pci_config_16(0, 0, 0, I830_GMCH_CTRL);
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switch (gmch_ctrl & I855_GMCH_GMS_MASK) {
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case I855_GMCH_GMS_STOLEN_1M:
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stolen_size = MB(1);
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break;
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case I855_GMCH_GMS_STOLEN_4M:
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stolen_size = MB(4);
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break;
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case I855_GMCH_GMS_STOLEN_8M:
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stolen_size = MB(8);
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break;
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case I855_GMCH_GMS_STOLEN_16M:
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stolen_size = MB(16);
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break;
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case I855_GMCH_GMS_STOLEN_32M:
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stolen_size = MB(32);
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break;
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case I915_GMCH_GMS_STOLEN_48M:
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stolen_size = MB(48);
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break;
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case I915_GMCH_GMS_STOLEN_64M:
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stolen_size = MB(64);
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break;
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case G33_GMCH_GMS_STOLEN_128M:
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stolen_size = MB(128);
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break;
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case G33_GMCH_GMS_STOLEN_256M:
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stolen_size = MB(256);
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break;
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case INTEL_GMCH_GMS_STOLEN_96M:
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stolen_size = MB(96);
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break;
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case INTEL_GMCH_GMS_STOLEN_160M:
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stolen_size = MB(160);
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break;
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case INTEL_GMCH_GMS_STOLEN_224M:
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stolen_size = MB(224);
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break;
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case INTEL_GMCH_GMS_STOLEN_352M:
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stolen_size = MB(352);
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break;
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default:
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stolen_size = 0;
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break;
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}
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return stolen_size;
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}
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static size_t __init gen6_stolen_size(int num, int slot, int func)
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{
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u16 gmch_ctrl;
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gmch_ctrl = read_pci_config_16(num, slot, func, SNB_GMCH_CTRL);
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gmch_ctrl >>= SNB_GMCH_GMS_SHIFT;
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gmch_ctrl &= SNB_GMCH_GMS_MASK;
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return gmch_ctrl << 25; /* 32 MB units */
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}
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typedef size_t (*stolen_size_fn)(int num, int slot, int func);
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static struct pci_device_id intel_stolen_ids[] __initdata = {
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INTEL_I915G_IDS(gen3_stolen_size),
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INTEL_I915GM_IDS(gen3_stolen_size),
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INTEL_I945G_IDS(gen3_stolen_size),
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INTEL_I945GM_IDS(gen3_stolen_size),
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INTEL_VLV_M_IDS(gen3_stolen_size),
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INTEL_VLV_D_IDS(gen3_stolen_size),
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INTEL_PINEVIEW_IDS(gen3_stolen_size),
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INTEL_I965G_IDS(gen3_stolen_size),
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INTEL_G33_IDS(gen3_stolen_size),
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INTEL_I965GM_IDS(gen3_stolen_size),
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INTEL_GM45_IDS(gen3_stolen_size),
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INTEL_G45_IDS(gen3_stolen_size),
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INTEL_IRONLAKE_D_IDS(gen3_stolen_size),
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INTEL_IRONLAKE_M_IDS(gen3_stolen_size),
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INTEL_SNB_D_IDS(gen6_stolen_size),
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INTEL_SNB_M_IDS(gen6_stolen_size),
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INTEL_IVB_M_IDS(gen6_stolen_size),
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INTEL_IVB_D_IDS(gen6_stolen_size),
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INTEL_HSW_D_IDS(gen6_stolen_size),
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INTEL_HSW_M_IDS(gen6_stolen_size),
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};
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static void __init intel_graphics_stolen(int num, int slot, int func)
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{
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size_t size;
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int i;
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u32 start;
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u16 device, subvendor, subdevice;
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device = read_pci_config_16(num, slot, func, PCI_DEVICE_ID);
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subvendor = read_pci_config_16(num, slot, func,
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PCI_SUBSYSTEM_VENDOR_ID);
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subdevice = read_pci_config_16(num, slot, func, PCI_SUBSYSTEM_ID);
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for (i = 0; i < ARRAY_SIZE(intel_stolen_ids); i++) {
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if (intel_stolen_ids[i].device == device) {
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stolen_size_fn stolen_size =
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(stolen_size_fn)intel_stolen_ids[i].driver_data;
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size = stolen_size(num, slot, func);
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start = intel_stolen_base(num, slot, func);
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if (size && start) {
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/* Mark this space as reserved */
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e820_add_region(start, size, E820_RESERVED);
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sanitize_e820_map(e820.map,
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ARRAY_SIZE(e820.map),
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&e820.nr_map);
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}
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return;
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}
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}
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}
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#define QFLAG_APPLY_ONCE 0x1
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#define QFLAG_APPLIED 0x2
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#define QFLAG_DONE (QFLAG_APPLY_ONCE|QFLAG_APPLIED)
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@ -251,6 +403,8 @@ static struct chipset early_qrk[] __initdata = {
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PCI_BASE_CLASS_BRIDGE, 0, intel_remapping_check },
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{ PCI_VENDOR_ID_INTEL, 0x3406, PCI_CLASS_BRIDGE_HOST,
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PCI_BASE_CLASS_BRIDGE, 0, intel_remapping_check },
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{ PCI_VENDOR_ID_INTEL, PCI_ANY_ID, PCI_CLASS_DISPLAY_VGA, PCI_ANY_ID,
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QFLAG_APPLY_ONCE, intel_graphics_stolen },
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{}
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};
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@ -33,21 +33,6 @@
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#define _MASKED_BIT_ENABLE(a) (((a) << 16) | (a))
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#define _MASKED_BIT_DISABLE(a) ((a) << 16)
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/*
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* The Bridge device's PCI config space has information about the
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* fb aperture size and the amount of pre-reserved memory.
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* This is all handled in the intel-gtt.ko module. i915.ko only
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* cares about the vga bit for the vga rbiter.
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*/
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#define INTEL_GMCH_CTRL 0x52
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#define INTEL_GMCH_VGA_DISABLE (1 << 1)
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#define SNB_GMCH_CTRL 0x50
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#define SNB_GMCH_GGMS_SHIFT 8 /* GTT Graphics Memory Size */
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#define SNB_GMCH_GGMS_MASK 0x3
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#define SNB_GMCH_GMS_SHIFT 3 /* Graphics Mode Select */
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#define SNB_GMCH_GMS_MASK 0x1f
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/* PCI config space */
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#define HPLLCC 0xc0 /* 855 only */
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@ -36,4 +36,36 @@ extern bool i915_gpu_lower(void);
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extern bool i915_gpu_busy(void);
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extern bool i915_gpu_turbo_disable(void);
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/*
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* The Bridge device's PCI config space has information about the
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* fb aperture size and the amount of pre-reserved memory.
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* This is all handled in the intel-gtt.ko module. i915.ko only
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* cares about the vga bit for the vga rbiter.
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*/
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#define INTEL_GMCH_CTRL 0x52
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#define INTEL_GMCH_VGA_DISABLE (1 << 1)
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#define SNB_GMCH_CTRL 0x50
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#define SNB_GMCH_GGMS_SHIFT 8 /* GTT Graphics Memory Size */
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#define SNB_GMCH_GGMS_MASK 0x3
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#define SNB_GMCH_GMS_SHIFT 3 /* Graphics Mode Select */
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#define SNB_GMCH_GMS_MASK 0x1f
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#define I830_GMCH_CTRL 0x52
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#define I855_GMCH_GMS_MASK 0xF0
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#define I855_GMCH_GMS_STOLEN_0M 0x0
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#define I855_GMCH_GMS_STOLEN_1M (0x1 << 4)
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#define I855_GMCH_GMS_STOLEN_4M (0x2 << 4)
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#define I855_GMCH_GMS_STOLEN_8M (0x3 << 4)
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#define I855_GMCH_GMS_STOLEN_16M (0x4 << 4)
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#define I855_GMCH_GMS_STOLEN_32M (0x5 << 4)
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#define I915_GMCH_GMS_STOLEN_48M (0x6 << 4)
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#define I915_GMCH_GMS_STOLEN_64M (0x7 << 4)
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#define G33_GMCH_GMS_STOLEN_128M (0x8 << 4)
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#define G33_GMCH_GMS_STOLEN_256M (0x9 << 4)
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#define INTEL_GMCH_GMS_STOLEN_96M (0xa << 4)
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#define INTEL_GMCH_GMS_STOLEN_160M (0xb << 4)
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#define INTEL_GMCH_GMS_STOLEN_224M (0xc << 4)
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#define INTEL_GMCH_GMS_STOLEN_352M (0xd << 4)
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#endif /* _I915_DRM_H_ */
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