drm/amdgpu: Add unique_id and serial_number for Arcturus v3
Add support for unique_id and serial_number, as these are now the same value, and will be for future ASICs as well. v2: Explicitly create unique_id only for VG10/20/ARC v3: Change set_unique_id to get_unique_id for clarity Signed-off-by: Kent Russell <kent.russell@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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81a1624111
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@ -1940,7 +1940,9 @@ static int default_attr_update(struct amdgpu_device *adev, struct amdgpu_device_
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if (adev->flags & AMD_IS_APU)
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*states = ATTR_STATE_UNSUPPORTED;
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} else if (DEVICE_ATTR_IS(unique_id)) {
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if (!adev->unique_id)
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if (asic_type != CHIP_VEGA10 &&
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asic_type != CHIP_VEGA20 &&
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asic_type != CHIP_ARCTURUS)
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*states = ATTR_STATE_UNSUPPORTED;
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} else if (DEVICE_ATTR_IS(pp_features)) {
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if (adev->flags & AMD_IS_APU || asic_type < CHIP_VEGA10)
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@ -793,6 +793,8 @@ static int smu_late_init(void *handle)
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if (!smu->pm_enabled)
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return 0;
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smu_get_unique_id(smu);
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smu_handle_task(&adev->smu,
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smu->smu_dpm.dpm_level,
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AMD_PP_TASK_COMPLETE_INIT,
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@ -2262,6 +2262,37 @@ static void arcturus_i2c_eeprom_control_fini(struct i2c_adapter *control)
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i2c_del_adapter(control);
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}
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static void arcturus_get_unique_id(struct smu_context *smu)
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{
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struct amdgpu_device *adev = smu->adev;
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uint32_t top32, bottom32, smu_version, size;
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char sn[16];
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uint64_t id;
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if (smu_get_smc_version(smu, NULL, &smu_version)) {
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pr_warn("Failed to get smu version, cannot get unique_id or serial_number\n");
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return;
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}
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/* PPSMC_MSG_ReadSerial* is supported by 54.23.0 and onwards */
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if (smu_version < 0x361700) {
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pr_warn("ReadSerial is only supported by PMFW 54.23.0 and onwards\n");
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return;
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}
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/* Get the SN to turn into a Unique ID */
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smu_send_smc_msg(smu, SMU_MSG_ReadSerialNumTop32, &top32);
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smu_send_smc_msg(smu, SMU_MSG_ReadSerialNumBottom32, &bottom32);
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id = ((uint64_t)bottom32 << 32) | top32;
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adev->unique_id = id;
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/* For Arcturus-and-later, unique_id == serial_number, so convert it to a
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* 16-digit HEX string for convenience and backwards-compatibility
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*/
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size = sprintf(sn, "%llx", id);
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memcpy(adev->serial, &sn, size);
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}
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static bool arcturus_is_baco_supported(struct smu_context *smu)
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{
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struct amdgpu_device *adev = smu->adev;
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@ -2416,6 +2447,7 @@ static const struct pptable_funcs arcturus_ppt_funcs = {
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.dpm_set_uvd_enable = arcturus_dpm_set_uvd_enable,
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.i2c_eeprom_init = arcturus_i2c_eeprom_control_init,
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.i2c_eeprom_fini = arcturus_i2c_eeprom_control_fini,
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.get_unique_id = arcturus_get_unique_id,
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.init_microcode = smu_v11_0_init_microcode,
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.load_microcode = smu_v11_0_load_microcode,
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.init_smc_tables = smu_v11_0_init_smc_tables,
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@ -495,6 +495,7 @@ struct pptable_funcs {
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int (*update_pcie_parameters)(struct smu_context *smu, uint32_t pcie_gen_cap, uint32_t pcie_width_cap);
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int (*i2c_eeprom_init)(struct i2c_adapter *control);
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void (*i2c_eeprom_fini)(struct i2c_adapter *control);
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void (*get_unique_id)(struct smu_context *smu);
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int (*get_dpm_clock_table)(struct smu_context *smu, struct dpm_clocks *clock_table);
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int (*init_microcode)(struct smu_context *smu);
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int (*load_microcode)(struct smu_context *smu);
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@ -218,6 +218,8 @@ static inline int smu_send_smc_msg(struct smu_context *smu, enum smu_message_typ
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((smu)->ppt_funcs->i2c_eeprom_init ? (smu)->ppt_funcs->i2c_eeprom_init((control)) : 0)
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#define smu_i2c_eeprom_fini(smu, control) \
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((smu)->ppt_funcs->i2c_eeprom_fini ? (smu)->ppt_funcs->i2c_eeprom_fini((control)) : 0)
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#define smu_get_unique_id(smu) \
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((smu)->ppt_funcs->get_unique_id ? (smu)->ppt_funcs->get_unique_id((smu)) : 0)
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#define smu_log_thermal_throttling(smu) \
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((smu)->ppt_funcs->log_thermal_throttling_event ? (smu)->ppt_funcs->log_thermal_throttling_event((smu)) : 0)
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