Merge branch 'clk-qcom-rpm' into clk-next
* clk-qcom-rpm: clk: qcom: Add support for RPM Clocks clk: qcom: Add support for SMD-RPM Clocks clk: qcom: Always add factor clock for xo clocks
This commit is contained in:
Stephen Boyd
Коммит
81ab3279c5
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@ -0,0 +1,37 @@
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Qualcomm RPM Clock Controller Binding
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------------------------------------------------
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The RPM is a dedicated hardware engine for managing the shared
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SoC resources in order to keep the lowest power profile. It
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communicates with other hardware subsystems via shared memory
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and accepts clock requests, aggregates the requests and turns
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the clocks on/off or scales them on demand.
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Required properties :
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- compatible : shall contain only one of the following. The generic
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compatible "qcom,rpmcc" should be also included.
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"qcom,rpmcc-msm8916", "qcom,rpmcc"
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"qcom,rpmcc-apq8064", "qcom,rpmcc"
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- #clock-cells : shall contain 1
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Example:
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smd {
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compatible = "qcom,smd";
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rpm {
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interrupts = <0 168 1>;
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qcom,ipc = <&apcs 8 0>;
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qcom,smd-edge = <15>;
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rpm_requests {
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compatible = "qcom,rpm-msm8916";
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qcom,smd-channels = "rpm_requests";
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rpmcc: clock-controller {
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compatible = "qcom,rpmcc-msm8916", "qcom,rpmcc";
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#clock-cells = <1>;
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};
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};
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};
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};
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@ -2,6 +2,9 @@ config QCOM_GDSC
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bool
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select PM_GENERIC_DOMAINS if PM
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config QCOM_RPMCC
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bool
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config COMMON_CLK_QCOM
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tristate "Support for Qualcomm's clock controllers"
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depends on OF
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@ -9,6 +12,32 @@ config COMMON_CLK_QCOM
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select REGMAP_MMIO
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select RESET_CONTROLLER
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config QCOM_CLK_RPM
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tristate "RPM based Clock Controller"
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depends on COMMON_CLK_QCOM && MFD_QCOM_RPM
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select QCOM_RPMCC
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help
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The RPM (Resource Power Manager) is a dedicated hardware engine for
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managing the shared SoC resources in order to keep the lowest power
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profile. It communicates with other hardware subsystems via shared
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memory and accepts clock requests, aggregates the requests and turns
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the clocks on/off or scales them on demand.
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Say Y if you want to support the clocks exposed by the RPM on
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platforms such as apq8064, msm8660, msm8960 etc.
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config QCOM_CLK_SMD_RPM
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tristate "RPM over SMD based Clock Controller"
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depends on COMMON_CLK_QCOM && QCOM_SMD_RPM
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select QCOM_RPMCC
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help
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The RPM (Resource Power Manager) is a dedicated hardware engine for
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managing the shared SoC resources in order to keep the lowest power
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profile. It communicates with other hardware subsystems via shared
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memory and accepts clock requests, aggregates the requests and turns
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the clocks on/off or scales them on demand.
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Say Y if you want to support the clocks exposed by the RPM on
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platforms such as apq8016, apq8084, msm8974 etc.
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config APQ_GCC_8084
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tristate "APQ8084 Global Clock Controller"
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select QCOM_GDSC
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@ -30,3 +30,5 @@ obj-$(CONFIG_MSM_LCC_8960) += lcc-msm8960.o
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obj-$(CONFIG_MSM_MMCC_8960) += mmcc-msm8960.o
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obj-$(CONFIG_MSM_MMCC_8974) += mmcc-msm8974.o
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obj-$(CONFIG_MSM_MMCC_8996) += mmcc-msm8996.o
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obj-$(CONFIG_QCOM_CLK_RPM) += clk-rpm.o
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obj-$(CONFIG_QCOM_CLK_SMD_RPM) += clk-smd-rpm.o
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@ -0,0 +1,489 @@
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/*
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* Copyright (c) 2016, Linaro Limited
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* Copyright (c) 2014, The Linux Foundation. All rights reserved.
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*
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* This software is licensed under the terms of the GNU General Public
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* License version 2, as published by the Free Software Foundation, and
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* may be copied, distributed, and modified under those terms.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <linux/clk-provider.h>
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#include <linux/err.h>
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#include <linux/export.h>
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#include <linux/init.h>
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/mutex.h>
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#include <linux/mfd/qcom_rpm.h>
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#include <linux/of.h>
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#include <linux/of_device.h>
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#include <linux/platform_device.h>
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#include <dt-bindings/mfd/qcom-rpm.h>
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#include <dt-bindings/clock/qcom,rpmcc.h>
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#define QCOM_RPM_MISC_CLK_TYPE 0x306b6c63
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#define QCOM_RPM_SCALING_ENABLE_ID 0x2
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#define DEFINE_CLK_RPM(_platform, _name, _active, r_id) \
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static struct clk_rpm _platform##_##_active; \
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static struct clk_rpm _platform##_##_name = { \
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.rpm_clk_id = (r_id), \
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.peer = &_platform##_##_active, \
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.rate = INT_MAX, \
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.hw.init = &(struct clk_init_data){ \
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.ops = &clk_rpm_ops, \
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.name = #_name, \
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.parent_names = (const char *[]){ "pxo_board" }, \
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.num_parents = 1, \
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}, \
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}; \
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static struct clk_rpm _platform##_##_active = { \
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.rpm_clk_id = (r_id), \
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.peer = &_platform##_##_name, \
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.active_only = true, \
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.rate = INT_MAX, \
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.hw.init = &(struct clk_init_data){ \
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.ops = &clk_rpm_ops, \
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.name = #_active, \
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.parent_names = (const char *[]){ "pxo_board" }, \
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.num_parents = 1, \
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}, \
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}
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#define DEFINE_CLK_RPM_PXO_BRANCH(_platform, _name, _active, r_id, r) \
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static struct clk_rpm _platform##_##_active; \
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static struct clk_rpm _platform##_##_name = { \
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.rpm_clk_id = (r_id), \
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.active_only = true, \
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.peer = &_platform##_##_active, \
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.rate = (r), \
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.branch = true, \
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.hw.init = &(struct clk_init_data){ \
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.ops = &clk_rpm_branch_ops, \
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.name = #_name, \
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.parent_names = (const char *[]){ "pxo_board" }, \
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.num_parents = 1, \
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}, \
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}; \
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static struct clk_rpm _platform##_##_active = { \
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.rpm_clk_id = (r_id), \
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.peer = &_platform##_##_name, \
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.rate = (r), \
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.branch = true, \
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.hw.init = &(struct clk_init_data){ \
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.ops = &clk_rpm_branch_ops, \
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.name = #_active, \
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.parent_names = (const char *[]){ "pxo_board" }, \
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.num_parents = 1, \
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}, \
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}
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#define DEFINE_CLK_RPM_CXO_BRANCH(_platform, _name, _active, r_id, r) \
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static struct clk_rpm _platform##_##_active; \
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static struct clk_rpm _platform##_##_name = { \
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.rpm_clk_id = (r_id), \
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.peer = &_platform##_##_active, \
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.rate = (r), \
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.branch = true, \
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.hw.init = &(struct clk_init_data){ \
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.ops = &clk_rpm_branch_ops, \
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.name = #_name, \
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.parent_names = (const char *[]){ "cxo_board" }, \
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.num_parents = 1, \
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}, \
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}; \
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static struct clk_rpm _platform##_##_active = { \
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.rpm_clk_id = (r_id), \
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.active_only = true, \
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.peer = &_platform##_##_name, \
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.rate = (r), \
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.branch = true, \
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.hw.init = &(struct clk_init_data){ \
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.ops = &clk_rpm_branch_ops, \
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.name = #_active, \
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.parent_names = (const char *[]){ "cxo_board" }, \
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.num_parents = 1, \
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}, \
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}
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#define to_clk_rpm(_hw) container_of(_hw, struct clk_rpm, hw)
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struct clk_rpm {
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const int rpm_clk_id;
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const bool active_only;
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unsigned long rate;
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bool enabled;
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bool branch;
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struct clk_rpm *peer;
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struct clk_hw hw;
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struct qcom_rpm *rpm;
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};
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struct rpm_cc {
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struct qcom_rpm *rpm;
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struct clk_hw_onecell_data data;
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struct clk_hw *hws[];
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};
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struct rpm_clk_desc {
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struct clk_rpm **clks;
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size_t num_clks;
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};
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static DEFINE_MUTEX(rpm_clk_lock);
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static int clk_rpm_handoff(struct clk_rpm *r)
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{
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int ret;
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u32 value = INT_MAX;
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ret = qcom_rpm_write(r->rpm, QCOM_RPM_ACTIVE_STATE,
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r->rpm_clk_id, &value, 1);
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if (ret)
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return ret;
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ret = qcom_rpm_write(r->rpm, QCOM_RPM_SLEEP_STATE,
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r->rpm_clk_id, &value, 1);
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if (ret)
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return ret;
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return 0;
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}
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static int clk_rpm_set_rate_active(struct clk_rpm *r, unsigned long rate)
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{
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u32 value = DIV_ROUND_UP(rate, 1000); /* to kHz */
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return qcom_rpm_write(r->rpm, QCOM_RPM_ACTIVE_STATE,
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r->rpm_clk_id, &value, 1);
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}
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static int clk_rpm_set_rate_sleep(struct clk_rpm *r, unsigned long rate)
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{
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u32 value = DIV_ROUND_UP(rate, 1000); /* to kHz */
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return qcom_rpm_write(r->rpm, QCOM_RPM_SLEEP_STATE,
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r->rpm_clk_id, &value, 1);
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}
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static void to_active_sleep(struct clk_rpm *r, unsigned long rate,
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unsigned long *active, unsigned long *sleep)
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{
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*active = rate;
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/*
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* Active-only clocks don't care what the rate is during sleep. So,
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* they vote for zero.
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*/
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if (r->active_only)
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*sleep = 0;
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else
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*sleep = *active;
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}
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static int clk_rpm_prepare(struct clk_hw *hw)
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{
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struct clk_rpm *r = to_clk_rpm(hw);
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struct clk_rpm *peer = r->peer;
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unsigned long this_rate = 0, this_sleep_rate = 0;
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unsigned long peer_rate = 0, peer_sleep_rate = 0;
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unsigned long active_rate, sleep_rate;
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int ret = 0;
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mutex_lock(&rpm_clk_lock);
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/* Don't send requests to the RPM if the rate has not been set. */
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if (!r->rate)
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goto out;
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to_active_sleep(r, r->rate, &this_rate, &this_sleep_rate);
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/* Take peer clock's rate into account only if it's enabled. */
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if (peer->enabled)
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to_active_sleep(peer, peer->rate,
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&peer_rate, &peer_sleep_rate);
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active_rate = max(this_rate, peer_rate);
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|
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if (r->branch)
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active_rate = !!active_rate;
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|
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ret = clk_rpm_set_rate_active(r, active_rate);
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if (ret)
|
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goto out;
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||||
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sleep_rate = max(this_sleep_rate, peer_sleep_rate);
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if (r->branch)
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sleep_rate = !!sleep_rate;
|
||||
|
||||
ret = clk_rpm_set_rate_sleep(r, sleep_rate);
|
||||
if (ret)
|
||||
/* Undo the active set vote and restore it */
|
||||
ret = clk_rpm_set_rate_active(r, peer_rate);
|
||||
|
||||
out:
|
||||
if (!ret)
|
||||
r->enabled = true;
|
||||
|
||||
mutex_unlock(&rpm_clk_lock);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
static void clk_rpm_unprepare(struct clk_hw *hw)
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||||
{
|
||||
struct clk_rpm *r = to_clk_rpm(hw);
|
||||
struct clk_rpm *peer = r->peer;
|
||||
unsigned long peer_rate = 0, peer_sleep_rate = 0;
|
||||
unsigned long active_rate, sleep_rate;
|
||||
int ret;
|
||||
|
||||
mutex_lock(&rpm_clk_lock);
|
||||
|
||||
if (!r->rate)
|
||||
goto out;
|
||||
|
||||
/* Take peer clock's rate into account only if it's enabled. */
|
||||
if (peer->enabled)
|
||||
to_active_sleep(peer, peer->rate, &peer_rate,
|
||||
&peer_sleep_rate);
|
||||
|
||||
active_rate = r->branch ? !!peer_rate : peer_rate;
|
||||
ret = clk_rpm_set_rate_active(r, active_rate);
|
||||
if (ret)
|
||||
goto out;
|
||||
|
||||
sleep_rate = r->branch ? !!peer_sleep_rate : peer_sleep_rate;
|
||||
ret = clk_rpm_set_rate_sleep(r, sleep_rate);
|
||||
if (ret)
|
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goto out;
|
||||
|
||||
r->enabled = false;
|
||||
|
||||
out:
|
||||
mutex_unlock(&rpm_clk_lock);
|
||||
}
|
||||
|
||||
static int clk_rpm_set_rate(struct clk_hw *hw,
|
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unsigned long rate, unsigned long parent_rate)
|
||||
{
|
||||
struct clk_rpm *r = to_clk_rpm(hw);
|
||||
struct clk_rpm *peer = r->peer;
|
||||
unsigned long active_rate, sleep_rate;
|
||||
unsigned long this_rate = 0, this_sleep_rate = 0;
|
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unsigned long peer_rate = 0, peer_sleep_rate = 0;
|
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int ret = 0;
|
||||
|
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mutex_lock(&rpm_clk_lock);
|
||||
|
||||
if (!r->enabled)
|
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goto out;
|
||||
|
||||
to_active_sleep(r, rate, &this_rate, &this_sleep_rate);
|
||||
|
||||
/* Take peer clock's rate into account only if it's enabled. */
|
||||
if (peer->enabled)
|
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to_active_sleep(peer, peer->rate,
|
||||
&peer_rate, &peer_sleep_rate);
|
||||
|
||||
active_rate = max(this_rate, peer_rate);
|
||||
ret = clk_rpm_set_rate_active(r, active_rate);
|
||||
if (ret)
|
||||
goto out;
|
||||
|
||||
sleep_rate = max(this_sleep_rate, peer_sleep_rate);
|
||||
ret = clk_rpm_set_rate_sleep(r, sleep_rate);
|
||||
if (ret)
|
||||
goto out;
|
||||
|
||||
r->rate = rate;
|
||||
|
||||
out:
|
||||
mutex_unlock(&rpm_clk_lock);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
static long clk_rpm_round_rate(struct clk_hw *hw, unsigned long rate,
|
||||
unsigned long *parent_rate)
|
||||
{
|
||||
/*
|
||||
* RPM handles rate rounding and we don't have a way to
|
||||
* know what the rate will be, so just return whatever
|
||||
* rate is requested.
|
||||
*/
|
||||
return rate;
|
||||
}
|
||||
|
||||
static unsigned long clk_rpm_recalc_rate(struct clk_hw *hw,
|
||||
unsigned long parent_rate)
|
||||
{
|
||||
struct clk_rpm *r = to_clk_rpm(hw);
|
||||
|
||||
/*
|
||||
* RPM handles rate rounding and we don't have a way to
|
||||
* know what the rate will be, so just return whatever
|
||||
* rate was set.
|
||||
*/
|
||||
return r->rate;
|
||||
}
|
||||
|
||||
static const struct clk_ops clk_rpm_ops = {
|
||||
.prepare = clk_rpm_prepare,
|
||||
.unprepare = clk_rpm_unprepare,
|
||||
.set_rate = clk_rpm_set_rate,
|
||||
.round_rate = clk_rpm_round_rate,
|
||||
.recalc_rate = clk_rpm_recalc_rate,
|
||||
};
|
||||
|
||||
static const struct clk_ops clk_rpm_branch_ops = {
|
||||
.prepare = clk_rpm_prepare,
|
||||
.unprepare = clk_rpm_unprepare,
|
||||
.round_rate = clk_rpm_round_rate,
|
||||
.recalc_rate = clk_rpm_recalc_rate,
|
||||
};
|
||||
|
||||
/* apq8064 */
|
||||
DEFINE_CLK_RPM(apq8064, afab_clk, afab_a_clk, QCOM_RPM_APPS_FABRIC_CLK);
|
||||
DEFINE_CLK_RPM(apq8064, cfpb_clk, cfpb_a_clk, QCOM_RPM_CFPB_CLK);
|
||||
DEFINE_CLK_RPM(apq8064, daytona_clk, daytona_a_clk, QCOM_RPM_DAYTONA_FABRIC_CLK);
|
||||
DEFINE_CLK_RPM(apq8064, ebi1_clk, ebi1_a_clk, QCOM_RPM_EBI1_CLK);
|
||||
DEFINE_CLK_RPM(apq8064, mmfab_clk, mmfab_a_clk, QCOM_RPM_MM_FABRIC_CLK);
|
||||
DEFINE_CLK_RPM(apq8064, mmfpb_clk, mmfpb_a_clk, QCOM_RPM_MMFPB_CLK);
|
||||
DEFINE_CLK_RPM(apq8064, sfab_clk, sfab_a_clk, QCOM_RPM_SYS_FABRIC_CLK);
|
||||
DEFINE_CLK_RPM(apq8064, sfpb_clk, sfpb_a_clk, QCOM_RPM_SFPB_CLK);
|
||||
DEFINE_CLK_RPM(apq8064, qdss_clk, qdss_a_clk, QCOM_RPM_QDSS_CLK);
|
||||
|
||||
static struct clk_rpm *apq8064_clks[] = {
|
||||
[RPM_APPS_FABRIC_CLK] = &apq8064_afab_clk,
|
||||
[RPM_APPS_FABRIC_A_CLK] = &apq8064_afab_a_clk,
|
||||
[RPM_CFPB_CLK] = &apq8064_cfpb_clk,
|
||||
[RPM_CFPB_A_CLK] = &apq8064_cfpb_a_clk,
|
||||
[RPM_DAYTONA_FABRIC_CLK] = &apq8064_daytona_clk,
|
||||
[RPM_DAYTONA_FABRIC_A_CLK] = &apq8064_daytona_a_clk,
|
||||
[RPM_EBI1_CLK] = &apq8064_ebi1_clk,
|
||||
[RPM_EBI1_A_CLK] = &apq8064_ebi1_a_clk,
|
||||
[RPM_MM_FABRIC_CLK] = &apq8064_mmfab_clk,
|
||||
[RPM_MM_FABRIC_A_CLK] = &apq8064_mmfab_a_clk,
|
||||
[RPM_MMFPB_CLK] = &apq8064_mmfpb_clk,
|
||||
[RPM_MMFPB_A_CLK] = &apq8064_mmfpb_a_clk,
|
||||
[RPM_SYS_FABRIC_CLK] = &apq8064_sfab_clk,
|
||||
[RPM_SYS_FABRIC_A_CLK] = &apq8064_sfab_a_clk,
|
||||
[RPM_SFPB_CLK] = &apq8064_sfpb_clk,
|
||||
[RPM_SFPB_A_CLK] = &apq8064_sfpb_a_clk,
|
||||
[RPM_QDSS_CLK] = &apq8064_qdss_clk,
|
||||
[RPM_QDSS_A_CLK] = &apq8064_qdss_a_clk,
|
||||
};
|
||||
|
||||
static const struct rpm_clk_desc rpm_clk_apq8064 = {
|
||||
.clks = apq8064_clks,
|
||||
.num_clks = ARRAY_SIZE(apq8064_clks),
|
||||
};
|
||||
|
||||
static const struct of_device_id rpm_clk_match_table[] = {
|
||||
{ .compatible = "qcom,rpmcc-apq8064", .data = &rpm_clk_apq8064 },
|
||||
{ }
|
||||
};
|
||||
MODULE_DEVICE_TABLE(of, rpm_clk_match_table);
|
||||
|
||||
static int rpm_clk_probe(struct platform_device *pdev)
|
||||
{
|
||||
struct clk_hw **hws;
|
||||
struct rpm_cc *rcc;
|
||||
struct clk_hw_onecell_data *data;
|
||||
int ret;
|
||||
size_t num_clks, i;
|
||||
struct qcom_rpm *rpm;
|
||||
struct clk_rpm **rpm_clks;
|
||||
const struct rpm_clk_desc *desc;
|
||||
|
||||
rpm = dev_get_drvdata(pdev->dev.parent);
|
||||
if (!rpm) {
|
||||
dev_err(&pdev->dev, "Unable to retrieve handle to RPM\n");
|
||||
return -ENODEV;
|
||||
}
|
||||
|
||||
desc = of_device_get_match_data(&pdev->dev);
|
||||
if (!desc)
|
||||
return -EINVAL;
|
||||
|
||||
rpm_clks = desc->clks;
|
||||
num_clks = desc->num_clks;
|
||||
|
||||
rcc = devm_kzalloc(&pdev->dev, sizeof(*rcc) + sizeof(*hws) * num_clks,
|
||||
GFP_KERNEL);
|
||||
if (!rcc)
|
||||
return -ENOMEM;
|
||||
|
||||
hws = rcc->hws;
|
||||
data = &rcc->data;
|
||||
data->num = num_clks;
|
||||
|
||||
for (i = 0; i < num_clks; i++) {
|
||||
if (!rpm_clks[i])
|
||||
continue;
|
||||
|
||||
rpm_clks[i]->rpm = rpm;
|
||||
|
||||
ret = clk_rpm_handoff(rpm_clks[i]);
|
||||
if (ret)
|
||||
goto err;
|
||||
}
|
||||
|
||||
for (i = 0; i < num_clks; i++) {
|
||||
if (!rpm_clks[i]) {
|
||||
data->hws[i] = ERR_PTR(-ENOENT);
|
||||
continue;
|
||||
}
|
||||
|
||||
ret = devm_clk_hw_register(&pdev->dev, &rpm_clks[i]->hw);
|
||||
if (ret)
|
||||
goto err;
|
||||
}
|
||||
|
||||
ret = of_clk_add_hw_provider(pdev->dev.of_node, of_clk_hw_onecell_get,
|
||||
data);
|
||||
if (ret)
|
||||
goto err;
|
||||
|
||||
return 0;
|
||||
err:
|
||||
dev_err(&pdev->dev, "Error registering RPM Clock driver (%d)\n", ret);
|
||||
return ret;
|
||||
}
|
||||
|
||||
static int rpm_clk_remove(struct platform_device *pdev)
|
||||
{
|
||||
of_clk_del_provider(pdev->dev.of_node);
|
||||
return 0;
|
||||
}
|
||||
|
||||
static struct platform_driver rpm_clk_driver = {
|
||||
.driver = {
|
||||
.name = "qcom-clk-rpm",
|
||||
.of_match_table = rpm_clk_match_table,
|
||||
},
|
||||
.probe = rpm_clk_probe,
|
||||
.remove = rpm_clk_remove,
|
||||
};
|
||||
|
||||
static int __init rpm_clk_init(void)
|
||||
{
|
||||
return platform_driver_register(&rpm_clk_driver);
|
||||
}
|
||||
core_initcall(rpm_clk_init);
|
||||
|
||||
static void __exit rpm_clk_exit(void)
|
||||
{
|
||||
platform_driver_unregister(&rpm_clk_driver);
|
||||
}
|
||||
module_exit(rpm_clk_exit);
|
||||
|
||||
MODULE_DESCRIPTION("Qualcomm RPM Clock Controller Driver");
|
||||
MODULE_LICENSE("GPL v2");
|
||||
MODULE_ALIAS("platform:qcom-clk-rpm");
|
||||
|
|
@ -0,0 +1,570 @@
|
|||
/*
|
||||
* Copyright (c) 2016, Linaro Limited
|
||||
* Copyright (c) 2014, The Linux Foundation. All rights reserved.
|
||||
*
|
||||
* This software is licensed under the terms of the GNU General Public
|
||||
* License version 2, as published by the Free Software Foundation, and
|
||||
* may be copied, distributed, and modified under those terms.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#include <linux/clk-provider.h>
|
||||
#include <linux/err.h>
|
||||
#include <linux/export.h>
|
||||
#include <linux/init.h>
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/module.h>
|
||||
#include <linux/mutex.h>
|
||||
#include <linux/of.h>
|
||||
#include <linux/of_device.h>
|
||||
#include <linux/platform_device.h>
|
||||
#include <linux/soc/qcom/smd-rpm.h>
|
||||
|
||||
#include <dt-bindings/clock/qcom,rpmcc.h>
|
||||
#include <dt-bindings/mfd/qcom-rpm.h>
|
||||
|
||||
#define QCOM_RPM_KEY_SOFTWARE_ENABLE 0x6e657773
|
||||
#define QCOM_RPM_KEY_PIN_CTRL_CLK_BUFFER_ENABLE_KEY 0x62636370
|
||||
#define QCOM_RPM_SMD_KEY_RATE 0x007a484b
|
||||
#define QCOM_RPM_SMD_KEY_ENABLE 0x62616e45
|
||||
#define QCOM_RPM_SMD_KEY_STATE 0x54415453
|
||||
#define QCOM_RPM_SCALING_ENABLE_ID 0x2
|
||||
|
||||
#define __DEFINE_CLK_SMD_RPM(_platform, _name, _active, type, r_id, stat_id, \
|
||||
key) \
|
||||
static struct clk_smd_rpm _platform##_##_active; \
|
||||
static struct clk_smd_rpm _platform##_##_name = { \
|
||||
.rpm_res_type = (type), \
|
||||
.rpm_clk_id = (r_id), \
|
||||
.rpm_status_id = (stat_id), \
|
||||
.rpm_key = (key), \
|
||||
.peer = &_platform##_##_active, \
|
||||
.rate = INT_MAX, \
|
||||
.hw.init = &(struct clk_init_data){ \
|
||||
.ops = &clk_smd_rpm_ops, \
|
||||
.name = #_name, \
|
||||
.parent_names = (const char *[]){ "xo_board" }, \
|
||||
.num_parents = 1, \
|
||||
}, \
|
||||
}; \
|
||||
static struct clk_smd_rpm _platform##_##_active = { \
|
||||
.rpm_res_type = (type), \
|
||||
.rpm_clk_id = (r_id), \
|
||||
.rpm_status_id = (stat_id), \
|
||||
.active_only = true, \
|
||||
.rpm_key = (key), \
|
||||
.peer = &_platform##_##_name, \
|
||||
.rate = INT_MAX, \
|
||||
.hw.init = &(struct clk_init_data){ \
|
||||
.ops = &clk_smd_rpm_ops, \
|
||||
.name = #_active, \
|
||||
.parent_names = (const char *[]){ "xo_board" }, \
|
||||
.num_parents = 1, \
|
||||
}, \
|
||||
}
|
||||
|
||||
#define __DEFINE_CLK_SMD_RPM_BRANCH(_platform, _name, _active, type, r_id, \
|
||||
stat_id, r, key) \
|
||||
static struct clk_smd_rpm _platform##_##_active; \
|
||||
static struct clk_smd_rpm _platform##_##_name = { \
|
||||
.rpm_res_type = (type), \
|
||||
.rpm_clk_id = (r_id), \
|
||||
.rpm_status_id = (stat_id), \
|
||||
.rpm_key = (key), \
|
||||
.branch = true, \
|
||||
.peer = &_platform##_##_active, \
|
||||
.rate = (r), \
|
||||
.hw.init = &(struct clk_init_data){ \
|
||||
.ops = &clk_smd_rpm_branch_ops, \
|
||||
.name = #_name, \
|
||||
.parent_names = (const char *[]){ "xo_board" }, \
|
||||
.num_parents = 1, \
|
||||
}, \
|
||||
}; \
|
||||
static struct clk_smd_rpm _platform##_##_active = { \
|
||||
.rpm_res_type = (type), \
|
||||
.rpm_clk_id = (r_id), \
|
||||
.rpm_status_id = (stat_id), \
|
||||
.active_only = true, \
|
||||
.rpm_key = (key), \
|
||||
.branch = true, \
|
||||
.peer = &_platform##_##_name, \
|
||||
.rate = (r), \
|
||||
.hw.init = &(struct clk_init_data){ \
|
||||
.ops = &clk_smd_rpm_branch_ops, \
|
||||
.name = #_active, \
|
||||
.parent_names = (const char *[]){ "xo_board" }, \
|
||||
.num_parents = 1, \
|
||||
}, \
|
||||
}
|
||||
|
||||
#define DEFINE_CLK_SMD_RPM(_platform, _name, _active, type, r_id) \
|
||||
__DEFINE_CLK_SMD_RPM(_platform, _name, _active, type, r_id, \
|
||||
0, QCOM_RPM_SMD_KEY_RATE)
|
||||
|
||||
#define DEFINE_CLK_SMD_RPM_BRANCH(_platform, _name, _active, type, r_id, r) \
|
||||
__DEFINE_CLK_SMD_RPM_BRANCH(_platform, _name, _active, type, \
|
||||
r_id, 0, r, QCOM_RPM_SMD_KEY_ENABLE)
|
||||
|
||||
#define DEFINE_CLK_SMD_RPM_QDSS(_platform, _name, _active, type, r_id) \
|
||||
__DEFINE_CLK_SMD_RPM(_platform, _name, _active, type, r_id, \
|
||||
0, QCOM_RPM_SMD_KEY_STATE)
|
||||
|
||||
#define DEFINE_CLK_SMD_RPM_XO_BUFFER(_platform, _name, _active, r_id) \
|
||||
__DEFINE_CLK_SMD_RPM_BRANCH(_platform, _name, _active, \
|
||||
QCOM_SMD_RPM_CLK_BUF_A, r_id, 0, 1000, \
|
||||
QCOM_RPM_KEY_SOFTWARE_ENABLE)
|
||||
|
||||
#define DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(_platform, _name, _active, r_id) \
|
||||
__DEFINE_CLK_SMD_RPM_BRANCH(_platform, _name, _active, \
|
||||
QCOM_SMD_RPM_CLK_BUF_A, r_id, 0, 1000, \
|
||||
QCOM_RPM_KEY_PIN_CTRL_CLK_BUFFER_ENABLE_KEY)
|
||||
|
||||
#define to_clk_smd_rpm(_hw) container_of(_hw, struct clk_smd_rpm, hw)
|
||||
|
||||
struct clk_smd_rpm {
|
||||
const int rpm_res_type;
|
||||
const int rpm_key;
|
||||
const int rpm_clk_id;
|
||||
const int rpm_status_id;
|
||||
const bool active_only;
|
||||
bool enabled;
|
||||
bool branch;
|
||||
struct clk_smd_rpm *peer;
|
||||
struct clk_hw hw;
|
||||
unsigned long rate;
|
||||
struct qcom_smd_rpm *rpm;
|
||||
};
|
||||
|
||||
struct clk_smd_rpm_req {
|
||||
__le32 key;
|
||||
__le32 nbytes;
|
||||
__le32 value;
|
||||
};
|
||||
|
||||
struct rpm_cc {
|
||||
struct qcom_rpm *rpm;
|
||||
struct clk_hw_onecell_data data;
|
||||
struct clk_hw *hws[];
|
||||
};
|
||||
|
||||
struct rpm_smd_clk_desc {
|
||||
struct clk_smd_rpm **clks;
|
||||
size_t num_clks;
|
||||
};
|
||||
|
||||
static DEFINE_MUTEX(rpm_smd_clk_lock);
|
||||
|
||||
static int clk_smd_rpm_handoff(struct clk_smd_rpm *r)
|
||||
{
|
||||
int ret;
|
||||
struct clk_smd_rpm_req req = {
|
||||
.key = cpu_to_le32(r->rpm_key),
|
||||
.nbytes = cpu_to_le32(sizeof(u32)),
|
||||
.value = cpu_to_le32(INT_MAX),
|
||||
};
|
||||
|
||||
ret = qcom_rpm_smd_write(r->rpm, QCOM_SMD_RPM_ACTIVE_STATE,
|
||||
r->rpm_res_type, r->rpm_clk_id, &req,
|
||||
sizeof(req));
|
||||
if (ret)
|
||||
return ret;
|
||||
ret = qcom_rpm_smd_write(r->rpm, QCOM_SMD_RPM_SLEEP_STATE,
|
||||
r->rpm_res_type, r->rpm_clk_id, &req,
|
||||
sizeof(req));
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int clk_smd_rpm_set_rate_active(struct clk_smd_rpm *r,
|
||||
unsigned long rate)
|
||||
{
|
||||
struct clk_smd_rpm_req req = {
|
||||
.key = cpu_to_le32(r->rpm_key),
|
||||
.nbytes = cpu_to_le32(sizeof(u32)),
|
||||
.value = cpu_to_le32(DIV_ROUND_UP(rate, 1000)), /* to kHz */
|
||||
};
|
||||
|
||||
return qcom_rpm_smd_write(r->rpm, QCOM_SMD_RPM_ACTIVE_STATE,
|
||||
r->rpm_res_type, r->rpm_clk_id, &req,
|
||||
sizeof(req));
|
||||
}
|
||||
|
||||
static int clk_smd_rpm_set_rate_sleep(struct clk_smd_rpm *r,
|
||||
unsigned long rate)
|
||||
{
|
||||
struct clk_smd_rpm_req req = {
|
||||
.key = cpu_to_le32(r->rpm_key),
|
||||
.nbytes = cpu_to_le32(sizeof(u32)),
|
||||
.value = cpu_to_le32(DIV_ROUND_UP(rate, 1000)), /* to kHz */
|
||||
};
|
||||
|
||||
return qcom_rpm_smd_write(r->rpm, QCOM_SMD_RPM_SLEEP_STATE,
|
||||
r->rpm_res_type, r->rpm_clk_id, &req,
|
||||
sizeof(req));
|
||||
}
|
||||
|
||||
static void to_active_sleep(struct clk_smd_rpm *r, unsigned long rate,
|
||||
unsigned long *active, unsigned long *sleep)
|
||||
{
|
||||
*active = rate;
|
||||
|
||||
/*
|
||||
* Active-only clocks don't care what the rate is during sleep. So,
|
||||
* they vote for zero.
|
||||
*/
|
||||
if (r->active_only)
|
||||
*sleep = 0;
|
||||
else
|
||||
*sleep = *active;
|
||||
}
|
||||
|
||||
static int clk_smd_rpm_prepare(struct clk_hw *hw)
|
||||
{
|
||||
struct clk_smd_rpm *r = to_clk_smd_rpm(hw);
|
||||
struct clk_smd_rpm *peer = r->peer;
|
||||
unsigned long this_rate = 0, this_sleep_rate = 0;
|
||||
unsigned long peer_rate = 0, peer_sleep_rate = 0;
|
||||
unsigned long active_rate, sleep_rate;
|
||||
int ret = 0;
|
||||
|
||||
mutex_lock(&rpm_smd_clk_lock);
|
||||
|
||||
/* Don't send requests to the RPM if the rate has not been set. */
|
||||
if (!r->rate)
|
||||
goto out;
|
||||
|
||||
to_active_sleep(r, r->rate, &this_rate, &this_sleep_rate);
|
||||
|
||||
/* Take peer clock's rate into account only if it's enabled. */
|
||||
if (peer->enabled)
|
||||
to_active_sleep(peer, peer->rate,
|
||||
&peer_rate, &peer_sleep_rate);
|
||||
|
||||
active_rate = max(this_rate, peer_rate);
|
||||
|
||||
if (r->branch)
|
||||
active_rate = !!active_rate;
|
||||
|
||||
ret = clk_smd_rpm_set_rate_active(r, active_rate);
|
||||
if (ret)
|
||||
goto out;
|
||||
|
||||
sleep_rate = max(this_sleep_rate, peer_sleep_rate);
|
||||
if (r->branch)
|
||||
sleep_rate = !!sleep_rate;
|
||||
|
||||
ret = clk_smd_rpm_set_rate_sleep(r, sleep_rate);
|
||||
if (ret)
|
||||
/* Undo the active set vote and restore it */
|
||||
ret = clk_smd_rpm_set_rate_active(r, peer_rate);
|
||||
|
||||
out:
|
||||
if (!ret)
|
||||
r->enabled = true;
|
||||
|
||||
mutex_unlock(&rpm_smd_clk_lock);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
static void clk_smd_rpm_unprepare(struct clk_hw *hw)
|
||||
{
|
||||
struct clk_smd_rpm *r = to_clk_smd_rpm(hw);
|
||||
struct clk_smd_rpm *peer = r->peer;
|
||||
unsigned long peer_rate = 0, peer_sleep_rate = 0;
|
||||
unsigned long active_rate, sleep_rate;
|
||||
int ret;
|
||||
|
||||
mutex_lock(&rpm_smd_clk_lock);
|
||||
|
||||
if (!r->rate)
|
||||
goto out;
|
||||
|
||||
/* Take peer clock's rate into account only if it's enabled. */
|
||||
if (peer->enabled)
|
||||
to_active_sleep(peer, peer->rate, &peer_rate,
|
||||
&peer_sleep_rate);
|
||||
|
||||
active_rate = r->branch ? !!peer_rate : peer_rate;
|
||||
ret = clk_smd_rpm_set_rate_active(r, active_rate);
|
||||
if (ret)
|
||||
goto out;
|
||||
|
||||
sleep_rate = r->branch ? !!peer_sleep_rate : peer_sleep_rate;
|
||||
ret = clk_smd_rpm_set_rate_sleep(r, sleep_rate);
|
||||
if (ret)
|
||||
goto out;
|
||||
|
||||
r->enabled = false;
|
||||
|
||||
out:
|
||||
mutex_unlock(&rpm_smd_clk_lock);
|
||||
}
|
||||
|
||||
static int clk_smd_rpm_set_rate(struct clk_hw *hw, unsigned long rate,
|
||||
unsigned long parent_rate)
|
||||
{
|
||||
struct clk_smd_rpm *r = to_clk_smd_rpm(hw);
|
||||
struct clk_smd_rpm *peer = r->peer;
|
||||
unsigned long active_rate, sleep_rate;
|
||||
unsigned long this_rate = 0, this_sleep_rate = 0;
|
||||
unsigned long peer_rate = 0, peer_sleep_rate = 0;
|
||||
int ret = 0;
|
||||
|
||||
mutex_lock(&rpm_smd_clk_lock);
|
||||
|
||||
if (!r->enabled)
|
||||
goto out;
|
||||
|
||||
to_active_sleep(r, rate, &this_rate, &this_sleep_rate);
|
||||
|
||||
/* Take peer clock's rate into account only if it's enabled. */
|
||||
if (peer->enabled)
|
||||
to_active_sleep(peer, peer->rate,
|
||||
&peer_rate, &peer_sleep_rate);
|
||||
|
||||
active_rate = max(this_rate, peer_rate);
|
||||
ret = clk_smd_rpm_set_rate_active(r, active_rate);
|
||||
if (ret)
|
||||
goto out;
|
||||
|
||||
sleep_rate = max(this_sleep_rate, peer_sleep_rate);
|
||||
ret = clk_smd_rpm_set_rate_sleep(r, sleep_rate);
|
||||
if (ret)
|
||||
goto out;
|
||||
|
||||
r->rate = rate;
|
||||
|
||||
out:
|
||||
mutex_unlock(&rpm_smd_clk_lock);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
static long clk_smd_rpm_round_rate(struct clk_hw *hw, unsigned long rate,
|
||||
unsigned long *parent_rate)
|
||||
{
|
||||
/*
|
||||
* RPM handles rate rounding and we don't have a way to
|
||||
* know what the rate will be, so just return whatever
|
||||
* rate is requested.
|
||||
*/
|
||||
return rate;
|
||||
}
|
||||
|
||||
static unsigned long clk_smd_rpm_recalc_rate(struct clk_hw *hw,
|
||||
unsigned long parent_rate)
|
||||
{
|
||||
struct clk_smd_rpm *r = to_clk_smd_rpm(hw);
|
||||
|
||||
/*
|
||||
* RPM handles rate rounding and we don't have a way to
|
||||
* know what the rate will be, so just return whatever
|
||||
* rate was set.
|
||||
*/
|
||||
return r->rate;
|
||||
}
|
||||
|
||||
static int clk_smd_rpm_enable_scaling(struct qcom_smd_rpm *rpm)
|
||||
{
|
||||
int ret;
|
||||
struct clk_smd_rpm_req req = {
|
||||
.key = cpu_to_le32(QCOM_RPM_SMD_KEY_ENABLE),
|
||||
.nbytes = cpu_to_le32(sizeof(u32)),
|
||||
.value = cpu_to_le32(1),
|
||||
};
|
||||
|
||||
ret = qcom_rpm_smd_write(rpm, QCOM_SMD_RPM_SLEEP_STATE,
|
||||
QCOM_SMD_RPM_MISC_CLK,
|
||||
QCOM_RPM_SCALING_ENABLE_ID, &req, sizeof(req));
|
||||
if (ret) {
|
||||
pr_err("RPM clock scaling (sleep set) not enabled!\n");
|
||||
return ret;
|
||||
}
|
||||
|
||||
ret = qcom_rpm_smd_write(rpm, QCOM_SMD_RPM_ACTIVE_STATE,
|
||||
QCOM_SMD_RPM_MISC_CLK,
|
||||
QCOM_RPM_SCALING_ENABLE_ID, &req, sizeof(req));
|
||||
if (ret) {
|
||||
pr_err("RPM clock scaling (active set) not enabled!\n");
|
||||
return ret;
|
||||
}
|
||||
|
||||
pr_debug("%s: RPM clock scaling is enabled\n", __func__);
|
||||
return 0;
|
||||
}
|
||||
|
||||
static const struct clk_ops clk_smd_rpm_ops = {
|
||||
.prepare = clk_smd_rpm_prepare,
|
||||
.unprepare = clk_smd_rpm_unprepare,
|
||||
.set_rate = clk_smd_rpm_set_rate,
|
||||
.round_rate = clk_smd_rpm_round_rate,
|
||||
.recalc_rate = clk_smd_rpm_recalc_rate,
|
||||
};
|
||||
|
||||
static const struct clk_ops clk_smd_rpm_branch_ops = {
|
||||
.prepare = clk_smd_rpm_prepare,
|
||||
.unprepare = clk_smd_rpm_unprepare,
|
||||
.round_rate = clk_smd_rpm_round_rate,
|
||||
.recalc_rate = clk_smd_rpm_recalc_rate,
|
||||
};
|
||||
|
||||
/* msm8916 */
|
||||
DEFINE_CLK_SMD_RPM(msm8916, pcnoc_clk, pcnoc_a_clk, QCOM_SMD_RPM_BUS_CLK, 0);
|
||||
DEFINE_CLK_SMD_RPM(msm8916, snoc_clk, snoc_a_clk, QCOM_SMD_RPM_BUS_CLK, 1);
|
||||
DEFINE_CLK_SMD_RPM(msm8916, bimc_clk, bimc_a_clk, QCOM_SMD_RPM_MEM_CLK, 0);
|
||||
DEFINE_CLK_SMD_RPM_QDSS(msm8916, qdss_clk, qdss_a_clk, QCOM_SMD_RPM_MISC_CLK, 1);
|
||||
DEFINE_CLK_SMD_RPM_XO_BUFFER(msm8916, bb_clk1, bb_clk1_a, 1);
|
||||
DEFINE_CLK_SMD_RPM_XO_BUFFER(msm8916, bb_clk2, bb_clk2_a, 2);
|
||||
DEFINE_CLK_SMD_RPM_XO_BUFFER(msm8916, rf_clk1, rf_clk1_a, 4);
|
||||
DEFINE_CLK_SMD_RPM_XO_BUFFER(msm8916, rf_clk2, rf_clk2_a, 5);
|
||||
DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(msm8916, bb_clk1_pin, bb_clk1_a_pin, 1);
|
||||
DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(msm8916, bb_clk2_pin, bb_clk2_a_pin, 2);
|
||||
DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(msm8916, rf_clk1_pin, rf_clk1_a_pin, 4);
|
||||
DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(msm8916, rf_clk2_pin, rf_clk2_a_pin, 5);
|
||||
|
||||
static struct clk_smd_rpm *msm8916_clks[] = {
|
||||
[RPM_SMD_PCNOC_CLK] = &msm8916_pcnoc_clk,
|
||||
[RPM_SMD_PCNOC_A_CLK] = &msm8916_pcnoc_a_clk,
|
||||
[RPM_SMD_SNOC_CLK] = &msm8916_snoc_clk,
|
||||
[RPM_SMD_SNOC_A_CLK] = &msm8916_snoc_a_clk,
|
||||
[RPM_SMD_BIMC_CLK] = &msm8916_bimc_clk,
|
||||
[RPM_SMD_BIMC_A_CLK] = &msm8916_bimc_a_clk,
|
||||
[RPM_SMD_QDSS_CLK] = &msm8916_qdss_clk,
|
||||
[RPM_SMD_QDSS_A_CLK] = &msm8916_qdss_a_clk,
|
||||
[RPM_SMD_BB_CLK1] = &msm8916_bb_clk1,
|
||||
[RPM_SMD_BB_CLK1_A] = &msm8916_bb_clk1_a,
|
||||
[RPM_SMD_BB_CLK2] = &msm8916_bb_clk2,
|
||||
[RPM_SMD_BB_CLK2_A] = &msm8916_bb_clk2_a,
|
||||
[RPM_SMD_RF_CLK1] = &msm8916_rf_clk1,
|
||||
[RPM_SMD_RF_CLK1_A] = &msm8916_rf_clk1_a,
|
||||
[RPM_SMD_RF_CLK2] = &msm8916_rf_clk2,
|
||||
[RPM_SMD_RF_CLK2_A] = &msm8916_rf_clk2_a,
|
||||
[RPM_SMD_BB_CLK1_PIN] = &msm8916_bb_clk1_pin,
|
||||
[RPM_SMD_BB_CLK1_A_PIN] = &msm8916_bb_clk1_a_pin,
|
||||
[RPM_SMD_BB_CLK2_PIN] = &msm8916_bb_clk2_pin,
|
||||
[RPM_SMD_BB_CLK2_A_PIN] = &msm8916_bb_clk2_a_pin,
|
||||
[RPM_SMD_RF_CLK1_PIN] = &msm8916_rf_clk1_pin,
|
||||
[RPM_SMD_RF_CLK1_A_PIN] = &msm8916_rf_clk1_a_pin,
|
||||
[RPM_SMD_RF_CLK2_PIN] = &msm8916_rf_clk2_pin,
|
||||
[RPM_SMD_RF_CLK2_A_PIN] = &msm8916_rf_clk2_a_pin,
|
||||
};
|
||||
|
||||
static const struct rpm_smd_clk_desc rpm_clk_msm8916 = {
|
||||
.clks = msm8916_clks,
|
||||
.num_clks = ARRAY_SIZE(msm8916_clks),
|
||||
};
|
||||
|
||||
static const struct of_device_id rpm_smd_clk_match_table[] = {
|
||||
{ .compatible = "qcom,rpmcc-msm8916", .data = &rpm_clk_msm8916 },
|
||||
{ }
|
||||
};
|
||||
MODULE_DEVICE_TABLE(of, rpm_smd_clk_match_table);
|
||||
|
||||
static int rpm_smd_clk_probe(struct platform_device *pdev)
|
||||
{
|
||||
struct clk_hw **hws;
|
||||
struct rpm_cc *rcc;
|
||||
struct clk_hw_onecell_data *data;
|
||||
int ret;
|
||||
size_t num_clks, i;
|
||||
struct qcom_smd_rpm *rpm;
|
||||
struct clk_smd_rpm **rpm_smd_clks;
|
||||
const struct rpm_smd_clk_desc *desc;
|
||||
|
||||
rpm = dev_get_drvdata(pdev->dev.parent);
|
||||
if (!rpm) {
|
||||
dev_err(&pdev->dev, "Unable to retrieve handle to RPM\n");
|
||||
return -ENODEV;
|
||||
}
|
||||
|
||||
desc = of_device_get_match_data(&pdev->dev);
|
||||
if (!desc)
|
||||
return -EINVAL;
|
||||
|
||||
rpm_smd_clks = desc->clks;
|
||||
num_clks = desc->num_clks;
|
||||
|
||||
rcc = devm_kzalloc(&pdev->dev, sizeof(*rcc) + sizeof(*hws) * num_clks,
|
||||
GFP_KERNEL);
|
||||
if (!rcc)
|
||||
return -ENOMEM;
|
||||
|
||||
hws = rcc->hws;
|
||||
data = &rcc->data;
|
||||
data->num = num_clks;
|
||||
|
||||
for (i = 0; i < num_clks; i++) {
|
||||
if (!rpm_smd_clks[i])
|
||||
continue;
|
||||
|
||||
rpm_smd_clks[i]->rpm = rpm;
|
||||
|
||||
ret = clk_smd_rpm_handoff(rpm_smd_clks[i]);
|
||||
if (ret)
|
||||
goto err;
|
||||
}
|
||||
|
||||
ret = clk_smd_rpm_enable_scaling(rpm);
|
||||
if (ret)
|
||||
goto err;
|
||||
|
||||
for (i = 0; i < num_clks; i++) {
|
||||
if (!rpm_smd_clks[i]) {
|
||||
data->hws[i] = ERR_PTR(-ENOENT);
|
||||
continue;
|
||||
}
|
||||
|
||||
ret = devm_clk_hw_register(&pdev->dev, &rpm_smd_clks[i]->hw);
|
||||
if (ret)
|
||||
goto err;
|
||||
}
|
||||
|
||||
ret = of_clk_add_hw_provider(pdev->dev.of_node, of_clk_hw_onecell_get,
|
||||
data);
|
||||
if (ret)
|
||||
goto err;
|
||||
|
||||
return 0;
|
||||
err:
|
||||
dev_err(&pdev->dev, "Error registering SMD clock driver (%d)\n", ret);
|
||||
return ret;
|
||||
}
|
||||
|
||||
static int rpm_smd_clk_remove(struct platform_device *pdev)
|
||||
{
|
||||
of_clk_del_provider(pdev->dev.of_node);
|
||||
return 0;
|
||||
}
|
||||
|
||||
static struct platform_driver rpm_smd_clk_driver = {
|
||||
.driver = {
|
||||
.name = "qcom-clk-smd-rpm",
|
||||
.of_match_table = rpm_smd_clk_match_table,
|
||||
},
|
||||
.probe = rpm_smd_clk_probe,
|
||||
.remove = rpm_smd_clk_remove,
|
||||
};
|
||||
|
||||
static int __init rpm_smd_clk_init(void)
|
||||
{
|
||||
return platform_driver_register(&rpm_smd_clk_driver);
|
||||
}
|
||||
core_initcall(rpm_smd_clk_init);
|
||||
|
||||
static void __exit rpm_smd_clk_exit(void)
|
||||
{
|
||||
platform_driver_unregister(&rpm_smd_clk_driver);
|
||||
}
|
||||
module_exit(rpm_smd_clk_exit);
|
||||
|
||||
MODULE_DESCRIPTION("Qualcomm RPM over SMD Clock Controller Driver");
|
||||
MODULE_LICENSE("GPL v2");
|
||||
MODULE_ALIAS("platform:qcom-clk-smd-rpm");
|
||||
|
|
@ -174,15 +174,12 @@ int qcom_cc_register_board_clk(struct device *dev, const char *path,
|
|||
const char *name, unsigned long rate)
|
||||
{
|
||||
bool add_factor = true;
|
||||
struct device_node *node;
|
||||
|
||||
/* The RPM clock driver will add the factor clock if present */
|
||||
if (IS_ENABLED(CONFIG_QCOM_RPMCC)) {
|
||||
node = of_find_compatible_node(NULL, NULL, "qcom,rpmcc");
|
||||
if (of_device_is_available(node))
|
||||
add_factor = false;
|
||||
of_node_put(node);
|
||||
}
|
||||
/*
|
||||
* TODO: The RPM clock driver currently does not support the xo clock.
|
||||
* When xo is added to the RPM clock driver, we should change this
|
||||
* function to skip registration of xo factor clocks.
|
||||
*/
|
||||
|
||||
return _qcom_cc_register_board_clk(dev, path, name, rate, add_factor);
|
||||
}
|
||||
|
|
|
|||
|
|
@ -0,0 +1,69 @@
|
|||
/*
|
||||
* Copyright 2015 Linaro Limited
|
||||
*
|
||||
* This software is licensed under the terms of the GNU General Public
|
||||
* License version 2, as published by the Free Software Foundation, and
|
||||
* may be copied, distributed, and modified under those terms.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#ifndef _DT_BINDINGS_CLK_MSM_RPMCC_H
|
||||
#define _DT_BINDINGS_CLK_MSM_RPMCC_H
|
||||
|
||||
/* apq8064 */
|
||||
#define RPM_PXO_CLK 0
|
||||
#define RPM_PXO_A_CLK 1
|
||||
#define RPM_CXO_CLK 2
|
||||
#define RPM_CXO_A_CLK 3
|
||||
#define RPM_APPS_FABRIC_CLK 4
|
||||
#define RPM_APPS_FABRIC_A_CLK 5
|
||||
#define RPM_CFPB_CLK 6
|
||||
#define RPM_CFPB_A_CLK 7
|
||||
#define RPM_QDSS_CLK 8
|
||||
#define RPM_QDSS_A_CLK 9
|
||||
#define RPM_DAYTONA_FABRIC_CLK 10
|
||||
#define RPM_DAYTONA_FABRIC_A_CLK 11
|
||||
#define RPM_EBI1_CLK 12
|
||||
#define RPM_EBI1_A_CLK 13
|
||||
#define RPM_MM_FABRIC_CLK 14
|
||||
#define RPM_MM_FABRIC_A_CLK 15
|
||||
#define RPM_MMFPB_CLK 16
|
||||
#define RPM_MMFPB_A_CLK 17
|
||||
#define RPM_SYS_FABRIC_CLK 18
|
||||
#define RPM_SYS_FABRIC_A_CLK 19
|
||||
#define RPM_SFPB_CLK 20
|
||||
#define RPM_SFPB_A_CLK 21
|
||||
|
||||
/* msm8916 */
|
||||
#define RPM_SMD_XO_CLK_SRC 0
|
||||
#define RPM_SMD_XO_A_CLK_SRC 1
|
||||
#define RPM_SMD_PCNOC_CLK 2
|
||||
#define RPM_SMD_PCNOC_A_CLK 3
|
||||
#define RPM_SMD_SNOC_CLK 4
|
||||
#define RPM_SMD_SNOC_A_CLK 5
|
||||
#define RPM_SMD_BIMC_CLK 6
|
||||
#define RPM_SMD_BIMC_A_CLK 7
|
||||
#define RPM_SMD_QDSS_CLK 8
|
||||
#define RPM_SMD_QDSS_A_CLK 9
|
||||
#define RPM_SMD_BB_CLK1 10
|
||||
#define RPM_SMD_BB_CLK1_A 11
|
||||
#define RPM_SMD_BB_CLK2 12
|
||||
#define RPM_SMD_BB_CLK2_A 13
|
||||
#define RPM_SMD_RF_CLK1 14
|
||||
#define RPM_SMD_RF_CLK1_A 15
|
||||
#define RPM_SMD_RF_CLK2 16
|
||||
#define RPM_SMD_RF_CLK2_A 17
|
||||
#define RPM_SMD_BB_CLK1_PIN 18
|
||||
#define RPM_SMD_BB_CLK1_A_PIN 19
|
||||
#define RPM_SMD_BB_CLK2_PIN 20
|
||||
#define RPM_SMD_BB_CLK2_A_PIN 21
|
||||
#define RPM_SMD_RF_CLK1_PIN 22
|
||||
#define RPM_SMD_RF_CLK1_A_PIN 23
|
||||
#define RPM_SMD_RF_CLK2_PIN 24
|
||||
#define RPM_SMD_RF_CLK2_A_PIN 25
|
||||
|
||||
#endif
|
||||
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