IB/mlx5: Disable atomic operations
Currently Atomic operations don't work properly. Disable them for the time being. Signed-off-by: Eli Cohen <eli@mellanox.com> Signed-off-by: Roland Dreier <roland@purestorage.com>
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Родитель
2f6daec14d
Коммит
81bea28ffd
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@ -301,9 +301,8 @@ static int mlx5_ib_query_device(struct ib_device *ibdev,
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props->max_srq_sge = max_rq_sg - 1;
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props->max_srq_sge = max_rq_sg - 1;
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props->max_fast_reg_page_list_len = (unsigned int)-1;
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props->max_fast_reg_page_list_len = (unsigned int)-1;
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props->local_ca_ack_delay = dev->mdev.caps.local_ca_ack_delay;
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props->local_ca_ack_delay = dev->mdev.caps.local_ca_ack_delay;
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props->atomic_cap = dev->mdev.caps.flags & MLX5_DEV_CAP_FLAG_ATOMIC ?
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props->atomic_cap = IB_ATOMIC_NONE;
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IB_ATOMIC_HCA : IB_ATOMIC_NONE;
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props->masked_atomic_cap = IB_ATOMIC_NONE;
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props->masked_atomic_cap = IB_ATOMIC_HCA;
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props->max_pkeys = be16_to_cpup((__be16 *)(out_mad->data + 28));
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props->max_pkeys = be16_to_cpup((__be16 *)(out_mad->data + 28));
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props->max_mcast_grp = 1 << dev->mdev.caps.log_max_mcg;
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props->max_mcast_grp = 1 << dev->mdev.caps.log_max_mcg;
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props->max_mcast_qp_attach = dev->mdev.caps.max_qp_mcg;
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props->max_mcast_qp_attach = dev->mdev.caps.max_qp_mcg;
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@ -1661,29 +1661,6 @@ static __always_inline void set_raddr_seg(struct mlx5_wqe_raddr_seg *rseg,
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rseg->reserved = 0;
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rseg->reserved = 0;
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}
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}
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static void set_atomic_seg(struct mlx5_wqe_atomic_seg *aseg, struct ib_send_wr *wr)
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{
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if (wr->opcode == IB_WR_ATOMIC_CMP_AND_SWP) {
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aseg->swap_add = cpu_to_be64(wr->wr.atomic.swap);
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aseg->compare = cpu_to_be64(wr->wr.atomic.compare_add);
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} else if (wr->opcode == IB_WR_MASKED_ATOMIC_FETCH_AND_ADD) {
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aseg->swap_add = cpu_to_be64(wr->wr.atomic.compare_add);
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aseg->compare = cpu_to_be64(wr->wr.atomic.compare_add_mask);
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} else {
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aseg->swap_add = cpu_to_be64(wr->wr.atomic.compare_add);
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aseg->compare = 0;
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}
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}
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static void set_masked_atomic_seg(struct mlx5_wqe_masked_atomic_seg *aseg,
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struct ib_send_wr *wr)
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{
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aseg->swap_add = cpu_to_be64(wr->wr.atomic.swap);
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aseg->swap_add_mask = cpu_to_be64(wr->wr.atomic.swap_mask);
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aseg->compare = cpu_to_be64(wr->wr.atomic.compare_add);
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aseg->compare_mask = cpu_to_be64(wr->wr.atomic.compare_add_mask);
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}
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static void set_datagram_seg(struct mlx5_wqe_datagram_seg *dseg,
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static void set_datagram_seg(struct mlx5_wqe_datagram_seg *dseg,
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struct ib_send_wr *wr)
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struct ib_send_wr *wr)
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{
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{
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@ -2073,28 +2050,11 @@ int mlx5_ib_post_send(struct ib_qp *ibqp, struct ib_send_wr *wr,
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case IB_WR_ATOMIC_CMP_AND_SWP:
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case IB_WR_ATOMIC_CMP_AND_SWP:
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case IB_WR_ATOMIC_FETCH_AND_ADD:
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case IB_WR_ATOMIC_FETCH_AND_ADD:
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set_raddr_seg(seg, wr->wr.atomic.remote_addr,
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wr->wr.atomic.rkey);
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seg += sizeof(struct mlx5_wqe_raddr_seg);
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set_atomic_seg(seg, wr);
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seg += sizeof(struct mlx5_wqe_atomic_seg);
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size += (sizeof(struct mlx5_wqe_raddr_seg) +
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sizeof(struct mlx5_wqe_atomic_seg)) / 16;
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break;
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case IB_WR_MASKED_ATOMIC_CMP_AND_SWP:
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case IB_WR_MASKED_ATOMIC_CMP_AND_SWP:
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set_raddr_seg(seg, wr->wr.atomic.remote_addr,
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mlx5_ib_warn(dev, "Atomic operations are not supported yet\n");
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wr->wr.atomic.rkey);
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err = -ENOSYS;
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seg += sizeof(struct mlx5_wqe_raddr_seg);
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*bad_wr = wr;
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goto out;
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set_masked_atomic_seg(seg, wr);
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seg += sizeof(struct mlx5_wqe_masked_atomic_seg);
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size += (sizeof(struct mlx5_wqe_raddr_seg) +
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sizeof(struct mlx5_wqe_masked_atomic_seg)) / 16;
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break;
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case IB_WR_LOCAL_INV:
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case IB_WR_LOCAL_INV:
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next_fence = MLX5_FENCE_MODE_INITIATOR_SMALL;
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next_fence = MLX5_FENCE_MODE_INITIATOR_SMALL;
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