CLK: TI: clk-54xx: Set the rate for dpll_abe_m2x2_ck
In order to get correct clock dividers for AESS/ABE we need to set the dpll_abe_m2x2_ck rate to be double of dpll_abe_ck. Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com> Signed-off-by: Tero Kristo <t-kristo@ti.com>
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@ -240,6 +240,12 @@ int __init omap5xxx_dt_clk_init(void)
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if (rc)
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pr_err("%s: failed to configure ABE DPLL!\n", __func__);
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abe_dpll = clk_get_sys(NULL, "dpll_abe_m2x2_ck");
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if (!rc)
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rc = clk_set_rate(abe_dpll, OMAP5_DPLL_ABE_DEFFREQ * 2);
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if (rc)
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pr_err("%s: failed to configure ABE m2x2 DPLL!\n", __func__);
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usb_dpll = clk_get_sys(NULL, "dpll_usb_ck");
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rc = clk_set_rate(usb_dpll, OMAP5_DPLL_USB_DEFFREQ);
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if (rc)
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