ata: Add APM X-Gene SoC AHCI SATA host controller driver
This patch adds support for the APM X-Gene SoC AHCI SATA host controller driver. It requires the corresponding APM X-Gene SoC PHY driver. This initial version only supports Gen3 speed. Signed-off-by: Loc Ho <lho@apm.com> Signed-off-by: Tuan Phan <tphan@apm.com> Signed-off-by: Suman Tripathi <stripathi@apm.com> Reviewed-by: Bartlomiej Zolnierkiewicz <b.zolnierkie@samsung.com> Signed-off-by: Tejun Heo <tj@kernel.org>
This commit is contained in:
Loc Ho
Tejun Heo
Родитель
1ccaead5f5
Коммит
81d01bfa51
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@ -124,6 +124,13 @@ config AHCI_SUNXI
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If unsure, say N.
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config AHCI_XGENE
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tristate "APM X-Gene 6.0Gbps AHCI SATA host controller support"
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depends on SATA_AHCI_PLATFORM && (ARM64 || COMPILE_TEST)
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select PHY_XGENE
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help
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This option enables support for APM X-Gene SoC SATA host controller.
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config SATA_FSL
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tristate "Freescale 3.0Gbps SATA support"
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depends on FSL_SOC
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@ -13,6 +13,7 @@ obj-$(CONFIG_SATA_HIGHBANK) += sata_highbank.o libahci.o
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obj-$(CONFIG_AHCI_IMX) += ahci_imx.o
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obj-$(CONFIG_AHCI_SUNXI) += ahci_sunxi.o
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obj-$(CONFIG_AHCI_ST) += ahci_st.o
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obj-$(CONFIG_AHCI_XGENE) += ahci_xgene.o
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# SFF w/ custom DMA
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obj-$(CONFIG_PDC_ADMA) += pdc_adma.o
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@ -0,0 +1,486 @@
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/*
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* AppliedMicro X-Gene SoC SATA Host Controller Driver
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*
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* Copyright (c) 2014, Applied Micro Circuits Corporation
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* Author: Loc Ho <lho@apm.com>
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* Tuan Phan <tphan@apm.com>
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* Suman Tripathi <stripathi@apm.com>
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*
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* NOTE: PM support is not currently available.
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*
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*/
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#include <linux/module.h>
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#include <linux/platform_device.h>
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#include <linux/ahci_platform.h>
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#include <linux/of_address.h>
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#include <linux/of_irq.h>
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#include <linux/phy/phy.h>
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#include "ahci.h"
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/* Max # of disk per a controller */
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#define MAX_AHCI_CHN_PERCTR 2
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/* MUX CSR */
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#define SATA_ENET_CONFIG_REG 0x00000000
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#define CFG_SATA_ENET_SELECT_MASK 0x00000001
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/* SATA core host controller CSR */
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#define SLVRDERRATTRIBUTES 0x00000000
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#define SLVWRERRATTRIBUTES 0x00000004
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#define MSTRDERRATTRIBUTES 0x00000008
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#define MSTWRERRATTRIBUTES 0x0000000c
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#define BUSCTLREG 0x00000014
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#define IOFMSTRWAUX 0x00000018
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#define INTSTATUSMASK 0x0000002c
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#define ERRINTSTATUS 0x00000030
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#define ERRINTSTATUSMASK 0x00000034
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/* SATA host AHCI CSR */
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#define PORTCFG 0x000000a4
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#define PORTADDR_SET(dst, src) \
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(((dst) & ~0x0000003f) | (((u32)(src)) & 0x0000003f))
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#define PORTPHY1CFG 0x000000a8
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#define PORTPHY1CFG_FRCPHYRDY_SET(dst, src) \
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(((dst) & ~0x00100000) | (((u32)(src) << 0x14) & 0x00100000))
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#define PORTPHY2CFG 0x000000ac
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#define PORTPHY3CFG 0x000000b0
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#define PORTPHY4CFG 0x000000b4
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#define PORTPHY5CFG 0x000000b8
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#define SCTL0 0x0000012C
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#define PORTPHY5CFG_RTCHG_SET(dst, src) \
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(((dst) & ~0xfff00000) | (((u32)(src) << 0x14) & 0xfff00000))
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#define PORTAXICFG_EN_CONTEXT_SET(dst, src) \
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(((dst) & ~0x01000000) | (((u32)(src) << 0x18) & 0x01000000))
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#define PORTAXICFG 0x000000bc
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#define PORTAXICFG_OUTTRANS_SET(dst, src) \
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(((dst) & ~0x00f00000) | (((u32)(src) << 0x14) & 0x00f00000))
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/* SATA host controller AXI CSR */
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#define INT_SLV_TMOMASK 0x00000010
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/* SATA diagnostic CSR */
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#define CFG_MEM_RAM_SHUTDOWN 0x00000070
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#define BLOCK_MEM_RDY 0x00000074
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struct xgene_ahci_context {
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struct ahci_host_priv *hpriv;
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struct device *dev;
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void __iomem *csr_core; /* Core CSR address of IP */
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void __iomem *csr_diag; /* Diag CSR address of IP */
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void __iomem *csr_axi; /* AXI CSR address of IP */
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void __iomem *csr_mux; /* MUX CSR address of IP */
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};
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static int xgene_ahci_init_memram(struct xgene_ahci_context *ctx)
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{
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dev_dbg(ctx->dev, "Release memory from shutdown\n");
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writel(0x0, ctx->csr_diag + CFG_MEM_RAM_SHUTDOWN);
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readl(ctx->csr_diag + CFG_MEM_RAM_SHUTDOWN); /* Force a barrier */
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msleep(1); /* reset may take up to 1ms */
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if (readl(ctx->csr_diag + BLOCK_MEM_RDY) != 0xFFFFFFFF) {
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dev_err(ctx->dev, "failed to release memory from shutdown\n");
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return -ENODEV;
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}
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return 0;
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}
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/**
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* xgene_ahci_read_id - Read ID data from the specified device
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* @dev: device
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* @tf: proposed taskfile
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* @id: data buffer
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*
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* This custom read ID function is required due to the fact that the HW
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* does not support DEVSLP and the controller state machine may get stuck
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* after processing the ID query command.
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*/
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static unsigned int xgene_ahci_read_id(struct ata_device *dev,
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struct ata_taskfile *tf, u16 *id)
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{
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u32 err_mask;
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void __iomem *port_mmio = ahci_port_base(dev->link->ap);
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err_mask = ata_do_dev_read_id(dev, tf, id);
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if (err_mask)
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return err_mask;
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/*
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* Mask reserved area. Word78 spec of Link Power Management
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* bit15-8: reserved
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* bit7: NCQ autosence
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* bit6: Software settings preservation supported
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* bit5: reserved
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* bit4: In-order sata delivery supported
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* bit3: DIPM requests supported
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* bit2: DMA Setup FIS Auto-Activate optimization supported
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* bit1: DMA Setup FIX non-Zero buffer offsets supported
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* bit0: Reserved
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*
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* Clear reserved bit 8 (DEVSLP bit) as we don't support DEVSLP
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*/
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id[ATA_ID_FEATURE_SUPP] &= ~(1 << 8);
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/*
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* Due to HW errata, restart the port if no other command active.
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* Otherwise the controller may get stuck.
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*/
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if (!readl(port_mmio + PORT_CMD_ISSUE)) {
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writel(PORT_CMD_FIS_RX, port_mmio + PORT_CMD);
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readl(port_mmio + PORT_CMD); /* Force a barrier */
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writel(PORT_CMD_FIS_RX | PORT_CMD_START, port_mmio + PORT_CMD);
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readl(port_mmio + PORT_CMD); /* Force a barrier */
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}
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return 0;
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}
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static void xgene_ahci_set_phy_cfg(struct xgene_ahci_context *ctx, int channel)
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{
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void __iomem *mmio = ctx->hpriv->mmio;
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u32 val;
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dev_dbg(ctx->dev, "port configure mmio 0x%p channel %d\n",
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mmio, channel);
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val = readl(mmio + PORTCFG);
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val = PORTADDR_SET(val, channel == 0 ? 2 : 3);
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writel(val, mmio + PORTCFG);
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readl(mmio + PORTCFG); /* Force a barrier */
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/* Disable fix rate */
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writel(0x0001fffe, mmio + PORTPHY1CFG);
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readl(mmio + PORTPHY1CFG); /* Force a barrier */
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writel(0x5018461c, mmio + PORTPHY2CFG);
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readl(mmio + PORTPHY2CFG); /* Force a barrier */
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writel(0x1c081907, mmio + PORTPHY3CFG);
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readl(mmio + PORTPHY3CFG); /* Force a barrier */
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writel(0x1c080815, mmio + PORTPHY4CFG);
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readl(mmio + PORTPHY4CFG); /* Force a barrier */
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/* Set window negotiation */
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val = readl(mmio + PORTPHY5CFG);
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val = PORTPHY5CFG_RTCHG_SET(val, 0x300);
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writel(val, mmio + PORTPHY5CFG);
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readl(mmio + PORTPHY5CFG); /* Force a barrier */
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val = readl(mmio + PORTAXICFG);
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val = PORTAXICFG_EN_CONTEXT_SET(val, 0x1); /* Enable context mgmt */
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val = PORTAXICFG_OUTTRANS_SET(val, 0xe); /* Set outstanding */
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writel(val, mmio + PORTAXICFG);
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readl(mmio + PORTAXICFG); /* Force a barrier */
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}
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/**
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* xgene_ahci_do_hardreset - Issue the actual COMRESET
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* @link: link to reset
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* @deadline: deadline jiffies for the operation
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* @online: Return value to indicate if device online
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*
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* Due to the limitation of the hardware PHY, a difference set of setting is
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* required for each supported disk speed - Gen3 (6.0Gbps), Gen2 (3.0Gbps),
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* and Gen1 (1.5Gbps). Otherwise during long IO stress test, the PHY will
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* report disparity error and etc. In addition, during COMRESET, there can
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* be error reported in the register PORT_SCR_ERR. For SERR_DISPARITY and
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* SERR_10B_8B_ERR, the PHY receiver line must be reseted. The following
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* algorithm is followed to proper configure the hardware PHY during COMRESET:
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*
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* Alg Part 1:
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* 1. Start the PHY at Gen3 speed (default setting)
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* 2. Issue the COMRESET
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* 3. If no link, go to Alg Part 3
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* 4. If link up, determine if the negotiated speed matches the PHY
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* configured speed
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* 5. If they matched, go to Alg Part 2
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* 6. If they do not matched and first time, configure the PHY for the linked
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* up disk speed and repeat step 2
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* 7. Go to Alg Part 2
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*
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* Alg Part 2:
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* 1. On link up, if there are any SERR_DISPARITY and SERR_10B_8B_ERR error
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* reported in the register PORT_SCR_ERR, then reset the PHY receiver line
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* 2. Go to Alg Part 3
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*
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* Alg Part 3:
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* 1. Clear any pending from register PORT_SCR_ERR.
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*
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* NOTE: For the initial version, we will NOT support Gen1/Gen2. In addition
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* and until the underlying PHY supports an method to reset the receiver
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* line, on detection of SERR_DISPARITY or SERR_10B_8B_ERR errors,
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* an warning message will be printed.
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*/
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static int xgene_ahci_do_hardreset(struct ata_link *link,
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unsigned long deadline, bool *online)
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{
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const unsigned long *timing = sata_ehc_deb_timing(&link->eh_context);
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struct ata_port *ap = link->ap;
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struct ahci_host_priv *hpriv = ap->host->private_data;
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struct xgene_ahci_context *ctx = hpriv->plat_data;
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struct ahci_port_priv *pp = ap->private_data;
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u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG;
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void __iomem *port_mmio = ahci_port_base(ap);
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struct ata_taskfile tf;
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int rc;
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u32 val;
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/* clear D2H reception area to properly wait for D2H FIS */
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ata_tf_init(link->device, &tf);
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tf.command = ATA_BUSY;
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ata_tf_to_fis(&tf, 0, 0, d2h_fis);
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rc = sata_link_hardreset(link, timing, deadline, online,
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ahci_check_ready);
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val = readl(port_mmio + PORT_SCR_ERR);
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if (val & (SERR_DISPARITY | SERR_10B_8B_ERR))
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dev_warn(ctx->dev, "link has error\n");
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/* clear all errors if any pending */
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val = readl(port_mmio + PORT_SCR_ERR);
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writel(val, port_mmio + PORT_SCR_ERR);
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return rc;
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}
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static int xgene_ahci_hardreset(struct ata_link *link, unsigned int *class,
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unsigned long deadline)
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{
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struct ata_port *ap = link->ap;
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struct ahci_host_priv *hpriv = ap->host->private_data;
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void __iomem *port_mmio = ahci_port_base(ap);
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bool online;
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int rc;
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u32 portcmd_saved;
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u32 portclb_saved;
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u32 portclbhi_saved;
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u32 portrxfis_saved;
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u32 portrxfishi_saved;
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/* As hardreset resets these CSR, save it to restore later */
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portcmd_saved = readl(port_mmio + PORT_CMD);
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portclb_saved = readl(port_mmio + PORT_LST_ADDR);
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portclbhi_saved = readl(port_mmio + PORT_LST_ADDR_HI);
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portrxfis_saved = readl(port_mmio + PORT_FIS_ADDR);
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portrxfishi_saved = readl(port_mmio + PORT_FIS_ADDR_HI);
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ahci_stop_engine(ap);
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rc = xgene_ahci_do_hardreset(link, deadline, &online);
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/* As controller hardreset clears them, restore them */
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writel(portcmd_saved, port_mmio + PORT_CMD);
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writel(portclb_saved, port_mmio + PORT_LST_ADDR);
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writel(portclbhi_saved, port_mmio + PORT_LST_ADDR_HI);
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writel(portrxfis_saved, port_mmio + PORT_FIS_ADDR);
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writel(portrxfishi_saved, port_mmio + PORT_FIS_ADDR_HI);
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hpriv->start_engine(ap);
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if (online)
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*class = ahci_dev_classify(ap);
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return rc;
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}
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static void xgene_ahci_host_stop(struct ata_host *host)
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{
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struct ahci_host_priv *hpriv = host->private_data;
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ahci_platform_disable_resources(hpriv);
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}
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static struct ata_port_operations xgene_ahci_ops = {
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.inherits = &ahci_ops,
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.host_stop = xgene_ahci_host_stop,
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.hardreset = xgene_ahci_hardreset,
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.read_id = xgene_ahci_read_id,
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};
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static const struct ata_port_info xgene_ahci_port_info = {
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AHCI_HFLAGS(AHCI_HFLAG_NO_PMP | AHCI_HFLAG_YES_NCQ),
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.flags = AHCI_FLAG_COMMON | ATA_FLAG_NCQ,
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.pio_mask = ATA_PIO4,
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.udma_mask = ATA_UDMA6,
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.port_ops = &xgene_ahci_ops,
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};
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static int xgene_ahci_hw_init(struct ahci_host_priv *hpriv)
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{
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struct xgene_ahci_context *ctx = hpriv->plat_data;
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int i;
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int rc;
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u32 val;
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/* Remove IP RAM out of shutdown */
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rc = xgene_ahci_init_memram(ctx);
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if (rc)
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return rc;
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for (i = 0; i < MAX_AHCI_CHN_PERCTR; i++)
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xgene_ahci_set_phy_cfg(ctx, i);
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/* AXI disable Mask */
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writel(0xffffffff, hpriv->mmio + HOST_IRQ_STAT);
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readl(hpriv->mmio + HOST_IRQ_STAT); /* Force a barrier */
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writel(0, ctx->csr_core + INTSTATUSMASK);
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readl(ctx->csr_core + INTSTATUSMASK); /* Force a barrier */
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dev_dbg(ctx->dev, "top level interrupt mask 0x%X value 0x%08X\n",
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INTSTATUSMASK, val);
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writel(0x0, ctx->csr_core + ERRINTSTATUSMASK);
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readl(ctx->csr_core + ERRINTSTATUSMASK); /* Force a barrier */
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writel(0x0, ctx->csr_axi + INT_SLV_TMOMASK);
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readl(ctx->csr_axi + INT_SLV_TMOMASK);
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/* Enable AXI Interrupt */
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writel(0xffffffff, ctx->csr_core + SLVRDERRATTRIBUTES);
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writel(0xffffffff, ctx->csr_core + SLVWRERRATTRIBUTES);
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writel(0xffffffff, ctx->csr_core + MSTRDERRATTRIBUTES);
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writel(0xffffffff, ctx->csr_core + MSTWRERRATTRIBUTES);
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/* Enable coherency */
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val = readl(ctx->csr_core + BUSCTLREG);
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val &= ~0x00000002; /* Enable write coherency */
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val &= ~0x00000001; /* Enable read coherency */
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writel(val, ctx->csr_core + BUSCTLREG);
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val = readl(ctx->csr_core + IOFMSTRWAUX);
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val |= (1 << 3); /* Enable read coherency */
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val |= (1 << 9); /* Enable write coherency */
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writel(val, ctx->csr_core + IOFMSTRWAUX);
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val = readl(ctx->csr_core + IOFMSTRWAUX);
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dev_dbg(ctx->dev, "coherency 0x%X value 0x%08X\n",
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IOFMSTRWAUX, val);
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return rc;
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}
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static int xgene_ahci_mux_select(struct xgene_ahci_context *ctx)
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{
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u32 val;
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/* Check for optional MUX resource */
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if (IS_ERR(ctx->csr_mux))
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return 0;
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val = readl(ctx->csr_mux + SATA_ENET_CONFIG_REG);
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val &= ~CFG_SATA_ENET_SELECT_MASK;
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writel(val, ctx->csr_mux + SATA_ENET_CONFIG_REG);
|
||||
val = readl(ctx->csr_mux + SATA_ENET_CONFIG_REG);
|
||||
return val & CFG_SATA_ENET_SELECT_MASK ? -1 : 0;
|
||||
}
|
||||
|
||||
static int xgene_ahci_probe(struct platform_device *pdev)
|
||||
{
|
||||
struct device *dev = &pdev->dev;
|
||||
struct ahci_host_priv *hpriv;
|
||||
struct xgene_ahci_context *ctx;
|
||||
struct resource *res;
|
||||
int rc;
|
||||
|
||||
hpriv = ahci_platform_get_resources(pdev);
|
||||
if (IS_ERR(hpriv))
|
||||
return PTR_ERR(hpriv);
|
||||
|
||||
ctx = devm_kzalloc(dev, sizeof(*ctx), GFP_KERNEL);
|
||||
if (!ctx)
|
||||
return -ENOMEM;
|
||||
|
||||
hpriv->plat_data = ctx;
|
||||
ctx->hpriv = hpriv;
|
||||
ctx->dev = dev;
|
||||
|
||||
/* Retrieve the IP core resource */
|
||||
res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
|
||||
ctx->csr_core = devm_ioremap_resource(dev, res);
|
||||
if (IS_ERR(ctx->csr_core))
|
||||
return PTR_ERR(ctx->csr_core);
|
||||
|
||||
/* Retrieve the IP diagnostic resource */
|
||||
res = platform_get_resource(pdev, IORESOURCE_MEM, 2);
|
||||
ctx->csr_diag = devm_ioremap_resource(dev, res);
|
||||
if (IS_ERR(ctx->csr_diag))
|
||||
return PTR_ERR(ctx->csr_diag);
|
||||
|
||||
/* Retrieve the IP AXI resource */
|
||||
res = platform_get_resource(pdev, IORESOURCE_MEM, 3);
|
||||
ctx->csr_axi = devm_ioremap_resource(dev, res);
|
||||
if (IS_ERR(ctx->csr_axi))
|
||||
return PTR_ERR(ctx->csr_axi);
|
||||
|
||||
/* Retrieve the optional IP mux resource */
|
||||
res = platform_get_resource(pdev, IORESOURCE_MEM, 4);
|
||||
ctx->csr_mux = devm_ioremap_resource(dev, res);
|
||||
|
||||
dev_dbg(dev, "VAddr 0x%p Mmio VAddr 0x%p\n", ctx->csr_core,
|
||||
hpriv->mmio);
|
||||
|
||||
/* Select ATA */
|
||||
if ((rc = xgene_ahci_mux_select(ctx))) {
|
||||
dev_err(dev, "SATA mux selection failed error %d\n", rc);
|
||||
return -ENODEV;
|
||||
}
|
||||
|
||||
/* Due to errata, HW requires full toggle transition */
|
||||
rc = ahci_platform_enable_clks(hpriv);
|
||||
if (rc)
|
||||
goto disable_resources;
|
||||
ahci_platform_disable_clks(hpriv);
|
||||
|
||||
rc = ahci_platform_enable_resources(hpriv);
|
||||
if (rc)
|
||||
goto disable_resources;
|
||||
|
||||
/* Configure the host controller */
|
||||
xgene_ahci_hw_init(hpriv);
|
||||
|
||||
/*
|
||||
* Setup DMA mask. This is preliminary until the DMA range is sorted
|
||||
* out.
|
||||
*/
|
||||
rc = dma_set_mask_and_coherent(dev, DMA_BIT_MASK(64));
|
||||
if (rc) {
|
||||
dev_err(dev, "Unable to set dma mask\n");
|
||||
goto disable_resources;
|
||||
}
|
||||
|
||||
rc = ahci_platform_init_host(pdev, hpriv, &xgene_ahci_port_info, 0, 0);
|
||||
if (rc)
|
||||
goto disable_resources;
|
||||
|
||||
dev_dbg(dev, "X-Gene SATA host controller initialized\n");
|
||||
return 0;
|
||||
|
||||
disable_resources:
|
||||
ahci_platform_disable_resources(hpriv);
|
||||
return rc;
|
||||
}
|
||||
|
||||
static const struct of_device_id xgene_ahci_of_match[] = {
|
||||
{.compatible = "apm,xgene-ahci"},
|
||||
{},
|
||||
};
|
||||
MODULE_DEVICE_TABLE(of, xgene_ahci_of_match);
|
||||
|
||||
static struct platform_driver xgene_ahci_driver = {
|
||||
.probe = xgene_ahci_probe,
|
||||
.remove = ata_platform_remove_one,
|
||||
.driver = {
|
||||
.name = "xgene-ahci",
|
||||
.owner = THIS_MODULE,
|
||||
.of_match_table = xgene_ahci_of_match,
|
||||
},
|
||||
};
|
||||
|
||||
module_platform_driver(xgene_ahci_driver);
|
||||
|
||||
MODULE_DESCRIPTION("APM X-Gene AHCI SATA driver");
|
||||
MODULE_AUTHOR("Loc Ho <lho@apm.com>");
|
||||
MODULE_LICENSE("GPL");
|
||||
MODULE_VERSION("0.4");
|
||||
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