intel-gtt: switch i81x to the common initialization helpers
Still a separate agp_bridge_driver because of the i81x-only dedicated vram support. Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
This commit is contained in:
Daniel Vetter
Chris Wilson
Родитель
625dd9d331
Коммит
820647b97a
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@ -39,26 +39,10 @@
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#define USE_PCI_DMA_API 0
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#endif
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static const struct aper_size_info_fixed intel_i810_sizes[] =
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{
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{64, 16384, 4},
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/* The 32M mode still requires a 64k gatt */
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{32, 8192, 4}
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};
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#define AGP_DCACHE_MEMORY 1
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#define AGP_PHYS_MEMORY 2
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#define INTEL_AGP_CACHED_MEMORY 3
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static struct gatt_mask intel_i810_masks[] =
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{
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{.mask = I810_PTE_VALID, .type = 0},
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{.mask = (I810_PTE_VALID | I810_PTE_LOCAL), .type = AGP_DCACHE_MEMORY},
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{.mask = I810_PTE_VALID, .type = 0},
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{.mask = I810_PTE_VALID | I830_PTE_SYSTEM_CACHED,
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.type = INTEL_AGP_CACHED_MEMORY}
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};
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struct intel_gtt_driver {
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unsigned int gen : 8;
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unsigned int is_g33 : 1;
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@ -94,6 +78,7 @@ static struct _intel_private {
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void __iomem *i9xx_flush_page;
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void *i8xx_flush_page;
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};
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char *i81x_gtt_table;
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struct page *i8xx_page;
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struct resource ifp_resource;
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int resource_valid;
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@ -163,86 +148,6 @@ static void intel_agp_unmap_memory(struct agp_memory *mem)
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intel_agp_free_sglist(mem);
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}
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static int intel_i810_fetch_size(void)
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{
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u32 smram_miscc;
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struct aper_size_info_fixed *values;
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pci_read_config_dword(intel_private.bridge_dev,
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I810_SMRAM_MISCC, &smram_miscc);
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values = A_SIZE_FIX(agp_bridge->driver->aperture_sizes);
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if ((smram_miscc & I810_GMS) == I810_GMS_DISABLE) {
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dev_warn(&intel_private.bridge_dev->dev, "i810 is disabled\n");
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return 0;
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}
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if ((smram_miscc & I810_GFX_MEM_WIN_SIZE) == I810_GFX_MEM_WIN_32M) {
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agp_bridge->current_size = (void *) (values + 1);
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agp_bridge->aperture_size_idx = 1;
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intel_private.base.gtt_total_entries = KB(32) / 4;
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return values[1].size;
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} else {
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agp_bridge->current_size = (void *) (values);
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agp_bridge->aperture_size_idx = 0;
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intel_private.base.gtt_total_entries = KB(64) / 4;
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return values[0].size;
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}
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return 0;
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}
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static int intel_i810_configure(void)
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{
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struct aper_size_info_fixed *current_size;
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u32 temp;
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int i;
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current_size = A_SIZE_FIX(agp_bridge->current_size);
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if (!intel_private.registers) {
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pci_read_config_dword(intel_private.pcidev, I810_MMADDR, &temp);
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temp &= 0xfff80000;
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intel_private.registers = ioremap(temp, 128 * 4096);
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if (!intel_private.registers) {
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dev_err(&intel_private.pcidev->dev,
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"can't remap memory\n");
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return -ENOMEM;
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}
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}
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intel_private.gtt = intel_private.registers + I810_PTE_BASE;
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intel_private.scratch_page_dma = agp_bridge->scratch_page & PAGE_MASK;
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if ((readl(intel_private.registers+I810_DRAM_CTL)
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& I810_DRAM_ROW_0) == I810_DRAM_ROW_0_SDRAM) {
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/* This will need to be dynamically assigned */
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dev_info(&intel_private.pcidev->dev,
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"detected 4MB dedicated video ram\n");
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intel_private.num_dcache_entries = 1024;
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}
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pci_read_config_dword(intel_private.pcidev, I810_GMADDR, &temp);
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agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
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writel(agp_bridge->gatt_bus_addr | I810_PGETBL_ENABLED, intel_private.registers+I810_PGETBL_CTL);
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readl(intel_private.registers+I810_PGETBL_CTL); /* PCI Posting. */
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if (agp_bridge->driver->needs_scratch_page) {
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for (i = 0; i < current_size->num_entries; i++) {
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writel(agp_bridge->scratch_page, intel_private.registers+I810_PTE_BASE+(i*4));
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}
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readl(intel_private.registers+I810_PTE_BASE+((i-1)*4)); /* PCI posting. */
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}
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global_cache_flush();
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return 0;
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}
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static void intel_i810_cleanup(void)
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{
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writel(0, intel_private.registers+I810_PGETBL_CTL);
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readl(intel_private.registers); /* PCI Posting. */
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iounmap(intel_private.registers);
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}
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static void intel_fake_agp_enable(struct agp_bridge_data *bridge, u32 mode)
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{
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return;
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@ -278,6 +183,46 @@ static void i8xx_destroy_pages(struct page *page)
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atomic_dec(&agp_bridge->current_memory_agp);
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}
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#define I810_GTT_ORDER 4
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static int i810_setup(void)
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{
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u32 reg_addr;
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char *gtt_table;
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/* i81x does not preallocate the gtt. It's always 64kb in size. */
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gtt_table = alloc_gatt_pages(I810_GTT_ORDER);
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if (gtt_table == NULL)
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return -ENOMEM;
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intel_private.i81x_gtt_table = gtt_table;
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pci_read_config_dword(intel_private.pcidev, I810_MMADDR, ®_addr);
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reg_addr &= 0xfff80000;
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intel_private.registers = ioremap(reg_addr, KB(64));
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if (!intel_private.registers)
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return -ENOMEM;
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writel(virt_to_phys(gtt_table) | I810_PGETBL_ENABLED,
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intel_private.registers+I810_PGETBL_CTL);
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intel_private.gtt_bus_addr = reg_addr + I810_PTE_BASE;
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if ((readl(intel_private.registers+I810_DRAM_CTL)
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& I810_DRAM_ROW_0) == I810_DRAM_ROW_0_SDRAM) {
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dev_info(&intel_private.pcidev->dev,
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"detected 4MB dedicated video ram\n");
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intel_private.num_dcache_entries = 1024;
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}
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return 0;
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}
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static void i810_cleanup(void)
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{
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writel(0, intel_private.registers+I810_PGETBL_CTL);
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free_gatt_pages(intel_private.i81x_gtt_table, I810_GTT_ORDER);
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}
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static int intel_i810_insert_entries(struct agp_memory *mem, off_t pg_start,
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int type)
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{
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@ -363,13 +308,6 @@ static void intel_i810_free_by_type(struct agp_memory *curr)
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kfree(curr);
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}
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static unsigned long intel_i810_mask_memory(struct agp_bridge_data *bridge,
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dma_addr_t addr, int type)
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{
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/* Type checking must be done elsewhere */
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return addr | bridge->driver->masks[type].mask;
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}
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static int intel_gtt_setup_scratch_page(void)
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{
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struct page *page;
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@ -414,9 +352,9 @@ static void i810_write_entry(dma_addr_t addr, unsigned int entry,
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}
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static const struct aper_size_info_fixed const intel_fake_agp_sizes[] = {
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{32, 8192, 3},
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{64, 16384, 4},
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{128, 32768, 5},
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/* The 64M mode still requires a 128k gatt */
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{64, 16384, 5},
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{256, 65536, 6},
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{512, 131072, 7},
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};
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@ -429,6 +367,9 @@ static unsigned int intel_gtt_stolen_size(void)
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static const int ddt[4] = { 0, 16, 32, 64 };
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unsigned int stolen_size = 0;
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if (INTEL_GTT_GEN == 1)
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return 0; /* no stolen mem on i81x */
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pci_read_config_word(intel_private.bridge_dev,
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I830_GMCH_CTRL, &gmch_ctrl);
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@ -677,7 +618,18 @@ static unsigned int intel_gtt_mappable_entries(void)
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{
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unsigned int aperture_size;
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if (INTEL_GTT_GEN == 2) {
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if (INTEL_GTT_GEN == 1) {
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u32 smram_miscc;
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pci_read_config_dword(intel_private.bridge_dev,
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I810_SMRAM_MISCC, &smram_miscc);
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if ((smram_miscc & I810_GFX_MEM_WIN_SIZE)
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== I810_GFX_MEM_WIN_32M)
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aperture_size = MB(32);
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else
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aperture_size = MB(64);
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} else if (INTEL_GTT_GEN == 2) {
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u16 gmch_ctrl;
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pci_read_config_word(intel_private.bridge_dev,
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@ -751,14 +703,7 @@ static int intel_gtt_init(void)
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global_cache_flush(); /* FIXME: ? */
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/* we have to call this as early as possible after the MMIO base address is known */
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intel_private.base.stolen_size = intel_gtt_stolen_size();
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if (intel_private.base.stolen_size == 0) {
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intel_private.driver->cleanup();
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iounmap(intel_private.registers);
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iounmap(intel_private.gtt);
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return -ENOMEM;
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}
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ret = intel_gtt_setup_scratch_page();
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if (ret != 0) {
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@ -851,7 +796,7 @@ static bool intel_enable_gtt(void)
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u32 gma_addr;
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u8 __iomem *reg;
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if (INTEL_GTT_GEN == 2)
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if (INTEL_GTT_GEN <= 2)
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pci_read_config_dword(intel_private.pcidev, I810_GMADDR,
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&gma_addr);
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else
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@ -1268,19 +1213,16 @@ static int i9xx_setup(void)
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static const struct agp_bridge_driver intel_810_driver = {
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.owner = THIS_MODULE,
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.aperture_sizes = intel_i810_sizes,
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.size_type = FIXED_APER_SIZE,
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.num_aperture_sizes = 2,
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.needs_scratch_page = true,
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.configure = intel_i810_configure,
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.fetch_size = intel_i810_fetch_size,
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.cleanup = intel_i810_cleanup,
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.mask_memory = intel_i810_mask_memory,
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.masks = intel_i810_masks,
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.aperture_sizes = intel_fake_agp_sizes,
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.num_aperture_sizes = ARRAY_SIZE(intel_fake_agp_sizes),
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.configure = intel_fake_agp_configure,
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.fetch_size = intel_fake_agp_fetch_size,
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.cleanup = intel_gtt_cleanup,
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.agp_enable = intel_fake_agp_enable,
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.cache_flush = global_cache_flush,
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.create_gatt_table = agp_generic_create_gatt_table,
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.free_gatt_table = agp_generic_free_gatt_table,
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.create_gatt_table = intel_fake_agp_create_gatt_table,
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.free_gatt_table = intel_fake_agp_free_gatt_table,
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.insert_memory = intel_i810_insert_entries,
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.remove_memory = intel_fake_agp_remove_entries,
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.alloc_by_type = intel_fake_agp_alloc_by_type,
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@ -1289,7 +1231,6 @@ static const struct agp_bridge_driver intel_810_driver = {
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.agp_alloc_pages = agp_generic_alloc_pages,
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.agp_destroy_page = agp_generic_destroy_page,
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.agp_destroy_pages = agp_generic_destroy_pages,
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.agp_type_to_mask_type = agp_generic_type_to_mask_type,
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};
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static const struct agp_bridge_driver intel_fake_agp_driver = {
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@ -1317,7 +1258,10 @@ static const struct agp_bridge_driver intel_fake_agp_driver = {
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static const struct intel_gtt_driver i81x_gtt_driver = {
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.gen = 1,
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.has_pgtbl_enable = 1,
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.dma_mask_size = 32,
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.setup = i810_setup,
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.cleanup = i810_cleanup,
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.check_flags = i830_check_flags,
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.write_entry = i810_write_entry,
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};
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@ -1549,8 +1493,8 @@ int intel_gmch_probe(struct pci_dev *pdev,
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pci_set_consistent_dma_mask(intel_private.pcidev,
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DMA_BIT_MASK(mask));
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if (bridge->driver == &intel_810_driver)
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return 1;
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/*if (bridge->driver == &intel_810_driver)
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return 1;*/
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if (intel_gtt_init() != 0)
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return 0;
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