serial: imx: Fix checkpatch errors related to spacing
Fixed checkpatch errors and warnings related to incorrect spacing. Cc: Shawn Guo <shawn.guo@linaro.org> Signed-off-by: Sachin Kamat <sachin.kamat@linaro.org> Acked-by: Sascha Hauer <s.hauer@pengutronix.de> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
This commit is contained in:
Sachin Kamat
Greg Kroah-Hartman
Родитель
905f4ba252
Коммит
82313e66b1
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@ -73,102 +73,102 @@
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#define IMX21_UTS 0xb4 /* UART Test Register on all other i.mx*/
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/* UART Control Register Bit Fields.*/
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#define URXD_CHARRDY (1<<15)
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#define URXD_ERR (1<<14)
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#define URXD_OVRRUN (1<<13)
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#define URXD_FRMERR (1<<12)
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#define URXD_BRK (1<<11)
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#define URXD_PRERR (1<<10)
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#define UCR1_ADEN (1<<15) /* Auto detect interrupt */
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#define UCR1_ADBR (1<<14) /* Auto detect baud rate */
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#define UCR1_TRDYEN (1<<13) /* Transmitter ready interrupt enable */
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#define UCR1_IDEN (1<<12) /* Idle condition interrupt */
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#define UCR1_RRDYEN (1<<9) /* Recv ready interrupt enable */
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#define UCR1_RDMAEN (1<<8) /* Recv ready DMA enable */
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#define UCR1_IREN (1<<7) /* Infrared interface enable */
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#define UCR1_TXMPTYEN (1<<6) /* Transimitter empty interrupt enable */
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#define UCR1_RTSDEN (1<<5) /* RTS delta interrupt enable */
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#define UCR1_SNDBRK (1<<4) /* Send break */
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#define UCR1_TDMAEN (1<<3) /* Transmitter ready DMA enable */
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#define IMX1_UCR1_UARTCLKEN (1<<2) /* UART clock enabled, i.mx1 only */
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#define UCR1_DOZE (1<<1) /* Doze */
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#define UCR1_UARTEN (1<<0) /* UART enabled */
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#define UCR2_ESCI (1<<15) /* Escape seq interrupt enable */
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#define UCR2_IRTS (1<<14) /* Ignore RTS pin */
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#define UCR2_CTSC (1<<13) /* CTS pin control */
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#define UCR2_CTS (1<<12) /* Clear to send */
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#define UCR2_ESCEN (1<<11) /* Escape enable */
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#define UCR2_PREN (1<<8) /* Parity enable */
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#define UCR2_PROE (1<<7) /* Parity odd/even */
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#define UCR2_STPB (1<<6) /* Stop */
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#define UCR2_WS (1<<5) /* Word size */
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#define UCR2_RTSEN (1<<4) /* Request to send interrupt enable */
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#define UCR2_ATEN (1<<3) /* Aging Timer Enable */
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#define UCR2_TXEN (1<<2) /* Transmitter enabled */
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#define UCR2_RXEN (1<<1) /* Receiver enabled */
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#define UCR2_SRST (1<<0) /* SW reset */
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#define UCR3_DTREN (1<<13) /* DTR interrupt enable */
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#define UCR3_PARERREN (1<<12) /* Parity enable */
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#define UCR3_FRAERREN (1<<11) /* Frame error interrupt enable */
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#define UCR3_DSR (1<<10) /* Data set ready */
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#define UCR3_DCD (1<<9) /* Data carrier detect */
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#define UCR3_RI (1<<8) /* Ring indicator */
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#define UCR3_TIMEOUTEN (1<<7) /* Timeout interrupt enable */
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#define UCR3_RXDSEN (1<<6) /* Receive status interrupt enable */
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#define UCR3_AIRINTEN (1<<5) /* Async IR wake interrupt enable */
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#define UCR3_AWAKEN (1<<4) /* Async wake interrupt enable */
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#define IMX21_UCR3_RXDMUXSEL (1<<2) /* RXD Muxed Input Select */
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#define UCR3_INVT (1<<1) /* Inverted Infrared transmission */
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#define UCR3_BPEN (1<<0) /* Preset registers enable */
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#define UCR4_CTSTL_SHF 10 /* CTS trigger level shift */
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#define UCR4_CTSTL_MASK 0x3F /* CTS trigger is 6 bits wide */
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#define UCR4_INVR (1<<9) /* Inverted infrared reception */
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#define UCR4_ENIRI (1<<8) /* Serial infrared interrupt enable */
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#define UCR4_WKEN (1<<7) /* Wake interrupt enable */
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#define UCR4_REF16 (1<<6) /* Ref freq 16 MHz */
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#define UCR4_IRSC (1<<5) /* IR special case */
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#define UCR4_TCEN (1<<3) /* Transmit complete interrupt enable */
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#define UCR4_BKEN (1<<2) /* Break condition interrupt enable */
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#define UCR4_OREN (1<<1) /* Receiver overrun interrupt enable */
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#define UCR4_DREN (1<<0) /* Recv data ready interrupt enable */
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#define UFCR_RXTL_SHF 0 /* Receiver trigger level shift */
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#define UFCR_DCEDTE (1<<6) /* DCE/DTE mode select */
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#define UFCR_RFDIV (7<<7) /* Reference freq divider mask */
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#define UFCR_RFDIV_REG(x) (((x) < 7 ? 6 - (x) : 6) << 7)
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#define UFCR_TXTL_SHF 10 /* Transmitter trigger level shift */
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#define USR1_PARITYERR (1<<15) /* Parity error interrupt flag */
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#define USR1_RTSS (1<<14) /* RTS pin status */
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#define USR1_TRDY (1<<13) /* Transmitter ready interrupt/dma flag */
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#define USR1_RTSD (1<<12) /* RTS delta */
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#define USR1_ESCF (1<<11) /* Escape seq interrupt flag */
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#define USR1_FRAMERR (1<<10) /* Frame error interrupt flag */
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#define USR1_RRDY (1<<9) /* Receiver ready interrupt/dma flag */
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#define USR1_TIMEOUT (1<<7) /* Receive timeout interrupt status */
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#define USR1_RXDS (1<<6) /* Receiver idle interrupt flag */
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#define USR1_AIRINT (1<<5) /* Async IR wake interrupt flag */
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#define USR1_AWAKE (1<<4) /* Aysnc wake interrupt flag */
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#define USR2_ADET (1<<15) /* Auto baud rate detect complete */
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#define USR2_TXFE (1<<14) /* Transmit buffer FIFO empty */
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#define USR2_DTRF (1<<13) /* DTR edge interrupt flag */
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#define USR2_IDLE (1<<12) /* Idle condition */
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#define USR2_IRINT (1<<8) /* Serial infrared interrupt flag */
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#define USR2_WAKE (1<<7) /* Wake */
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#define USR2_RTSF (1<<4) /* RTS edge interrupt flag */
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#define USR2_TXDC (1<<3) /* Transmitter complete */
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#define USR2_BRCD (1<<2) /* Break condition */
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#define USR2_ORE (1<<1) /* Overrun error */
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#define USR2_RDR (1<<0) /* Recv data ready */
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#define UTS_FRCPERR (1<<13) /* Force parity error */
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#define UTS_LOOP (1<<12) /* Loop tx and rx */
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#define UTS_TXEMPTY (1<<6) /* TxFIFO empty */
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#define UTS_RXEMPTY (1<<5) /* RxFIFO empty */
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#define UTS_TXFULL (1<<4) /* TxFIFO full */
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#define UTS_RXFULL (1<<3) /* RxFIFO full */
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#define UTS_SOFTRST (1<<0) /* Software reset */
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#define URXD_CHARRDY (1<<15)
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#define URXD_ERR (1<<14)
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#define URXD_OVRRUN (1<<13)
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#define URXD_FRMERR (1<<12)
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#define URXD_BRK (1<<11)
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#define URXD_PRERR (1<<10)
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#define UCR1_ADEN (1<<15) /* Auto detect interrupt */
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#define UCR1_ADBR (1<<14) /* Auto detect baud rate */
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#define UCR1_TRDYEN (1<<13) /* Transmitter ready interrupt enable */
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#define UCR1_IDEN (1<<12) /* Idle condition interrupt */
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#define UCR1_RRDYEN (1<<9) /* Recv ready interrupt enable */
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#define UCR1_RDMAEN (1<<8) /* Recv ready DMA enable */
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#define UCR1_IREN (1<<7) /* Infrared interface enable */
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#define UCR1_TXMPTYEN (1<<6) /* Transimitter empty interrupt enable */
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#define UCR1_RTSDEN (1<<5) /* RTS delta interrupt enable */
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#define UCR1_SNDBRK (1<<4) /* Send break */
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#define UCR1_TDMAEN (1<<3) /* Transmitter ready DMA enable */
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#define IMX1_UCR1_UARTCLKEN (1<<2) /* UART clock enabled, i.mx1 only */
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#define UCR1_DOZE (1<<1) /* Doze */
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#define UCR1_UARTEN (1<<0) /* UART enabled */
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#define UCR2_ESCI (1<<15) /* Escape seq interrupt enable */
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#define UCR2_IRTS (1<<14) /* Ignore RTS pin */
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#define UCR2_CTSC (1<<13) /* CTS pin control */
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#define UCR2_CTS (1<<12) /* Clear to send */
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#define UCR2_ESCEN (1<<11) /* Escape enable */
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#define UCR2_PREN (1<<8) /* Parity enable */
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#define UCR2_PROE (1<<7) /* Parity odd/even */
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#define UCR2_STPB (1<<6) /* Stop */
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#define UCR2_WS (1<<5) /* Word size */
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#define UCR2_RTSEN (1<<4) /* Request to send interrupt enable */
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#define UCR2_ATEN (1<<3) /* Aging Timer Enable */
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#define UCR2_TXEN (1<<2) /* Transmitter enabled */
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#define UCR2_RXEN (1<<1) /* Receiver enabled */
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#define UCR2_SRST (1<<0) /* SW reset */
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#define UCR3_DTREN (1<<13) /* DTR interrupt enable */
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#define UCR3_PARERREN (1<<12) /* Parity enable */
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#define UCR3_FRAERREN (1<<11) /* Frame error interrupt enable */
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#define UCR3_DSR (1<<10) /* Data set ready */
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#define UCR3_DCD (1<<9) /* Data carrier detect */
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#define UCR3_RI (1<<8) /* Ring indicator */
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#define UCR3_TIMEOUTEN (1<<7) /* Timeout interrupt enable */
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#define UCR3_RXDSEN (1<<6) /* Receive status interrupt enable */
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#define UCR3_AIRINTEN (1<<5) /* Async IR wake interrupt enable */
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#define UCR3_AWAKEN (1<<4) /* Async wake interrupt enable */
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#define IMX21_UCR3_RXDMUXSEL (1<<2) /* RXD Muxed Input Select */
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#define UCR3_INVT (1<<1) /* Inverted Infrared transmission */
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#define UCR3_BPEN (1<<0) /* Preset registers enable */
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#define UCR4_CTSTL_SHF 10 /* CTS trigger level shift */
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#define UCR4_CTSTL_MASK 0x3F /* CTS trigger is 6 bits wide */
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#define UCR4_INVR (1<<9) /* Inverted infrared reception */
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#define UCR4_ENIRI (1<<8) /* Serial infrared interrupt enable */
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#define UCR4_WKEN (1<<7) /* Wake interrupt enable */
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#define UCR4_REF16 (1<<6) /* Ref freq 16 MHz */
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#define UCR4_IRSC (1<<5) /* IR special case */
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#define UCR4_TCEN (1<<3) /* Transmit complete interrupt enable */
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#define UCR4_BKEN (1<<2) /* Break condition interrupt enable */
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#define UCR4_OREN (1<<1) /* Receiver overrun interrupt enable */
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#define UCR4_DREN (1<<0) /* Recv data ready interrupt enable */
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#define UFCR_RXTL_SHF 0 /* Receiver trigger level shift */
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#define UFCR_DCEDTE (1<<6) /* DCE/DTE mode select */
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#define UFCR_RFDIV (7<<7) /* Reference freq divider mask */
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#define UFCR_RFDIV_REG(x) (((x) < 7 ? 6 - (x) : 6) << 7)
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#define UFCR_TXTL_SHF 10 /* Transmitter trigger level shift */
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#define USR1_PARITYERR (1<<15) /* Parity error interrupt flag */
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#define USR1_RTSS (1<<14) /* RTS pin status */
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#define USR1_TRDY (1<<13) /* Transmitter ready interrupt/dma flag */
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#define USR1_RTSD (1<<12) /* RTS delta */
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#define USR1_ESCF (1<<11) /* Escape seq interrupt flag */
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#define USR1_FRAMERR (1<<10) /* Frame error interrupt flag */
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#define USR1_RRDY (1<<9) /* Receiver ready interrupt/dma flag */
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#define USR1_TIMEOUT (1<<7) /* Receive timeout interrupt status */
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#define USR1_RXDS (1<<6) /* Receiver idle interrupt flag */
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#define USR1_AIRINT (1<<5) /* Async IR wake interrupt flag */
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#define USR1_AWAKE (1<<4) /* Aysnc wake interrupt flag */
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#define USR2_ADET (1<<15) /* Auto baud rate detect complete */
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#define USR2_TXFE (1<<14) /* Transmit buffer FIFO empty */
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#define USR2_DTRF (1<<13) /* DTR edge interrupt flag */
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#define USR2_IDLE (1<<12) /* Idle condition */
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#define USR2_IRINT (1<<8) /* Serial infrared interrupt flag */
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#define USR2_WAKE (1<<7) /* Wake */
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#define USR2_RTSF (1<<4) /* RTS edge interrupt flag */
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#define USR2_TXDC (1<<3) /* Transmitter complete */
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#define USR2_BRCD (1<<2) /* Break condition */
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#define USR2_ORE (1<<1) /* Overrun error */
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#define USR2_RDR (1<<0) /* Recv data ready */
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#define UTS_FRCPERR (1<<13) /* Force parity error */
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#define UTS_LOOP (1<<12) /* Loop tx and rx */
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#define UTS_TXEMPTY (1<<6) /* TxFIFO empty */
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#define UTS_RXEMPTY (1<<5) /* RxFIFO empty */
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#define UTS_TXFULL (1<<4) /* TxFIFO full */
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#define UTS_RXFULL (1<<3) /* RxFIFO full */
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#define UTS_SOFTRST (1<<0) /* Software reset */
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/* We've been assigned a range on the "Low-density serial ports" major */
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#define SERIAL_IMX_MAJOR 207
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#define MINOR_START 16
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#define SERIAL_IMX_MAJOR 207
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#define MINOR_START 16
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#define DEV_NAME "ttymxc"
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/*
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@ -199,7 +199,7 @@ struct imx_port {
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struct uart_port port;
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struct timer_list timer;
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unsigned int old_status;
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int txirq,rxirq,rtsirq;
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int txirq, rxirq, rtsirq;
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unsigned int have_rtscts:1;
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unsigned int use_irda:1;
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unsigned int irda_inv_rx:1;
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@ -397,7 +397,7 @@ static void imx_stop_rx(struct uart_port *port)
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unsigned long temp;
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temp = readl(sport->port.membase + UCR2);
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writel(temp &~ UCR2_RXEN, sport->port.membase + UCR2);
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writel(temp & ~UCR2_RXEN, sport->port.membase + UCR2);
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}
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/*
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@ -490,7 +490,7 @@ static irqreturn_t imx_txint(int irq, void *dev_id)
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struct circ_buf *xmit = &sport->port.state->xmit;
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unsigned long flags;
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spin_lock_irqsave(&sport->port.lock,flags);
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spin_lock_irqsave(&sport->port.lock, flags);
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if (sport->port.x_char)
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{
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/* Send next char */
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@ -509,18 +509,18 @@ static irqreturn_t imx_txint(int irq, void *dev_id)
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uart_write_wakeup(&sport->port);
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out:
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spin_unlock_irqrestore(&sport->port.lock,flags);
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spin_unlock_irqrestore(&sport->port.lock, flags);
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return IRQ_HANDLED;
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}
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static irqreturn_t imx_rxint(int irq, void *dev_id)
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{
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struct imx_port *sport = dev_id;
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unsigned int rx,flg,ignored = 0;
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unsigned int rx, flg, ignored = 0;
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struct tty_struct *tty = sport->port.state->port.tty;
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unsigned long flags, temp;
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spin_lock_irqsave(&sport->port.lock,flags);
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spin_lock_irqsave(&sport->port.lock, flags);
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while (readl(sport->port.membase + USR2) & USR2_RDR) {
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flg = TTY_NORMAL;
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@ -574,7 +574,7 @@ static irqreturn_t imx_rxint(int irq, void *dev_id)
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}
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out:
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spin_unlock_irqrestore(&sport->port.lock,flags);
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spin_unlock_irqrestore(&sport->port.lock, flags);
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tty_flip_buffer_push(tty);
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return IRQ_HANDLED;
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}
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@ -654,7 +654,7 @@ static void imx_break_ctl(struct uart_port *port, int break_state)
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temp = readl(sport->port.membase + UCR1) & ~UCR1_SNDBRK;
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if ( break_state != 0 )
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if (break_state != 0)
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temp |= UCR1_SNDBRK;
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writel(temp, sport->port.membase + UCR1);
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@ -696,8 +696,8 @@ static int imx_startup(struct uart_port *port)
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temp |= UCR4_IRSC;
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/* set the trigger level for CTS */
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temp &= ~(UCR4_CTSTL_MASK<< UCR4_CTSTL_SHF);
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temp |= CTSTL<< UCR4_CTSTL_SHF;
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temp &= ~(UCR4_CTSTL_MASK << UCR4_CTSTL_SHF);
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temp |= CTSTL << UCR4_CTSTL_SHF;
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writel(temp & ~UCR4_DREN, sport->port.membase + UCR4);
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@ -799,7 +799,7 @@ static int imx_startup(struct uart_port *port)
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* Enable modem status interrupts
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*/
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imx_enable_ms(&sport->port);
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spin_unlock_irqrestore(&sport->port.lock,flags);
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spin_unlock_irqrestore(&sport->port.lock, flags);
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if (USE_IRDA(sport)) {
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struct imxuart_platform_data *pdata;
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@ -909,7 +909,7 @@ imx_set_termios(struct uart_port *port, struct ktermios *termios,
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ucr2 = UCR2_SRST | UCR2_IRTS;
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if (termios->c_cflag & CRTSCTS) {
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if( sport->have_rtscts ) {
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if (sport->have_rtscts) {
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ucr2 &= ~UCR2_IRTS;
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ucr2 |= UCR2_CTSC;
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} else {
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@ -969,12 +969,12 @@ imx_set_termios(struct uart_port *port, struct ktermios *termios,
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writel(old_ucr1 & ~(UCR1_TXMPTYEN | UCR1_RRDYEN | UCR1_RTSDEN),
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sport->port.membase + UCR1);
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while ( !(readl(sport->port.membase + USR2) & USR2_TXDC))
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while (!(readl(sport->port.membase + USR2) & USR2_TXDC))
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barrier();
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/* then, disable everything */
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old_txrxen = readl(sport->port.membase + UCR2);
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writel(old_txrxen & ~( UCR2_TXEN | UCR2_RXEN),
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writel(old_txrxen & ~(UCR2_TXEN | UCR2_RXEN),
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sport->port.membase + UCR2);
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old_txrxen &= (UCR2_TXEN | UCR2_RXEN);
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@ -1255,7 +1255,7 @@ imx_console_get_options(struct imx_port *sport, int *baud,
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if (readl(sport->port.membase + UCR1) & UCR1_UARTEN) {
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/* ok, the port was enabled */
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unsigned int ucr2, ubir,ubmr, uartclk;
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unsigned int ucr2, ubir, ubmr, uartclk;
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unsigned int baud_raw;
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unsigned int ucfr_rfdiv;
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@ -1301,7 +1301,7 @@ imx_console_get_options(struct imx_port *sport, int *baud,
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*baud = (baud_raw + 50) / 100 * 100;
|
||||
}
|
||||
|
||||
if(*baud != baud_raw)
|
||||
if (*baud != baud_raw)
|
||||
printk(KERN_INFO "Serial: Console IMX rounded baud rate from %d to %d\n",
|
||||
baud_raw, *baud);
|
||||
}
|
||||
|
|
@ -1324,7 +1324,7 @@ imx_console_setup(struct console *co, char *options)
|
|||
if (co->index == -1 || co->index >= ARRAY_SIZE(imx_ports))
|
||||
co->index = 0;
|
||||
sport = imx_ports[co->index];
|
||||
if(sport == NULL)
|
||||
if (sport == NULL)
|
||||
return -ENODEV;
|
||||
|
||||
if (options)
|
||||
|
|
|
|||
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