irqchip: mips-gic: Clean up header file
Remove duplicate #defines and unnecessary #includes, fix parenthesization, and re-order register definitions in ascending order. Signed-off-by: Andrew Bresticker <abrestic@chromium.org> Cc: Daniel Lezcano <daniel.lezcano@linaro.org> Cc: Thomas Gleixner <tglx@linutronix.de> Cc: Jason Cooper <jason@lakedaemon.net> Cc: Paul Burton <paul.burton@imgtec.com> Cc: Qais Yousef <qais.yousef@imgtec.com> Cc: John Crispin <blogic@openwrt.org> Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/8128/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
This commit is contained in:
Andrew Bresticker
Ralf Baechle
Родитель
7110e227c8
Коммит
824f3f7fa2
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@ -253,8 +253,8 @@ static unsigned int gic_get_int(void)
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intrmask = intrmask_regs[smp_processor_id()].intrmask;
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pcpu_mask = pcpu_masks[smp_processor_id()].pcpu_mask;
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pending_reg = GIC_REG(SHARED, GIC_SH_PEND_31_0);
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intrmask_reg = GIC_REG(SHARED, GIC_SH_MASK_31_0);
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pending_reg = GIC_REG(SHARED, GIC_SH_PEND);
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intrmask_reg = GIC_REG(SHARED, GIC_SH_MASK);
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for (i = 0; i < BITS_TO_LONGS(gic_shared_intrs); i++) {
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pending[i] = gic_read(pending_reg);
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@ -4,17 +4,11 @@
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* for more details.
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*
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* Copyright (C) 2000, 07 MIPS Technologies, Inc.
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*
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* GIC Register Definitions
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*
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*/
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#ifndef _ASM_GICREGS_H
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#define _ASM_GICREGS_H
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#ifndef __LINUX_IRQCHIP_MIPS_GIC_H
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#define __LINUX_IRQCHIP_MIPS_GIC_H
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#include <linux/bitmap.h>
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#include <linux/threads.h>
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#include <irq.h>
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#include <linux/clocksource.h>
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#define GIC_MAX_INTRS 256
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@ -50,94 +44,9 @@
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#define GIC_SH_COUNTER_63_32_OFS 0x0014
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#define GIC_SH_REVISIONID_OFS 0x0020
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/* Interrupt Polarity */
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#define GIC_SH_POL_31_0_OFS 0x0100
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#define GIC_SH_POL_63_32_OFS 0x0104
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#define GIC_SH_POL_95_64_OFS 0x0108
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#define GIC_SH_POL_127_96_OFS 0x010c
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#define GIC_SH_POL_159_128_OFS 0x0110
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#define GIC_SH_POL_191_160_OFS 0x0114
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#define GIC_SH_POL_223_192_OFS 0x0118
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#define GIC_SH_POL_255_224_OFS 0x011c
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/* Edge/Level Triggering */
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#define GIC_SH_TRIG_31_0_OFS 0x0180
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#define GIC_SH_TRIG_63_32_OFS 0x0184
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#define GIC_SH_TRIG_95_64_OFS 0x0188
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#define GIC_SH_TRIG_127_96_OFS 0x018c
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#define GIC_SH_TRIG_159_128_OFS 0x0190
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#define GIC_SH_TRIG_191_160_OFS 0x0194
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#define GIC_SH_TRIG_223_192_OFS 0x0198
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#define GIC_SH_TRIG_255_224_OFS 0x019c
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/* Dual Edge Triggering */
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#define GIC_SH_DUAL_31_0_OFS 0x0200
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#define GIC_SH_DUAL_63_32_OFS 0x0204
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#define GIC_SH_DUAL_95_64_OFS 0x0208
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#define GIC_SH_DUAL_127_96_OFS 0x020c
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#define GIC_SH_DUAL_159_128_OFS 0x0210
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#define GIC_SH_DUAL_191_160_OFS 0x0214
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#define GIC_SH_DUAL_223_192_OFS 0x0218
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#define GIC_SH_DUAL_255_224_OFS 0x021c
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/* Set/Clear corresponding bit in Edge Detect Register */
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#define GIC_SH_WEDGE_OFS 0x0280
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/* Reset Mask - Disables Interrupt */
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#define GIC_SH_RMASK_31_0_OFS 0x0300
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#define GIC_SH_RMASK_63_32_OFS 0x0304
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#define GIC_SH_RMASK_95_64_OFS 0x0308
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#define GIC_SH_RMASK_127_96_OFS 0x030c
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#define GIC_SH_RMASK_159_128_OFS 0x0310
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#define GIC_SH_RMASK_191_160_OFS 0x0314
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#define GIC_SH_RMASK_223_192_OFS 0x0318
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#define GIC_SH_RMASK_255_224_OFS 0x031c
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/* Set Mask (WO) - Enables Interrupt */
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#define GIC_SH_SMASK_31_0_OFS 0x0380
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#define GIC_SH_SMASK_63_32_OFS 0x0384
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#define GIC_SH_SMASK_95_64_OFS 0x0388
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#define GIC_SH_SMASK_127_96_OFS 0x038c
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#define GIC_SH_SMASK_159_128_OFS 0x0390
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#define GIC_SH_SMASK_191_160_OFS 0x0394
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#define GIC_SH_SMASK_223_192_OFS 0x0398
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#define GIC_SH_SMASK_255_224_OFS 0x039c
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/* Global Interrupt Mask Register (RO) - Bit Set == Interrupt enabled */
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#define GIC_SH_MASK_31_0_OFS 0x0400
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#define GIC_SH_MASK_63_32_OFS 0x0404
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#define GIC_SH_MASK_95_64_OFS 0x0408
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#define GIC_SH_MASK_127_96_OFS 0x040c
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#define GIC_SH_MASK_159_128_OFS 0x0410
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#define GIC_SH_MASK_191_160_OFS 0x0414
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#define GIC_SH_MASK_223_192_OFS 0x0418
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#define GIC_SH_MASK_255_224_OFS 0x041c
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/* Pending Global Interrupts (RO) */
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#define GIC_SH_PEND_31_0_OFS 0x0480
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#define GIC_SH_PEND_63_32_OFS 0x0484
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#define GIC_SH_PEND_95_64_OFS 0x0488
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#define GIC_SH_PEND_127_96_OFS 0x048c
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#define GIC_SH_PEND_159_128_OFS 0x0490
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#define GIC_SH_PEND_191_160_OFS 0x0494
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#define GIC_SH_PEND_223_192_OFS 0x0498
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#define GIC_SH_PEND_255_224_OFS 0x049c
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#define GIC_SH_INTR_MAP_TO_PIN_BASE_OFS 0x0500
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/* Maps Interrupt X to a Pin */
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#define GIC_SH_MAP_TO_PIN(intr) (4 * (intr))
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#define GIC_SH_INTR_MAP_TO_VPE_BASE_OFS 0x2000
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/* Maps Interrupt X to a VPE */
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#define GIC_SH_MAP_TO_VPE_REG_OFF(intr, vpe) \
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((32 * (intr)) + (((vpe) / 32) * 4))
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#define GIC_SH_MAP_TO_VPE_REG_BIT(vpe) (1 << ((vpe) % 32))
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/* Convert an interrupt number to a byte offset/bit for multi-word registers */
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#define GIC_INTR_OFS(intr) (((intr) / 32)*4)
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#define GIC_INTR_BIT(intr) ((intr) % 32)
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#define GIC_INTR_OFS(intr) (((intr) / 32) * 4)
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#define GIC_INTR_BIT(intr) ((intr) % 32)
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/* Polarity : Reset Value is always 0 */
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#define GIC_SH_SET_POLARITY_OFS 0x0100
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@ -148,9 +57,28 @@
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/* Dual edge triggering : Reset Value is always 0 */
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#define GIC_SH_SET_DUAL_OFS 0x0200
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/* Set/Clear corresponding bit in Edge Detect Register */
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#define GIC_SH_WEDGE_OFS 0x0280
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/* Mask manipulation */
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#define GIC_SH_SMASK_OFS 0x0380
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#define GIC_SH_RMASK_OFS 0x0300
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#define GIC_SH_SMASK_OFS 0x0380
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/* Global Interrupt Mask Register (RO) - Bit Set == Interrupt enabled */
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#define GIC_SH_MASK_OFS 0x0400
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/* Pending Global Interrupts (RO) */
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#define GIC_SH_PEND_OFS 0x0480
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/* Maps Interrupt X to a Pin */
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#define GIC_SH_INTR_MAP_TO_PIN_BASE_OFS 0x0500
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#define GIC_SH_MAP_TO_PIN(intr) (4 * (intr))
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/* Maps Interrupt X to a VPE */
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#define GIC_SH_INTR_MAP_TO_VPE_BASE_OFS 0x2000
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#define GIC_SH_MAP_TO_VPE_REG_OFF(intr, vpe) \
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((32 * (intr)) + (((vpe) / 32) * 4))
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#define GIC_SH_MAP_TO_VPE_REG_BIT(vpe) (1 << ((vpe) % 32))
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/* Register Map for Local Section */
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#define GIC_VPE_CTL_OFS 0x0000
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@ -200,8 +128,8 @@
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#define GIC_SH_CONFIG_NUMVPES_SHF 0
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#define GIC_SH_CONFIG_NUMVPES_MSK (MSK(8) << GIC_SH_CONFIG_NUMVPES_SHF)
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#define GIC_SH_WEDGE_SET(intr) (intr | (0x1 << 31))
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#define GIC_SH_WEDGE_CLR(intr) (intr & ~(0x1 << 31))
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#define GIC_SH_WEDGE_SET(intr) ((intr) | (0x1 << 31))
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#define GIC_SH_WEDGE_CLR(intr) ((intr) & ~(0x1 << 31))
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#define GIC_MAP_TO_PIN_SHF 31
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#define GIC_MAP_TO_PIN_MSK (MSK(1) << GIC_MAP_TO_PIN_SHF)
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@ -278,10 +206,10 @@
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#define GIC_CPU_PIN_OFFSET 2
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/* Add 2 to convert non-EIC hardware interrupt to EIC vector number. */
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#define GIC_CPU_TO_VEC_OFFSET (2)
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#define GIC_CPU_TO_VEC_OFFSET 2
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/* Mapped interrupt to pin X, then GIC will generate the vector (X+1). */
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#define GIC_PIN_TO_VEC_OFFSET (1)
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#define GIC_PIN_TO_VEC_OFFSET 1
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/* Local GIC interrupts. */
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#define GIC_LOCAL_INT_WD 0 /* GIC watchdog */
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@ -301,9 +229,6 @@
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#define GIC_SHARED_TO_HWIRQ(x) (GIC_SHARED_HWIRQ_BASE + (x))
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#define GIC_HWIRQ_TO_SHARED(x) ((x) - GIC_SHARED_HWIRQ_BASE)
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#include <linux/clocksource.h>
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#include <linux/irq.h>
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extern unsigned int gic_present;
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extern unsigned int gic_frequency;
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@ -322,4 +247,4 @@ extern unsigned int plat_ipi_resched_int_xlate(unsigned int);
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extern unsigned int gic_get_timer_pending(void);
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extern int gic_get_c0_compare_int(void);
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extern int gic_get_c0_perfcount_int(void);
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#endif /* _ASM_GICREGS_H */
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#endif /* __LINUX_IRQCHIP_MIPS_GIC_H */
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