perf/x86/uncore: Move SNB/IVB-EP specific code to seperate file
Signed-off-by: Yan, Zheng <zheng.z.yan@intel.com> Signed-off-by: Peter Zijlstra <peterz@infradead.org> Cc: Andi Kleen <ak@linux.intel.com> Cc: Arnaldo Carvalho de Melo <acme@kernel.org> Cc: Borislav Petkov <bp@suse.de> Cc: Paul Mackerras <paulus@samba.org> Cc: Stephane Eranian <eranian@google.com> Link: http://lkml.kernel.org/r/1406704935-27708-3-git-send-email-zheng.z.yan@intel.com Signed-off-by: Ingo Molnar <mingo@kernel.org>
This commit is contained in:
Yan, Zheng
Ingo Molnar
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92807ffdf3
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8268fdfc45
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@ -37,6 +37,7 @@ endif
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obj-$(CONFIG_CPU_SUP_INTEL) += perf_event_p6.o perf_event_knc.o perf_event_p4.o
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obj-$(CONFIG_CPU_SUP_INTEL) += perf_event_intel_lbr.o perf_event_intel_ds.o perf_event_intel.o
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obj-$(CONFIG_CPU_SUP_INTEL) += perf_event_intel_uncore.o perf_event_intel_uncore_snb.o
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obj-$(CONFIG_CPU_SUP_INTEL) += perf_event_intel_uncore_snbep.o
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obj-$(CONFIG_CPU_SUP_INTEL) += perf_event_intel_rapl.o
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endif
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@ -24,164 +24,6 @@
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#define UNCORE_EVENT_CONSTRAINT(c, n) EVENT_CONSTRAINT(c, n, 0xff)
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/* SNB-EP Box level control */
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#define SNBEP_PMON_BOX_CTL_RST_CTRL (1 << 0)
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#define SNBEP_PMON_BOX_CTL_RST_CTRS (1 << 1)
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#define SNBEP_PMON_BOX_CTL_FRZ (1 << 8)
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#define SNBEP_PMON_BOX_CTL_FRZ_EN (1 << 16)
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#define SNBEP_PMON_BOX_CTL_INT (SNBEP_PMON_BOX_CTL_RST_CTRL | \
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SNBEP_PMON_BOX_CTL_RST_CTRS | \
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SNBEP_PMON_BOX_CTL_FRZ_EN)
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/* SNB-EP event control */
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#define SNBEP_PMON_CTL_EV_SEL_MASK 0x000000ff
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#define SNBEP_PMON_CTL_UMASK_MASK 0x0000ff00
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#define SNBEP_PMON_CTL_RST (1 << 17)
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#define SNBEP_PMON_CTL_EDGE_DET (1 << 18)
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#define SNBEP_PMON_CTL_EV_SEL_EXT (1 << 21)
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#define SNBEP_PMON_CTL_EN (1 << 22)
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#define SNBEP_PMON_CTL_INVERT (1 << 23)
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#define SNBEP_PMON_CTL_TRESH_MASK 0xff000000
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#define SNBEP_PMON_RAW_EVENT_MASK (SNBEP_PMON_CTL_EV_SEL_MASK | \
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SNBEP_PMON_CTL_UMASK_MASK | \
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SNBEP_PMON_CTL_EDGE_DET | \
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SNBEP_PMON_CTL_INVERT | \
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SNBEP_PMON_CTL_TRESH_MASK)
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/* SNB-EP Ubox event control */
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#define SNBEP_U_MSR_PMON_CTL_TRESH_MASK 0x1f000000
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#define SNBEP_U_MSR_PMON_RAW_EVENT_MASK \
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(SNBEP_PMON_CTL_EV_SEL_MASK | \
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SNBEP_PMON_CTL_UMASK_MASK | \
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SNBEP_PMON_CTL_EDGE_DET | \
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SNBEP_PMON_CTL_INVERT | \
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SNBEP_U_MSR_PMON_CTL_TRESH_MASK)
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#define SNBEP_CBO_PMON_CTL_TID_EN (1 << 19)
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#define SNBEP_CBO_MSR_PMON_RAW_EVENT_MASK (SNBEP_PMON_RAW_EVENT_MASK | \
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SNBEP_CBO_PMON_CTL_TID_EN)
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/* SNB-EP PCU event control */
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#define SNBEP_PCU_MSR_PMON_CTL_OCC_SEL_MASK 0x0000c000
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#define SNBEP_PCU_MSR_PMON_CTL_TRESH_MASK 0x1f000000
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#define SNBEP_PCU_MSR_PMON_CTL_OCC_INVERT (1 << 30)
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#define SNBEP_PCU_MSR_PMON_CTL_OCC_EDGE_DET (1 << 31)
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#define SNBEP_PCU_MSR_PMON_RAW_EVENT_MASK \
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(SNBEP_PMON_CTL_EV_SEL_MASK | \
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SNBEP_PCU_MSR_PMON_CTL_OCC_SEL_MASK | \
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SNBEP_PMON_CTL_EDGE_DET | \
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SNBEP_PMON_CTL_EV_SEL_EXT | \
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SNBEP_PMON_CTL_INVERT | \
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SNBEP_PCU_MSR_PMON_CTL_TRESH_MASK | \
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SNBEP_PCU_MSR_PMON_CTL_OCC_INVERT | \
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SNBEP_PCU_MSR_PMON_CTL_OCC_EDGE_DET)
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#define SNBEP_QPI_PCI_PMON_RAW_EVENT_MASK \
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(SNBEP_PMON_RAW_EVENT_MASK | \
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SNBEP_PMON_CTL_EV_SEL_EXT)
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/* SNB-EP pci control register */
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#define SNBEP_PCI_PMON_BOX_CTL 0xf4
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#define SNBEP_PCI_PMON_CTL0 0xd8
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/* SNB-EP pci counter register */
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#define SNBEP_PCI_PMON_CTR0 0xa0
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/* SNB-EP home agent register */
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#define SNBEP_HA_PCI_PMON_BOX_ADDRMATCH0 0x40
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#define SNBEP_HA_PCI_PMON_BOX_ADDRMATCH1 0x44
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#define SNBEP_HA_PCI_PMON_BOX_OPCODEMATCH 0x48
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/* SNB-EP memory controller register */
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#define SNBEP_MC_CHy_PCI_PMON_FIXED_CTL 0xf0
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#define SNBEP_MC_CHy_PCI_PMON_FIXED_CTR 0xd0
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/* SNB-EP QPI register */
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#define SNBEP_Q_Py_PCI_PMON_PKT_MATCH0 0x228
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#define SNBEP_Q_Py_PCI_PMON_PKT_MATCH1 0x22c
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#define SNBEP_Q_Py_PCI_PMON_PKT_MASK0 0x238
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#define SNBEP_Q_Py_PCI_PMON_PKT_MASK1 0x23c
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/* SNB-EP Ubox register */
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#define SNBEP_U_MSR_PMON_CTR0 0xc16
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#define SNBEP_U_MSR_PMON_CTL0 0xc10
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#define SNBEP_U_MSR_PMON_UCLK_FIXED_CTL 0xc08
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#define SNBEP_U_MSR_PMON_UCLK_FIXED_CTR 0xc09
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/* SNB-EP Cbo register */
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#define SNBEP_C0_MSR_PMON_CTR0 0xd16
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#define SNBEP_C0_MSR_PMON_CTL0 0xd10
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#define SNBEP_C0_MSR_PMON_BOX_CTL 0xd04
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#define SNBEP_C0_MSR_PMON_BOX_FILTER 0xd14
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#define SNBEP_CBO_MSR_OFFSET 0x20
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#define SNBEP_CB0_MSR_PMON_BOX_FILTER_TID 0x1f
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#define SNBEP_CB0_MSR_PMON_BOX_FILTER_NID 0x3fc00
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#define SNBEP_CB0_MSR_PMON_BOX_FILTER_STATE 0x7c0000
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#define SNBEP_CB0_MSR_PMON_BOX_FILTER_OPC 0xff800000
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#define SNBEP_CBO_EVENT_EXTRA_REG(e, m, i) { \
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.event = (e), \
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.msr = SNBEP_C0_MSR_PMON_BOX_FILTER, \
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.config_mask = (m), \
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.idx = (i) \
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}
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/* SNB-EP PCU register */
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#define SNBEP_PCU_MSR_PMON_CTR0 0xc36
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#define SNBEP_PCU_MSR_PMON_CTL0 0xc30
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#define SNBEP_PCU_MSR_PMON_BOX_CTL 0xc24
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#define SNBEP_PCU_MSR_PMON_BOX_FILTER 0xc34
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#define SNBEP_PCU_MSR_PMON_BOX_FILTER_MASK 0xffffffff
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#define SNBEP_PCU_MSR_CORE_C3_CTR 0x3fc
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#define SNBEP_PCU_MSR_CORE_C6_CTR 0x3fd
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/* IVT event control */
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#define IVT_PMON_BOX_CTL_INT (SNBEP_PMON_BOX_CTL_RST_CTRL | \
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SNBEP_PMON_BOX_CTL_RST_CTRS)
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#define IVT_PMON_RAW_EVENT_MASK (SNBEP_PMON_CTL_EV_SEL_MASK | \
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SNBEP_PMON_CTL_UMASK_MASK | \
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SNBEP_PMON_CTL_EDGE_DET | \
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SNBEP_PMON_CTL_TRESH_MASK)
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/* IVT Ubox */
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#define IVT_U_MSR_PMON_GLOBAL_CTL 0xc00
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#define IVT_U_PMON_GLOBAL_FRZ_ALL (1 << 31)
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#define IVT_U_PMON_GLOBAL_UNFRZ_ALL (1 << 29)
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#define IVT_U_MSR_PMON_RAW_EVENT_MASK \
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(SNBEP_PMON_CTL_EV_SEL_MASK | \
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SNBEP_PMON_CTL_UMASK_MASK | \
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SNBEP_PMON_CTL_EDGE_DET | \
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SNBEP_U_MSR_PMON_CTL_TRESH_MASK)
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/* IVT Cbo */
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#define IVT_CBO_MSR_PMON_RAW_EVENT_MASK (IVT_PMON_RAW_EVENT_MASK | \
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SNBEP_CBO_PMON_CTL_TID_EN)
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#define IVT_CB0_MSR_PMON_BOX_FILTER_TID (0x1fULL << 0)
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#define IVT_CB0_MSR_PMON_BOX_FILTER_LINK (0xfULL << 5)
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#define IVT_CB0_MSR_PMON_BOX_FILTER_STATE (0x3fULL << 17)
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#define IVT_CB0_MSR_PMON_BOX_FILTER_NID (0xffffULL << 32)
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#define IVT_CB0_MSR_PMON_BOX_FILTER_OPC (0x1ffULL << 52)
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#define IVT_CB0_MSR_PMON_BOX_FILTER_C6 (0x1ULL << 61)
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#define IVT_CB0_MSR_PMON_BOX_FILTER_NC (0x1ULL << 62)
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#define IVT_CB0_MSR_PMON_BOX_FILTER_IOSC (0x1ULL << 63)
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/* IVT home agent */
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#define IVT_HA_PCI_PMON_CTL_Q_OCC_RST (1 << 16)
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#define IVT_HA_PCI_PMON_RAW_EVENT_MASK \
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(IVT_PMON_RAW_EVENT_MASK | \
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IVT_HA_PCI_PMON_CTL_Q_OCC_RST)
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/* IVT PCU */
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#define IVT_PCU_MSR_PMON_RAW_EVENT_MASK \
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(SNBEP_PMON_CTL_EV_SEL_MASK | \
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SNBEP_PMON_CTL_EV_SEL_EXT | \
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SNBEP_PCU_MSR_PMON_CTL_OCC_SEL_MASK | \
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SNBEP_PMON_CTL_EDGE_DET | \
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SNBEP_PCU_MSR_PMON_CTL_TRESH_MASK | \
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SNBEP_PCU_MSR_PMON_CTL_OCC_INVERT | \
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SNBEP_PCU_MSR_PMON_CTL_OCC_EDGE_DET)
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/* IVT QPI */
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#define IVT_QPI_PCI_PMON_RAW_EVENT_MASK \
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(IVT_PMON_RAW_EVENT_MASK | \
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SNBEP_PMON_CTL_EV_SEL_EXT)
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/* NHM-EX event control */
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#define NHMEX_PMON_CTL_EV_SEL_MASK 0x000000ff
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#define NHMEX_PMON_CTL_UMASK_MASK 0x0000ff00
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@ -666,3 +508,9 @@ int ivb_uncore_pci_init(void);
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int hsw_uncore_pci_init(void);
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void snb_uncore_cpu_init(void);
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void nhm_uncore_cpu_init(void);
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/* perf_event_intel_uncore_snbep.c */
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int snbep_uncore_pci_init(void);
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void snbep_uncore_cpu_init(void);
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int ivt_uncore_pci_init(void);
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void ivt_uncore_cpu_init(void);
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