x86/mm: Handle LAM on context switch
Linear Address Masking mode for userspace pointers encoded in CR3 bits. The mode is selected per-process and stored in mm_context_t. switch_mm_irqs_off() now respects selected LAM mode and constructs CR3 accordingly. The active LAM mode gets recorded in the tlb_state. Signed-off-by: Kirill A. Shutemov <kirill.shutemov@linux.intel.com> Signed-off-by: Dave Hansen <dave.hansen@linux.intel.com> Acked-by: Peter Zijlstra (Intel) <peterz@infradead.org> Tested-by: Alexander Potapenko <glider@google.com> Link: https://lore.kernel.org/all/20230312112612.31869-5-kirill.shutemov%40linux.intel.com
This commit is contained in:
Kirill A. Shutemov
Dave Hansen
Родитель
6449dcb0ca
Коммит
82721d8b25
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@ -42,6 +42,11 @@ typedef struct {
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unsigned long flags;
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#endif
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#ifdef CONFIG_ADDRESS_MASKING
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/* Active LAM mode: X86_CR3_LAM_U48 or X86_CR3_LAM_U57 or 0 (disabled) */
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unsigned long lam_cr3_mask;
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#endif
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struct mutex lock;
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void __user *vdso; /* vdso base address */
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const struct vdso_image *vdso_image; /* vdso image in use */
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@ -92,6 +92,29 @@ static inline void switch_ldt(struct mm_struct *prev, struct mm_struct *next)
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}
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#endif
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#ifdef CONFIG_ADDRESS_MASKING
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static inline unsigned long mm_lam_cr3_mask(struct mm_struct *mm)
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{
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return mm->context.lam_cr3_mask;
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}
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static inline void dup_lam(struct mm_struct *oldmm, struct mm_struct *mm)
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{
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mm->context.lam_cr3_mask = oldmm->context.lam_cr3_mask;
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}
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#else
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static inline unsigned long mm_lam_cr3_mask(struct mm_struct *mm)
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{
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return 0;
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}
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static inline void dup_lam(struct mm_struct *oldmm, struct mm_struct *mm)
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{
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}
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#endif
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#define enter_lazy_tlb enter_lazy_tlb
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extern void enter_lazy_tlb(struct mm_struct *mm, struct task_struct *tsk);
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@ -169,6 +192,7 @@ static inline int arch_dup_mmap(struct mm_struct *oldmm, struct mm_struct *mm)
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{
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arch_dup_pkeys(oldmm, mm);
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paravirt_arch_dup_mmap(oldmm, mm);
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dup_lam(oldmm, mm);
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return ldt_dup_context(oldmm, mm);
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}
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@ -2,7 +2,7 @@
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#ifndef _ASM_X86_TLBFLUSH_H
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#define _ASM_X86_TLBFLUSH_H
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#include <linux/mm.h>
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#include <linux/mm_types.h>
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#include <linux/sched.h>
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#include <asm/processor.h>
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@ -12,6 +12,7 @@
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#include <asm/invpcid.h>
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#include <asm/pti.h>
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#include <asm/processor-flags.h>
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#include <asm/pgtable.h>
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void __flush_tlb_all(void);
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@ -101,6 +102,16 @@ struct tlb_state {
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*/
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bool invalidate_other;
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#ifdef CONFIG_ADDRESS_MASKING
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/*
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* Active LAM mode.
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*
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* X86_CR3_LAM_U57/U48 shifted right by X86_CR3_LAM_U57_BIT or 0 if LAM
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* disabled.
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*/
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u8 lam;
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#endif
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/*
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* Mask that contains TLB_NR_DYN_ASIDS+1 bits to indicate
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* the corresponding user PCID needs a flush next time we
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@ -357,6 +368,31 @@ static inline bool huge_pmd_needs_flush(pmd_t oldpmd, pmd_t newpmd)
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}
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#define huge_pmd_needs_flush huge_pmd_needs_flush
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#ifdef CONFIG_ADDRESS_MASKING
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static inline u64 tlbstate_lam_cr3_mask(void)
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{
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u64 lam = this_cpu_read(cpu_tlbstate.lam);
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return lam << X86_CR3_LAM_U57_BIT;
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}
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static inline void set_tlbstate_lam_mode(struct mm_struct *mm)
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{
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this_cpu_write(cpu_tlbstate.lam,
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mm->context.lam_cr3_mask >> X86_CR3_LAM_U57_BIT);
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}
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#else
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static inline u64 tlbstate_lam_cr3_mask(void)
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{
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return 0;
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}
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static inline void set_tlbstate_lam_mode(struct mm_struct *mm)
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{
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}
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#endif
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#endif /* !MODULE */
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static inline void __native_tlb_flush_global(unsigned long cr4)
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@ -154,26 +154,30 @@ static inline u16 user_pcid(u16 asid)
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return ret;
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}
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static inline unsigned long build_cr3(pgd_t *pgd, u16 asid)
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static inline unsigned long build_cr3(pgd_t *pgd, u16 asid, unsigned long lam)
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{
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unsigned long cr3 = __sme_pa(pgd) | lam;
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if (static_cpu_has(X86_FEATURE_PCID)) {
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return __sme_pa(pgd) | kern_pcid(asid);
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VM_WARN_ON_ONCE(asid > MAX_ASID_AVAILABLE);
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cr3 |= kern_pcid(asid);
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} else {
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VM_WARN_ON_ONCE(asid != 0);
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return __sme_pa(pgd);
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}
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return cr3;
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}
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static inline unsigned long build_cr3_noflush(pgd_t *pgd, u16 asid)
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static inline unsigned long build_cr3_noflush(pgd_t *pgd, u16 asid,
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unsigned long lam)
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{
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VM_WARN_ON_ONCE(asid > MAX_ASID_AVAILABLE);
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/*
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* Use boot_cpu_has() instead of this_cpu_has() as this function
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* might be called during early boot. This should work even after
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* boot because all CPU's the have same capabilities:
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*/
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VM_WARN_ON_ONCE(!boot_cpu_has(X86_FEATURE_PCID));
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return __sme_pa(pgd) | kern_pcid(asid) | CR3_NOFLUSH;
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return build_cr3(pgd, asid, lam) | CR3_NOFLUSH;
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}
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/*
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@ -274,15 +278,16 @@ static inline void invalidate_user_asid(u16 asid)
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(unsigned long *)this_cpu_ptr(&cpu_tlbstate.user_pcid_flush_mask));
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}
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static void load_new_mm_cr3(pgd_t *pgdir, u16 new_asid, bool need_flush)
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static void load_new_mm_cr3(pgd_t *pgdir, u16 new_asid, unsigned long lam,
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bool need_flush)
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{
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unsigned long new_mm_cr3;
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if (need_flush) {
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invalidate_user_asid(new_asid);
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new_mm_cr3 = build_cr3(pgdir, new_asid);
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new_mm_cr3 = build_cr3(pgdir, new_asid, lam);
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} else {
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new_mm_cr3 = build_cr3_noflush(pgdir, new_asid);
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new_mm_cr3 = build_cr3_noflush(pgdir, new_asid, lam);
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}
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/*
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@ -491,6 +496,7 @@ void switch_mm_irqs_off(struct mm_struct *prev, struct mm_struct *next,
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{
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struct mm_struct *real_prev = this_cpu_read(cpu_tlbstate.loaded_mm);
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u16 prev_asid = this_cpu_read(cpu_tlbstate.loaded_mm_asid);
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unsigned long new_lam = mm_lam_cr3_mask(next);
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bool was_lazy = this_cpu_read(cpu_tlbstate_shared.is_lazy);
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unsigned cpu = smp_processor_id();
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u64 next_tlb_gen;
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@ -520,7 +526,8 @@ void switch_mm_irqs_off(struct mm_struct *prev, struct mm_struct *next,
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* isn't free.
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*/
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#ifdef CONFIG_DEBUG_VM
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if (WARN_ON_ONCE(__read_cr3() != build_cr3(real_prev->pgd, prev_asid))) {
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if (WARN_ON_ONCE(__read_cr3() != build_cr3(real_prev->pgd, prev_asid,
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tlbstate_lam_cr3_mask()))) {
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/*
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* If we were to BUG here, we'd be very likely to kill
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* the system so hard that we don't see the call trace.
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@ -552,9 +559,15 @@ void switch_mm_irqs_off(struct mm_struct *prev, struct mm_struct *next,
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* instruction.
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*/
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if (real_prev == next) {
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/* Not actually switching mm's */
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VM_WARN_ON(this_cpu_read(cpu_tlbstate.ctxs[prev_asid].ctx_id) !=
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next->context.ctx_id);
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/*
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* If this races with another thread that enables lam, 'new_lam'
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* might not match tlbstate_lam_cr3_mask().
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*/
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/*
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* Even in lazy TLB mode, the CPU should stay set in the
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* mm_cpumask. The TLB shootdown code can figure out from
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@ -622,15 +635,16 @@ void switch_mm_irqs_off(struct mm_struct *prev, struct mm_struct *next,
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barrier();
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}
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set_tlbstate_lam_mode(next);
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if (need_flush) {
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this_cpu_write(cpu_tlbstate.ctxs[new_asid].ctx_id, next->context.ctx_id);
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this_cpu_write(cpu_tlbstate.ctxs[new_asid].tlb_gen, next_tlb_gen);
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load_new_mm_cr3(next->pgd, new_asid, true);
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load_new_mm_cr3(next->pgd, new_asid, new_lam, true);
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trace_tlb_flush(TLB_FLUSH_ON_TASK_SWITCH, TLB_FLUSH_ALL);
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} else {
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/* The new ASID is already up to date. */
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load_new_mm_cr3(next->pgd, new_asid, false);
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load_new_mm_cr3(next->pgd, new_asid, new_lam, false);
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trace_tlb_flush(TLB_FLUSH_ON_TASK_SWITCH, 0);
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}
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@ -691,6 +705,10 @@ void initialize_tlbstate_and_flush(void)
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/* Assert that CR3 already references the right mm. */
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WARN_ON((cr3 & CR3_ADDR_MASK) != __pa(mm->pgd));
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/* LAM expected to be disabled */
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WARN_ON(cr3 & (X86_CR3_LAM_U48 | X86_CR3_LAM_U57));
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WARN_ON(mm_lam_cr3_mask(mm));
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/*
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* Assert that CR4.PCIDE is set if needed. (CR4.PCIDE initialization
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* doesn't work like other CR4 bits because it can only be set from
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@ -699,8 +717,8 @@ void initialize_tlbstate_and_flush(void)
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WARN_ON(boot_cpu_has(X86_FEATURE_PCID) &&
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!(cr4_read_shadow() & X86_CR4_PCIDE));
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/* Force ASID 0 and force a TLB flush. */
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write_cr3(build_cr3(mm->pgd, 0));
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/* Disable LAM, force ASID 0 and force a TLB flush. */
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write_cr3(build_cr3(mm->pgd, 0, 0));
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/* Reinitialize tlbstate. */
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this_cpu_write(cpu_tlbstate.last_user_mm_spec, LAST_USER_MM_INIT);
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@ -708,6 +726,7 @@ void initialize_tlbstate_and_flush(void)
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this_cpu_write(cpu_tlbstate.next_asid, 1);
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this_cpu_write(cpu_tlbstate.ctxs[0].ctx_id, mm->context.ctx_id);
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this_cpu_write(cpu_tlbstate.ctxs[0].tlb_gen, tlb_gen);
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set_tlbstate_lam_mode(mm);
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for (i = 1; i < TLB_NR_DYN_ASIDS; i++)
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this_cpu_write(cpu_tlbstate.ctxs[i].ctx_id, 0);
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@ -1071,8 +1090,10 @@ void flush_tlb_kernel_range(unsigned long start, unsigned long end)
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*/
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unsigned long __get_current_cr3_fast(void)
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{
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unsigned long cr3 = build_cr3(this_cpu_read(cpu_tlbstate.loaded_mm)->pgd,
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this_cpu_read(cpu_tlbstate.loaded_mm_asid));
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unsigned long cr3 =
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build_cr3(this_cpu_read(cpu_tlbstate.loaded_mm)->pgd,
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this_cpu_read(cpu_tlbstate.loaded_mm_asid),
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tlbstate_lam_cr3_mask());
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/* For now, be very restrictive about when this can be called. */
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VM_WARN_ON(in_nmi() || preemptible());
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