ARM: dts: imx6: Add support for Phytec phyBOARD i.MX6UL Segin
The Phytec phyBOARD Segin is i.MX6 based SBC, available with either an i.MX6UL or i.MX6ULL SOM and various add-on boards. The following adds support for the "Full Featured" version of the Segin, which is provided with the i.MX6UL SOM and the PEB-EVAL-01 evaluation module. Its hardware specifications are: * 512MB DDR3 memory * 512MB NAND flash * Dual 10/100 Ethernet * USB Host and USB OTG * RS232 * MicroSD external storage * Audio, RS232, I2C, SPI, CAN headers * Further I/O options via A/V and Expansion headers Signed-off-by: Martyn Welch <martyn.welch@collabora.com> Reviewed-by: Fabio Estevam <festevam@gmail.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
This commit is contained in:
Martyn Welch
Shawn Guo
Родитель
d2b91ab148
Коммит
82ae9038dd
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@ -564,6 +564,7 @@ dtb-$(CONFIG_SOC_IMX6UL) += \
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imx6ul-opos6uldev.dtb \
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imx6ul-pico-hobbit.dtb \
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imx6ul-pico-pi.dtb \
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imx6ul-phytec-phyboard-segin-full.dtb \
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imx6ul-tx6ul-0010.dtb \
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imx6ul-tx6ul-0011.dtb \
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imx6ul-tx6ul-mainboard.dtb \
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@ -0,0 +1,148 @@
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// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (C) 2016 PHYTEC Messtechnik GmbH
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* Author: Christian Hemp <c.hemp@phytec.de>
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*/
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#include <dt-bindings/gpio/gpio.h>
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#include <dt-bindings/interrupt-controller/irq.h>
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#include <dt-bindings/pwm/pwm.h>
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#include "imx6ul.dtsi"
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/ {
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model = "Phytec phyCORE i.MX6 UltraLite";
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compatible = "phytec,imx6ul-pcl063", "fsl,imx6ul";
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chosen {
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stdout-path = &uart1;
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};
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/*
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* Set the minimum memory size here and
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* let the bootloader set the real size.
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*/
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memory {
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device_type = "memory";
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reg = <0x80000000 0x8000000>;
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};
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gpio_leds_som: leds {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_gpioleds_som>;
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compatible = "gpio-leds";
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led_green {
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label = "phycore:green";
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gpios = <&gpio5 4 GPIO_ACTIVE_HIGH>;
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linux,default-trigger = "heartbeat";
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};
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};
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};
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&fec1 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_enet1>;
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phy-mode = "rmii";
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phy-handle = <ðphy0>;
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status = "okay";
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mdio: mdio {
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#address-cells = <1>;
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#size-cells = <0>;
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ethphy0: ethernet-phy@1 {
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reg = <1>;
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interrupt-parent = <&gpio1>;
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interrupts = <2 IRQ_TYPE_LEVEL_LOW>;
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micrel,led-mode = <1>;
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clocks = <&clks IMX6UL_CLK_ENET_REF>;
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clock-names = "rmii-ref";
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};
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};
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};
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&gpmi {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_gpmi_nand>;
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nand-on-flash-bbt;
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status = "okay";
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};
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&i2c1 {
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pinctrl-names = "default";
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pinctrl-0 =<&pinctrl_i2c1>;
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clock-frequency = <100000>;
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status = "okay";
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eeprom@52 {
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compatible = "catalyst,24c32", "atmel,24c32";
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reg = <0x52>;
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};
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};
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&snvs_poweroff {
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status = "okay";
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};
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&uart1 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_uart1>;
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status = "okay";
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};
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&iomuxc {
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pinctrl_enet1: enet1grp {
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fsl,pins = <
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MX6UL_PAD_GPIO1_IO07__ENET1_MDC 0x1b0b0
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MX6UL_PAD_GPIO1_IO06__ENET1_MDIO 0x1b0b0
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MX6UL_PAD_ENET1_RX_EN__ENET1_RX_EN 0x1b0b0
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MX6UL_PAD_ENET1_RX_ER__ENET1_RX_ER 0x1b0b0
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MX6UL_PAD_ENET1_RX_DATA0__ENET1_RDATA00 0x1b0b0
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MX6UL_PAD_ENET1_RX_DATA1__ENET1_RDATA01 0x1b0b0
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MX6UL_PAD_ENET1_TX_EN__ENET1_TX_EN 0x1b0b0
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MX6UL_PAD_ENET1_TX_DATA0__ENET1_TDATA00 0x1b0b0
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MX6UL_PAD_ENET1_TX_DATA1__ENET1_TDATA01 0x1b0b0
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MX6UL_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 0x4001b031
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MX6UL_PAD_GPIO1_IO02__GPIO1_IO02 0x17059
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>;
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};
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pinctrl_gpioleds_som: gpioledssomgrp {
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fsl,pins = <MX6UL_PAD_SNVS_TAMPER4__GPIO5_IO04 0x0b0b0>;
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};
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pinctrl_gpmi_nand: gpminandgrp {
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fsl,pins = <
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MX6UL_PAD_NAND_CLE__RAWNAND_CLE 0x0b0b1
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MX6UL_PAD_NAND_ALE__RAWNAND_ALE 0x0b0b1
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MX6UL_PAD_NAND_WP_B__RAWNAND_WP_B 0x0b0b1
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MX6UL_PAD_NAND_READY_B__RAWNAND_READY_B 0x0b000
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MX6UL_PAD_NAND_CE0_B__RAWNAND_CE0_B 0x0b0b1
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MX6UL_PAD_NAND_RE_B__RAWNAND_RE_B 0x0b0b1
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MX6UL_PAD_NAND_WE_B__RAWNAND_WE_B 0x0b0b1
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MX6UL_PAD_NAND_DATA00__RAWNAND_DATA00 0x0b0b1
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MX6UL_PAD_NAND_DATA01__RAWNAND_DATA01 0x0b0b1
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MX6UL_PAD_NAND_DATA02__RAWNAND_DATA02 0x0b0b1
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MX6UL_PAD_NAND_DATA03__RAWNAND_DATA03 0x0b0b1
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MX6UL_PAD_NAND_DATA04__RAWNAND_DATA04 0x0b0b1
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MX6UL_PAD_NAND_DATA05__RAWNAND_DATA05 0x0b0b1
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MX6UL_PAD_NAND_DATA06__RAWNAND_DATA06 0x0b0b1
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MX6UL_PAD_NAND_DATA07__RAWNAND_DATA07 0x0b0b1
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>;
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};
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pinctrl_i2c1: i2cgrp {
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fsl,pins = <
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MX6UL_PAD_UART4_TX_DATA__I2C1_SCL 0x4001b8b0
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MX6UL_PAD_UART4_RX_DATA__I2C1_SDA 0x4001b8b0
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>;
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};
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pinctrl_uart1: uart1grp {
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fsl,pins = <
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MX6UL_PAD_UART1_TX_DATA__UART1_DCE_TX 0x1b0b1
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MX6UL_PAD_UART1_RX_DATA__UART1_DCE_RX 0x1b0b1
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>;
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};
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};
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@ -0,0 +1,55 @@
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// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (C) 2016 PHYTEC Messtechnik
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* Author: Christian Hemp <c.hemp@phytec.de>
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*/
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#include <dt-bindings/input/input.h>
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/ {
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gpio_keys: gpio-keys {
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compatible = "gpio-key";
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_gpio_keys>;
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status = "disabled";
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power {
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label = "Power Button";
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gpios = <&gpio5 0 GPIO_ACTIVE_LOW>;
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linux,code = <KEY_POWER>;
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wakeup-source;
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};
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};
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user_leds: leds {
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compatible = "gpio-leds";
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_user_leds>;
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status = "disabled";
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led_yellow {
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gpios = <&gpio1 1 GPIO_ACTIVE_HIGH>;
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linux,default-trigger = "default-on";
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};
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led_red {
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gpios = <&gpio1 10 GPIO_ACTIVE_HIGH>;
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linux,default-trigger = "default-on";
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};
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};
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};
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&iomuxc {
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pinctrl_gpio_keys: gpio_keysgrp {
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fsl,pins = <
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MX6UL_PAD_SNVS_TAMPER0__GPIO5_IO00 0x79
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>;
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};
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pinctrl_user_leds: user_ledsgrp {
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fsl,pins = <
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MX6UL_PAD_JTAG_MOD__GPIO1_IO10 0x79
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MX6UL_PAD_GPIO1_IO01__GPIO1_IO01 0x79
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>;
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};
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};
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@ -0,0 +1,89 @@
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// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (C) 2016 PHYTEC Messtechnik GmbH
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* Author: Christian Hemp <c.hemp@phytec.de>
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*/
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/dts-v1/;
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#include "imx6ul-phytec-pcl063.dtsi"
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#include "imx6ul-phytec-phyboard-segin.dtsi"
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#include "imx6ul-phytec-peb-eval-01.dtsi"
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/ {
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model = "Phytec phyBOARD-Segin i.MX6 UltraLite Full Featured";
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compatible = "phytec,imx6ul-pbacd10", "phytec,imx6ul-pcl063", "fsl,imx6ul";
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};
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&adc1 {
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status = "okay";
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};
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&can1 {
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status = "okay";
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};
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&tlv320 {
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status = "okay";
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};
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&ecspi3 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_ecspi3>;
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cs-gpios = <&gpio1 20 GPIO_ACTIVE_HIGH>;
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status = "okay";
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};
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&fec2 {
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status = "okay";
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};
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&i2c_rtc {
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status = "okay";
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};
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®_can1_en {
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status = "okay";
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};
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®_sound_1v8 {
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status = "okay";
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};
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®_sound_3v3 {
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status = "okay";
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};
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&sai2 {
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status = "okay";
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};
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&sound {
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status = "okay";
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};
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&uart5 {
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status = "okay";
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};
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&usbotg1 {
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status = "okay";
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};
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&usbotg2 {
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status = "okay";
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};
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&usdhc1 {
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status = "okay";
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};
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&iomuxc {
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pinctrl_ecspi3: ecspi3grp {
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fsl,pins = <
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MX6UL_PAD_UART2_RTS_B__ECSPI3_MISO 0x10b0
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MX6UL_PAD_UART2_CTS_B__ECSPI3_MOSI 0x10b0
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MX6UL_PAD_UART2_RX_DATA__ECSPI3_SCLK 0x10b0
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MX6UL_PAD_UART2_TX_DATA__GPIO1_IO20 0x10b0
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>;
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};
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};
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@ -0,0 +1,329 @@
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// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (C) 2016 PHYTEC Messtechnik GmbH
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* Author: Christian Hemp <c.hemp@phytec.de>
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*/
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/ {
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model = "Phytec phyBOARD-Segin i.MX6 UltraLite";
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compatible = "phytec,imx6ul-pbacd-10", "phytec,imx6ul-pcl063", "fsl,imx6ul";
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aliases {
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rtc0 = &i2c_rtc;
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rtc1 = &snvs_rtc;
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};
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reg_sound_1v8: regulator-1v8 {
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compatible = "regulator-fixed";
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regulator-name = "i2s-audio-1v8";
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regulator-min-microvolt = <1800000>;
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regulator-max-microvolt = <1800000>;
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status = "disabled";
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};
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reg_sound_3v3: regulator-3v3 {
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compatible = "regulator-fixed";
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regulator-name = "i2s-audio-3v3";
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regulator-min-microvolt = <3300000>;
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regulator-max-microvolt = <3300000>;
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status = "disabled";
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};
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reg_can1_en: regulator-can1 {
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compatible = "regulator-fixed";
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pinctrl-names = "default";
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pinctrl-0 = <&princtrl_flexcan1_en>;
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regulator-name = "Can";
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regulator-min-microvolt = <3300000>;
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regulator-max-microvolt = <3300000>;
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gpio = <&gpio5 2 GPIO_ACTIVE_HIGH>;
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enable-active-high;
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status = "disabled";
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};
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reg_adc1_vref_3v3: regulator-vref-3v3 {
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compatible = "regulator-fixed";
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regulator-name = "vref-3v3";
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regulator-min-microvolt = <3300000>;
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regulator-max-microvolt = <3300000>;
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};
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sound: sound {
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compatible = "simple-audio-card";
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simple-audio-card,name = "phyBOARD-Segin-TLV320AIC3007";
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simple-audio-card,format = "i2s";
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simple-audio-card,bitclock-master = <&dailink_master>;
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simple-audio-card,frame-master = <&dailink_master>;
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simple-audio-card,widgets =
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"Line", "Line In",
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"Line", "Line Out",
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"Speaker", "Speaker";
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simple-audio-card,routing =
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"Line Out", "LLOUT",
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"Line Out", "RLOUT",
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"Speaker", "SPOP",
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"Speaker", "SPOM",
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"LINE1L", "Line In",
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"LINE1R", "Line In";
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status = "disabled";
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simple-audio-card,cpu {
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sound-dai = <&sai2>;
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};
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dailink_master: simple-audio-card,codec {
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sound-dai = <&tlv320>;
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clocks = <&clks IMX6UL_CLK_SAI2>;
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};
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};
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};
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&adc1 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_adc1>;
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vref-supply = <®_adc1_vref_3v3>;
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/*
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* driver can not separate a specific channel so we request 4 channels
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* here - we need only the fourth channel
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*/
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num-channels = <4>;
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status = "disabled";
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};
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&can1 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_flexcan1>;
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xceiver-supply = <®_can1_en>;
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status = "disabled";
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};
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&clks {
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assigned-clocks = <&clks IMX6UL_CLK_PLL4_AUDIO_DIV>;
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assigned-clock-rates = <786432000>;
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};
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&fec2 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_enet2>;
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phy-mode = "rmii";
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phy-handle = <ðphy1>;
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status = "disabled";
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};
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&i2c1 {
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tlv320: codec@18 {
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compatible = "ti,tlv320aic3007";
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#sound-dai-cells = <0>;
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reg = <0x18>;
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AVDD-supply = <®_sound_3v3>;
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IOVDD-supply = <®_sound_3v3>;
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DRVDD-supply = <®_sound_3v3>;
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DVDD-supply = <®_sound_1v8>;
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status = "disabled";
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};
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stmpe: touchscreen@44 {
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compatible = "st,stmpe811";
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reg = <0x44>;
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interrupts = <3 IRQ_TYPE_LEVEL_LOW>;
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interrupt-parent = <&gpio5>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_stmpe>;
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status = "disabled";
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touchscreen {
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compatible = "st,stmpe-ts";
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st,sample-time = <4>;
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st,mod-12b = <1>;
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st,ref-sel = <0>;
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st,adc-freq = <1>;
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st,ave-ctrl = <1>;
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st,touch-det-delay = <2>;
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st,settling = <2>;
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st,fraction-z = <7>;
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st,i-drive = <1>;
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touchscreen-inverted-x = <1>;
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touchscreen-inverted-y = <1>;
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||||
};
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||||
};
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i2c_rtc: rtc@68 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_rtc_int>;
|
||||
compatible = "microcrystal,rv4162";
|
||||
reg = <0x68>;
|
||||
interrupt-parent = <&gpio5>;
|
||||
interrupts = <1 IRQ_TYPE_LEVEL_LOW>;
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
|
||||
&mdio {
|
||||
ethphy1: ethernet-phy@2 {
|
||||
reg = <2>;
|
||||
micrel,led-mode = <1>;
|
||||
clocks = <&clks IMX6UL_CLK_ENET2_REF>;
|
||||
clock-names = "rmii-ref";
|
||||
};
|
||||
};
|
||||
|
||||
&pwm3 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_pwm3>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&sai2 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_sai2>;
|
||||
assigned-clocks = <&clks IMX6UL_CLK_SAI2_SEL>,
|
||||
<&clks IMX6UL_CLK_SAI2>;
|
||||
assigned-clock-parents = <&clks IMX6UL_CLK_PLL4_AUDIO_DIV>;
|
||||
assigned-clock-rates = <0>, <19200000>;
|
||||
fsl,sai-mclk-direction-output;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&uart5 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_uart5>;
|
||||
uart-has-rtscts;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&usbotg1 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_usb_otg1_id>;
|
||||
dr_mode = "otg";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&usbotg2 {
|
||||
dr_mode = "host";
|
||||
disable-over-current;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&usdhc1 {
|
||||
pinctrl-names = "default", "state_100mhz", "state_200mhz";
|
||||
pinctrl-0 = <&pinctrl_usdhc1>;
|
||||
pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
|
||||
pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
|
||||
cd-gpios = <&gpio1 19 GPIO_ACTIVE_LOW>;
|
||||
no-1-8-v;
|
||||
keep-power-in-suspend;
|
||||
wakeup-source;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&iomuxc {
|
||||
pinctrl_adc1: adc1grp {
|
||||
fsl,pins = <
|
||||
MX6UL_PAD_GPIO1_IO03__GPIO1_IO03 0xb0
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_enet2: enet2grp {
|
||||
fsl,pins = <
|
||||
MX6UL_PAD_ENET2_RX_EN__ENET2_RX_EN 0x1b0b0
|
||||
MX6UL_PAD_ENET2_RX_ER__ENET2_RX_ER 0x1b0b0
|
||||
MX6UL_PAD_ENET2_RX_DATA0__ENET2_RDATA00 0x1b0b0
|
||||
MX6UL_PAD_ENET2_RX_DATA1__ENET2_RDATA01 0x1b0b0
|
||||
MX6UL_PAD_ENET2_TX_EN__ENET2_TX_EN 0x1b0b0
|
||||
MX6UL_PAD_ENET2_TX_DATA0__ENET2_TDATA00 0x1b0b0
|
||||
MX6UL_PAD_ENET2_TX_DATA1__ENET2_TDATA01 0x1b0b0
|
||||
MX6UL_PAD_ENET2_TX_CLK__ENET2_REF_CLK2 0x4001b031
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_flexcan1: flexcan1 {
|
||||
fsl,pins = <
|
||||
MX6UL_PAD_UART3_CTS_B__FLEXCAN1_TX 0x0b0b0
|
||||
MX6UL_PAD_UART3_RTS_B__FLEXCAN1_RX 0x0b0b0
|
||||
>;
|
||||
};
|
||||
|
||||
princtrl_flexcan1_en: flexcan1engrp {
|
||||
fsl,pins = <
|
||||
MX6UL_PAD_SNVS_TAMPER2__GPIO5_IO02 0x17059
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_pwm3: pwm3grp {
|
||||
fsl,pins = <
|
||||
MX6UL_PAD_GPIO1_IO04__PWM3_OUT 0x0b0b0
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_rtc_int: rtcintgrp {
|
||||
fsl,pins = <
|
||||
MX6UL_PAD_SNVS_TAMPER1__GPIO5_IO01 0x17059
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_sai2: sai2grp {
|
||||
fsl,pins = <
|
||||
MX6UL_PAD_JTAG_TDI__SAI2_TX_BCLK 0x17088
|
||||
MX6UL_PAD_JTAG_TDO__SAI2_TX_SYNC 0x17088
|
||||
MX6UL_PAD_JTAG_TRST_B__SAI2_TX_DATA 0x11088
|
||||
MX6UL_PAD_JTAG_TCK__SAI2_RX_DATA 0x11088
|
||||
MX6UL_PAD_JTAG_TMS__SAI2_MCLK 0x17088
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_stmpe: stmpegrp {
|
||||
fsl,pins = <
|
||||
MX6UL_PAD_SNVS_TAMPER3__GPIO5_IO03 0x17059
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_uart5: uart5grp {
|
||||
fsl,pins = <
|
||||
MX6UL_PAD_UART5_TX_DATA__UART5_DCE_TX 0x1b0b1
|
||||
MX6UL_PAD_UART5_RX_DATA__UART5_DCE_RX 0x1b0b1
|
||||
MX6UL_PAD_GPIO1_IO08__UART5_DCE_RTS 0x1b0b1
|
||||
MX6UL_PAD_GPIO1_IO09__UART5_DCE_CTS 0x1b0b1
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_usb_otg1_id: usbotg1idgrp {
|
||||
fsl,pins = <
|
||||
MX6UL_PAD_GPIO1_IO00__ANATOP_OTG1_ID 0x17059
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_usdhc1: usdhc1grp {
|
||||
fsl,pins = <
|
||||
MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x17059
|
||||
MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x10059
|
||||
MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x17059
|
||||
MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x17059
|
||||
MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x17059
|
||||
MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x17059
|
||||
MX6UL_PAD_UART1_RTS_B__GPIO1_IO19 0x17059
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_usdhc1_100mhz: usdhc1grp100mhz {
|
||||
fsl,pins = <
|
||||
MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x170b9
|
||||
MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x100b9
|
||||
MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170b9
|
||||
MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170b9
|
||||
MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170b9
|
||||
MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x170b9
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_usdhc1_200mhz: usdhc1grp200mhz {
|
||||
fsl,pins = <
|
||||
MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x170f9
|
||||
MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x100f9
|
||||
MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170f9
|
||||
MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170f9
|
||||
MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170f9
|
||||
MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x170f9
|
||||
>;
|
||||
};
|
||||
};
|
||||
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