drm/i915: Implement color management on bdw/skl/bxt/kbl
Patch based on a previous series by Shashank Sharma.
v2: Do not read GAMMA_MODE register to figure what mode we're in
v3: Program PREC_PAL_GC_MAX to clamp pixel values > 1.0
Add documentation on how the Broadcast RGB property is affected by CTM
v4: Update contributors
v5: Refactor degamma/gamma LUTs load into a single function
v6: Fix missing intel_crtc variable (bisect issue)
v7: Fix & simplify limited range matrix multiplication (Matt Roper's
comment)
Signed-off-by: Shashank Sharma <shashank.sharma@intel.com>
Signed-off-by: Kumar, Kiran S <kiran.s.kumar@intel.com>
Signed-off-by: Kausal Malladi <kausalmalladi@gmail.com>
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Acknowledged-by: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/1458125837-2576-4-git-send-email-lionel.g.landwerlin@intel.com
This commit is contained in:
Lionel Landwerlin
Matt Roper
Родитель
05dc698c2e
Коммит
82cf435b31
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@ -2153,7 +2153,11 @@ void intel_crt_init(struct drm_device *dev)
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<td valign="top" >ENUM</td>
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<td valign="top" >{ "Automatic", "Full", "Limited 16:235" }</td>
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<td valign="top" >Connector</td>
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<td valign="top" >TBD</td>
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<td valign="top" >When this property is set to Limited 16:235
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and CTM is set, the hardware will be programmed with the
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result of the multiplication of CTM by the limited range
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matrix to ensure the pixels normaly in the range 0..1.0 are
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remapped to the range 16/255..235/255.</td>
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</tr>
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<tr>
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<td valign="top" >“audio”</td>
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@ -66,6 +66,9 @@ static struct drm_driver driver;
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#define IVB_CURSOR_OFFSETS \
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.cursor_offsets = { CURSOR_A_OFFSET, IVB_CURSOR_B_OFFSET, IVB_CURSOR_C_OFFSET }
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#define BDW_COLORS \
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.color = { .degamma_lut_size = 512, .gamma_lut_size = 512 }
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static const struct intel_device_info intel_i830_info = {
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.gen = 2, .is_mobile = 1, .cursor_needs_physical = 1, .num_pipes = 2,
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.has_overlay = 1, .overlay_needs_physical = 1,
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@ -288,24 +291,28 @@ static const struct intel_device_info intel_haswell_m_info = {
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.is_mobile = 1,
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};
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#define BDW_FEATURES \
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HSW_FEATURES, \
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BDW_COLORS
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static const struct intel_device_info intel_broadwell_d_info = {
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HSW_FEATURES,
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BDW_FEATURES,
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.gen = 8,
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};
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static const struct intel_device_info intel_broadwell_m_info = {
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HSW_FEATURES,
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BDW_FEATURES,
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.gen = 8, .is_mobile = 1,
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};
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static const struct intel_device_info intel_broadwell_gt3d_info = {
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HSW_FEATURES,
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BDW_FEATURES,
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.gen = 8,
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.ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING | BSD2_RING,
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};
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static const struct intel_device_info intel_broadwell_gt3m_info = {
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HSW_FEATURES,
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BDW_FEATURES,
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.gen = 8, .is_mobile = 1,
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.ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING | BSD2_RING,
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};
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@ -321,13 +328,13 @@ static const struct intel_device_info intel_cherryview_info = {
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};
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static const struct intel_device_info intel_skylake_info = {
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HSW_FEATURES,
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BDW_FEATURES,
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.is_skylake = 1,
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.gen = 9,
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};
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static const struct intel_device_info intel_skylake_gt3_info = {
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HSW_FEATURES,
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BDW_FEATURES,
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.is_skylake = 1,
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.gen = 9,
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.ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING | BSD2_RING,
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@ -345,17 +352,18 @@ static const struct intel_device_info intel_broxton_info = {
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.has_fbc = 1,
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GEN_DEFAULT_PIPEOFFSETS,
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IVB_CURSOR_OFFSETS,
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BDW_COLORS,
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};
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static const struct intel_device_info intel_kabylake_info = {
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HSW_FEATURES,
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BDW_FEATURES,
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.is_preliminary = 1,
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.is_kabylake = 1,
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.gen = 9,
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};
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static const struct intel_device_info intel_kabylake_gt3_info = {
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HSW_FEATURES,
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BDW_FEATURES,
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.is_preliminary = 1,
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.is_kabylake = 1,
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.gen = 9,
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@ -630,6 +630,7 @@ struct drm_i915_display_funcs {
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/* display clock increase/decrease */
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/* pll clock increase/decrease */
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void (*load_csc_matrix)(struct drm_crtc *crtc);
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void (*load_luts)(struct drm_crtc *crtc);
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};
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@ -781,6 +782,11 @@ struct intel_device_info {
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u8 has_slice_pg:1;
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u8 has_subslice_pg:1;
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u8 has_eu_pg:1;
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struct color_luts {
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u16 degamma_lut_size;
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u16 gamma_lut_size;
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} color;
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};
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#undef DEFINE_FLAG
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@ -7663,6 +7663,28 @@ enum skl_disp_power_wells {
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#define PIPE_CSC_POSTOFF_ME(pipe) _MMIO_PIPE(pipe, _PIPE_A_CSC_POSTOFF_ME, _PIPE_B_CSC_POSTOFF_ME)
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#define PIPE_CSC_POSTOFF_LO(pipe) _MMIO_PIPE(pipe, _PIPE_A_CSC_POSTOFF_LO, _PIPE_B_CSC_POSTOFF_LO)
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/* pipe degamma/gamma LUTs on IVB+ */
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#define _PAL_PREC_INDEX_A 0x4A400
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#define _PAL_PREC_INDEX_B 0x4AC00
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#define _PAL_PREC_INDEX_C 0x4B400
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#define PAL_PREC_10_12_BIT (0 << 31)
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#define PAL_PREC_SPLIT_MODE (1 << 31)
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#define PAL_PREC_AUTO_INCREMENT (1 << 15)
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#define _PAL_PREC_DATA_A 0x4A404
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#define _PAL_PREC_DATA_B 0x4AC04
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#define _PAL_PREC_DATA_C 0x4B404
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#define _PAL_PREC_GC_MAX_A 0x4A410
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#define _PAL_PREC_GC_MAX_B 0x4AC10
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#define _PAL_PREC_GC_MAX_C 0x4B410
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#define _PAL_PREC_EXT_GC_MAX_A 0x4A420
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#define _PAL_PREC_EXT_GC_MAX_B 0x4AC20
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#define _PAL_PREC_EXT_GC_MAX_C 0x4B420
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#define PREC_PAL_INDEX(pipe) _MMIO_PIPE(pipe, _PAL_PREC_INDEX_A, _PAL_PREC_INDEX_B)
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#define PREC_PAL_DATA(pipe) _MMIO_PIPE(pipe, _PAL_PREC_DATA_A, _PAL_PREC_DATA_B)
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#define PREC_PAL_GC_MAX(pipe, i) _MMIO(_PIPE(pipe, _PAL_PREC_GC_MAX_A, _PAL_PREC_GC_MAX_B) + (i) * 4)
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#define PREC_PAL_EXT_GC_MAX(pipe, i) _MMIO(_PIPE(pipe, _PAL_PREC_EXT_GC_MAX_A, _PAL_PREC_EXT_GC_MAX_B) + (i) * 4)
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/* MIPI DSI registers */
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#define _MIPI_PORT(port, a, c) _PORT3(port, a, 0, c) /* ports A and C only */
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@ -24,39 +24,155 @@
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#include "intel_drv.h"
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#define CTM_COEFF_SIGN (1ULL << 63)
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#define CTM_COEFF_1_0 (1ULL << 32)
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#define CTM_COEFF_2_0 (CTM_COEFF_1_0 << 1)
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#define CTM_COEFF_4_0 (CTM_COEFF_2_0 << 1)
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#define CTM_COEFF_0_5 (CTM_COEFF_1_0 >> 1)
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#define CTM_COEFF_0_25 (CTM_COEFF_0_5 >> 1)
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#define CTM_COEFF_0_125 (CTM_COEFF_0_25 >> 1)
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#define CTM_COEFF_LIMITED_RANGE ((235ULL - 16ULL) * CTM_COEFF_1_0 / 255)
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#define CTM_COEFF_NEGATIVE(coeff) (((coeff) & CTM_COEFF_SIGN) != 0)
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#define CTM_COEFF_ABS(coeff) ((coeff) & (CTM_COEFF_SIGN - 1))
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#define LEGACY_LUT_LENGTH (sizeof(struct drm_color_lut) * 256)
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/*
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* Set up the pipe CSC unit.
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* Extract the CSC coefficient from a CTM coefficient (in U32.32 fixed point
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* format). This macro takes the coefficient we want transformed and the
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* number of fractional bits.
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*
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* Currently only full range RGB to limited range RGB conversion
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* is supported, but eventually this should handle various
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* RGB<->YCbCr scenarios as well.
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* We only have a 9 bits precision window which slides depending on the value
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* of the CTM coefficient and we write the value from bit 3. We also round the
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* value.
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*/
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#define I9XX_CSC_COEFF_FP(coeff, fbits) \
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(clamp_val(((coeff) >> (32 - (fbits) - 3)) + 4, 0, 0xfff) & 0xff8)
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#define I9XX_CSC_COEFF_LIMITED_RANGE \
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I9XX_CSC_COEFF_FP(CTM_COEFF_LIMITED_RANGE, 9)
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#define I9XX_CSC_COEFF_1_0 \
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((7 << 12) | I9XX_CSC_COEFF_FP(CTM_COEFF_1_0, 8))
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static bool crtc_state_is_legacy(struct drm_crtc_state *state)
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{
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return !state->degamma_lut &&
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!state->ctm &&
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state->gamma_lut &&
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state->gamma_lut->length == LEGACY_LUT_LENGTH;
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}
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/*
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* When using limited range, multiply the matrix given by userspace by
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* the matrix that we would use for the limited range. We do the
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* multiplication in U2.30 format.
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*/
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static void ctm_mult_by_limited(uint64_t *result, int64_t *input)
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{
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int i;
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for (i = 0; i < 9; i++)
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result[i] = 0;
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for (i = 0; i < 3; i++) {
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int64_t user_coeff = input[i * 3 + i];
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uint64_t limited_coeff = CTM_COEFF_LIMITED_RANGE >> 2;
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uint64_t abs_coeff = clamp_val(CTM_COEFF_ABS(user_coeff),
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0,
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CTM_COEFF_4_0 - 1) >> 2;
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result[i * 3 + i] = (limited_coeff * abs_coeff) >> 27;
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if (CTM_COEFF_NEGATIVE(user_coeff))
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result[i * 3 + i] |= CTM_COEFF_SIGN;
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}
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}
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/* Set up the pipe CSC unit. */
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static void i9xx_load_csc_matrix(struct drm_crtc *crtc)
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{
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struct drm_device *dev = crtc->dev;
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struct drm_crtc_state *crtc_state = crtc->state;
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struct drm_i915_private *dev_priv = dev->dev_private;
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struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
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int pipe = intel_crtc->pipe;
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uint16_t coeff = 0x7800; /* 1.0 */
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int i, pipe = intel_crtc->pipe;
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uint16_t coeffs[9] = { 0, };
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/*
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* TODO: Check what kind of values actually come out of the pipe
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* with these coeff/postoff values and adjust to get the best
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* accuracy. Perhaps we even need to take the bpc value into
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* consideration.
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*/
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if (crtc_state->ctm) {
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struct drm_color_ctm *ctm =
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(struct drm_color_ctm *)crtc_state->ctm->data;
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uint64_t input[9] = { 0, };
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if (intel_crtc->config->limited_color_range)
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coeff = ((235 - 16) * (1 << 12) / 255) & 0xff8; /* 0.xxx... */
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if (intel_crtc->config->limited_color_range) {
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ctm_mult_by_limited(input, ctm->matrix);
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} else {
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for (i = 0; i < ARRAY_SIZE(input); i++)
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input[i] = ctm->matrix[i];
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}
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I915_WRITE(PIPE_CSC_COEFF_RY_GY(pipe), coeff << 16);
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I915_WRITE(PIPE_CSC_COEFF_BY(pipe), 0);
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/*
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* Convert fixed point S31.32 input to format supported by the
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* hardware.
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*/
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for (i = 0; i < ARRAY_SIZE(coeffs); i++) {
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uint64_t abs_coeff = ((1ULL << 63) - 1) & input[i];
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I915_WRITE(PIPE_CSC_COEFF_RU_GU(pipe), coeff);
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I915_WRITE(PIPE_CSC_COEFF_BU(pipe), 0);
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/*
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* Clamp input value to min/max supported by
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* hardware.
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*/
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abs_coeff = clamp_val(abs_coeff, 0, CTM_COEFF_4_0 - 1);
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I915_WRITE(PIPE_CSC_COEFF_RV_GV(pipe), 0);
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I915_WRITE(PIPE_CSC_COEFF_BV(pipe), coeff << 16);
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/* sign bit */
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if (CTM_COEFF_NEGATIVE(input[i]))
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coeffs[i] |= 1 << 15;
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if (abs_coeff < CTM_COEFF_0_125)
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coeffs[i] |= (3 << 12) |
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I9XX_CSC_COEFF_FP(abs_coeff, 12);
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else if (abs_coeff < CTM_COEFF_0_25)
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coeffs[i] |= (2 << 12) |
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I9XX_CSC_COEFF_FP(abs_coeff, 11);
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else if (abs_coeff < CTM_COEFF_0_5)
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coeffs[i] |= (1 << 12) |
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I9XX_CSC_COEFF_FP(abs_coeff, 10);
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else if (abs_coeff < CTM_COEFF_1_0)
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coeffs[i] |= I9XX_CSC_COEFF_FP(abs_coeff, 9);
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else if (abs_coeff < CTM_COEFF_2_0)
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coeffs[i] |= (7 << 12) |
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I9XX_CSC_COEFF_FP(abs_coeff, 8);
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else
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coeffs[i] |= (6 << 12) |
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I9XX_CSC_COEFF_FP(abs_coeff, 7);
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}
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} else {
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/*
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* Load an identity matrix if no coefficients are provided.
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*
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* TODO: Check what kind of values actually come out of the
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* pipe with these coeff/postoff values and adjust to get the
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* best accuracy. Perhaps we even need to take the bpc value
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* into consideration.
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*/
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for (i = 0; i < 3; i++) {
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if (intel_crtc->config->limited_color_range)
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coeffs[i * 3 + i] =
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I9XX_CSC_COEFF_LIMITED_RANGE;
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else
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coeffs[i * 3 + i] = I9XX_CSC_COEFF_1_0;
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}
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}
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I915_WRITE(PIPE_CSC_COEFF_RY_GY(pipe), coeffs[0] << 16 | coeffs[1]);
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I915_WRITE(PIPE_CSC_COEFF_BY(pipe), coeffs[2] << 16);
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I915_WRITE(PIPE_CSC_COEFF_RU_GU(pipe), coeffs[3] << 16 | coeffs[4]);
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I915_WRITE(PIPE_CSC_COEFF_BU(pipe), coeffs[5] << 16);
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I915_WRITE(PIPE_CSC_COEFF_RV_GV(pipe), coeffs[6] << 16 | coeffs[7]);
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I915_WRITE(PIPE_CSC_COEFF_BV(pipe), coeffs[8] << 16);
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I915_WRITE(PIPE_CSC_PREOFF_HI(pipe), 0);
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I915_WRITE(PIPE_CSC_PREOFF_ME(pipe), 0);
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@ -85,13 +201,18 @@ static void i9xx_load_csc_matrix(struct drm_crtc *crtc)
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void intel_color_set_csc(struct drm_crtc *crtc)
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{
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i9xx_load_csc_matrix(crtc);
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struct drm_device *dev = crtc->dev;
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struct drm_i915_private *dev_priv = dev->dev_private;
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if (dev_priv->display.load_csc_matrix)
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dev_priv->display.load_csc_matrix(crtc);
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}
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/* Loads the palette/gamma unit for the CRTC with the prepared values. */
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/* Loads the legacy palette/gamma unit for the CRTC. */
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static void i9xx_load_luts(struct drm_crtc *crtc)
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{
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struct drm_device *dev = crtc->dev;
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struct drm_crtc_state *state = crtc->state;
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struct drm_i915_private *dev_priv = dev->dev_private;
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struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
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enum pipe pipe = intel_crtc->pipe;
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@ -104,18 +225,33 @@ static void i9xx_load_luts(struct drm_crtc *crtc)
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assert_pll_enabled(dev_priv, pipe);
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}
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for (i = 0; i < 256; i++) {
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uint32_t word = (intel_crtc->lut_r[i] << 16) |
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(intel_crtc->lut_g[i] << 8) |
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intel_crtc->lut_b[i];
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if (HAS_GMCH_DISPLAY(dev))
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I915_WRITE(PALETTE(pipe, i), word);
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else
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I915_WRITE(LGC_PALETTE(pipe, i), word);
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if (state->gamma_lut) {
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struct drm_color_lut *lut =
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(struct drm_color_lut *) state->gamma_lut->data;
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for (i = 0; i < 256; i++) {
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uint32_t word =
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(drm_color_lut_extract(lut[i].red, 8) << 16) |
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(drm_color_lut_extract(lut[i].green, 8) << 8) |
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drm_color_lut_extract(lut[i].blue, 8);
|
||||
|
||||
if (HAS_GMCH_DISPLAY(dev))
|
||||
I915_WRITE(PALETTE(pipe, i), word);
|
||||
else
|
||||
I915_WRITE(LGC_PALETTE(pipe, i), word);
|
||||
}
|
||||
} else {
|
||||
for (i = 0; i < 256; i++) {
|
||||
uint32_t word = (i << 16) | (i << 8) | i;
|
||||
|
||||
if (HAS_GMCH_DISPLAY(dev))
|
||||
I915_WRITE(PALETTE(pipe, i), word);
|
||||
else
|
||||
I915_WRITE(LGC_PALETTE(pipe, i), word);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
/* Loads the legacy palette/gamma unit for the CRTC on Haswell+. */
|
||||
/* Loads the legacy palette/gamma unit for the CRTC on Haswell. */
|
||||
static void haswell_load_luts(struct drm_crtc *crtc)
|
||||
{
|
||||
struct drm_device *dev = crtc->dev;
|
||||
|
|
@ -144,6 +280,89 @@ static void haswell_load_luts(struct drm_crtc *crtc)
|
|||
hsw_enable_ips(intel_crtc);
|
||||
}
|
||||
|
||||
/* Loads the palette/gamma unit for the CRTC on Broadwell+. */
|
||||
static void broadwell_load_luts(struct drm_crtc *crtc)
|
||||
{
|
||||
struct drm_device *dev = crtc->dev;
|
||||
struct drm_crtc_state *state = crtc->state;
|
||||
struct drm_i915_private *dev_priv = dev->dev_private;
|
||||
struct intel_crtc_state *intel_state = to_intel_crtc_state(state);
|
||||
enum pipe pipe = to_intel_crtc(crtc)->pipe;
|
||||
uint32_t i, lut_size = INTEL_INFO(dev)->color.degamma_lut_size;
|
||||
|
||||
if (crtc_state_is_legacy(state)) {
|
||||
haswell_load_luts(crtc);
|
||||
return;
|
||||
}
|
||||
|
||||
I915_WRITE(PREC_PAL_INDEX(pipe),
|
||||
PAL_PREC_SPLIT_MODE | PAL_PREC_AUTO_INCREMENT);
|
||||
|
||||
if (state->degamma_lut) {
|
||||
struct drm_color_lut *lut =
|
||||
(struct drm_color_lut *) state->degamma_lut->data;
|
||||
|
||||
for (i = 0; i < lut_size; i++) {
|
||||
uint32_t word =
|
||||
drm_color_lut_extract(lut[i].red, 10) << 20 |
|
||||
drm_color_lut_extract(lut[i].green, 10) << 10 |
|
||||
drm_color_lut_extract(lut[i].blue, 10);
|
||||
|
||||
I915_WRITE(PREC_PAL_DATA(pipe), word);
|
||||
}
|
||||
} else {
|
||||
for (i = 0; i < lut_size; i++) {
|
||||
uint32_t v = (i * ((1 << 10) - 1)) / (lut_size - 1);
|
||||
|
||||
I915_WRITE(PREC_PAL_DATA(pipe),
|
||||
(v << 20) | (v << 10) | v);
|
||||
}
|
||||
}
|
||||
|
||||
if (state->gamma_lut) {
|
||||
struct drm_color_lut *lut =
|
||||
(struct drm_color_lut *) state->gamma_lut->data;
|
||||
|
||||
for (i = 0; i < lut_size; i++) {
|
||||
uint32_t word =
|
||||
(drm_color_lut_extract(lut[i].red, 10) << 20) |
|
||||
(drm_color_lut_extract(lut[i].green, 10) << 10) |
|
||||
drm_color_lut_extract(lut[i].blue, 10);
|
||||
|
||||
I915_WRITE(PREC_PAL_DATA(pipe), word);
|
||||
}
|
||||
|
||||
/* Program the max register to clamp values > 1.0. */
|
||||
I915_WRITE(PREC_PAL_GC_MAX(pipe, 0),
|
||||
drm_color_lut_extract(lut[i].red, 16));
|
||||
I915_WRITE(PREC_PAL_GC_MAX(pipe, 1),
|
||||
drm_color_lut_extract(lut[i].green, 16));
|
||||
I915_WRITE(PREC_PAL_GC_MAX(pipe, 2),
|
||||
drm_color_lut_extract(lut[i].blue, 16));
|
||||
} else {
|
||||
for (i = 0; i < lut_size; i++) {
|
||||
uint32_t v = (i * ((1 << 10) - 1)) / (lut_size - 1);
|
||||
|
||||
I915_WRITE(PREC_PAL_DATA(pipe),
|
||||
(v << 20) | (v << 10) | v);
|
||||
}
|
||||
|
||||
I915_WRITE(PREC_PAL_GC_MAX(pipe, 0), (1 << 16) - 1);
|
||||
I915_WRITE(PREC_PAL_GC_MAX(pipe, 1), (1 << 16) - 1);
|
||||
I915_WRITE(PREC_PAL_GC_MAX(pipe, 2), (1 << 16) - 1);
|
||||
}
|
||||
|
||||
intel_state->gamma_mode = GAMMA_MODE_MODE_SPLIT;
|
||||
I915_WRITE(GAMMA_MODE(pipe), GAMMA_MODE_MODE_SPLIT);
|
||||
POSTING_READ(GAMMA_MODE(pipe));
|
||||
|
||||
/*
|
||||
* Reset the index, otherwise it prevents the legacy palette to be
|
||||
* written properly.
|
||||
*/
|
||||
I915_WRITE(PREC_PAL_INDEX(pipe), 0);
|
||||
}
|
||||
|
||||
void intel_color_load_luts(struct drm_crtc *crtc)
|
||||
{
|
||||
struct drm_device *dev = crtc->dev;
|
||||
|
|
@ -156,39 +375,61 @@ void intel_color_load_luts(struct drm_crtc *crtc)
|
|||
dev_priv->display.load_luts(crtc);
|
||||
}
|
||||
|
||||
void intel_color_legacy_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
|
||||
u16 *blue, uint32_t start, uint32_t size)
|
||||
int intel_color_check(struct drm_crtc *crtc,
|
||||
struct drm_crtc_state *crtc_state)
|
||||
{
|
||||
int end = (start + size > 256) ? 256 : start + size, i;
|
||||
struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
|
||||
struct drm_device *dev = crtc->dev;
|
||||
size_t gamma_length, degamma_length;
|
||||
|
||||
for (i = start; i < end; i++) {
|
||||
intel_crtc->lut_r[i] = red[i] >> 8;
|
||||
intel_crtc->lut_g[i] = green[i] >> 8;
|
||||
intel_crtc->lut_b[i] = blue[i] >> 8;
|
||||
}
|
||||
degamma_length = INTEL_INFO(dev)->color.degamma_lut_size *
|
||||
sizeof(struct drm_color_lut);
|
||||
gamma_length = INTEL_INFO(dev)->color.gamma_lut_size *
|
||||
sizeof(struct drm_color_lut);
|
||||
|
||||
intel_color_load_luts(crtc);
|
||||
/*
|
||||
* We allow both degamma & gamma luts at the right size or
|
||||
* NULL.
|
||||
*/
|
||||
if ((!crtc_state->degamma_lut ||
|
||||
crtc_state->degamma_lut->length == degamma_length) &&
|
||||
(!crtc_state->gamma_lut ||
|
||||
crtc_state->gamma_lut->length == gamma_length))
|
||||
return 0;
|
||||
|
||||
/*
|
||||
* We also allow no degamma lut and a gamma lut at the legacy
|
||||
* size (256 entries).
|
||||
*/
|
||||
if (!crtc_state->degamma_lut &&
|
||||
crtc_state->gamma_lut &&
|
||||
crtc_state->gamma_lut->length == LEGACY_LUT_LENGTH)
|
||||
return 0;
|
||||
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
void intel_color_init(struct drm_crtc *crtc)
|
||||
{
|
||||
struct drm_device *dev = crtc->dev;
|
||||
struct drm_i915_private *dev_priv = dev->dev_private;
|
||||
struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
|
||||
int i;
|
||||
|
||||
drm_mode_crtc_set_gamma_size(crtc, 256);
|
||||
for (i = 0; i < 256; i++) {
|
||||
intel_crtc->lut_r[i] = i;
|
||||
intel_crtc->lut_g[i] = i;
|
||||
intel_crtc->lut_b[i] = i;
|
||||
}
|
||||
|
||||
if (IS_HASWELL(dev) ||
|
||||
(INTEL_INFO(dev)->gen >= 8 && !IS_CHERRYVIEW(dev))) {
|
||||
if (IS_HASWELL(dev)) {
|
||||
dev_priv->display.load_csc_matrix = i9xx_load_csc_matrix;
|
||||
dev_priv->display.load_luts = haswell_load_luts;
|
||||
} else if (IS_BROADWELL(dev) || IS_SKYLAKE(dev) ||
|
||||
IS_BROXTON(dev) || IS_KABYLAKE(dev)) {
|
||||
dev_priv->display.load_csc_matrix = i9xx_load_csc_matrix;
|
||||
dev_priv->display.load_luts = broadwell_load_luts;
|
||||
} else {
|
||||
dev_priv->display.load_luts = i9xx_load_luts;
|
||||
}
|
||||
|
||||
/* Enable color management support when we have degamma & gamma LUTs. */
|
||||
if (INTEL_INFO(dev)->color.degamma_lut_size != 0 &&
|
||||
INTEL_INFO(dev)->color.gamma_lut_size != 0)
|
||||
drm_helper_crtc_enable_color_mgmt(crtc,
|
||||
INTEL_INFO(dev)->color.degamma_lut_size,
|
||||
INTEL_INFO(dev)->color.gamma_lut_size);
|
||||
}
|
||||
|
|
|
|||
|
|
@ -11911,6 +11911,12 @@ static int intel_crtc_atomic_check(struct drm_crtc *crtc,
|
|||
return ret;
|
||||
}
|
||||
|
||||
if (crtc_state->color_mgmt_changed) {
|
||||
ret = intel_color_check(crtc, crtc_state);
|
||||
if (ret)
|
||||
return ret;
|
||||
}
|
||||
|
||||
ret = 0;
|
||||
if (dev_priv->display.compute_pipe_wm) {
|
||||
ret = dev_priv->display.compute_pipe_wm(pipe_config);
|
||||
|
|
@ -11953,7 +11959,6 @@ static int intel_crtc_atomic_check(struct drm_crtc *crtc,
|
|||
|
||||
static const struct drm_crtc_helper_funcs intel_helper_funcs = {
|
||||
.mode_set_base_atomic = intel_pipe_set_base_atomic,
|
||||
.load_lut = intel_color_load_luts,
|
||||
.atomic_begin = intel_begin_crtc_commit,
|
||||
.atomic_flush = intel_finish_crtc_commit,
|
||||
.atomic_check = intel_crtc_atomic_check,
|
||||
|
|
@ -13576,6 +13581,18 @@ static int intel_atomic_commit(struct drm_device *dev,
|
|||
dev_priv->display.crtc_enable(crtc);
|
||||
}
|
||||
|
||||
if (!modeset &&
|
||||
crtc->state->active &&
|
||||
crtc->state->color_mgmt_changed) {
|
||||
/*
|
||||
* Only update color management when not doing
|
||||
* a modeset as this will be done by
|
||||
* crtc_enable already.
|
||||
*/
|
||||
intel_color_set_csc(crtc);
|
||||
intel_color_load_luts(crtc);
|
||||
}
|
||||
|
||||
if (!modeset)
|
||||
intel_pre_plane_update(to_intel_crtc_state(old_crtc_state));
|
||||
|
||||
|
|
@ -13686,8 +13703,9 @@ out:
|
|||
#undef for_each_intel_crtc_masked
|
||||
|
||||
static const struct drm_crtc_funcs intel_crtc_funcs = {
|
||||
.gamma_set = intel_color_legacy_gamma_set,
|
||||
.gamma_set = drm_atomic_helper_legacy_gamma_set,
|
||||
.set_config = drm_atomic_helper_set_config,
|
||||
.set_property = drm_atomic_helper_crtc_set_property,
|
||||
.destroy = intel_crtc_destroy,
|
||||
.page_flip = intel_crtc_page_flip,
|
||||
.atomic_duplicate_state = intel_crtc_duplicate_state,
|
||||
|
|
|
|||
|
|
@ -1668,9 +1668,8 @@ extern const struct drm_plane_helper_funcs intel_plane_helper_funcs;
|
|||
|
||||
/* intel_color.c */
|
||||
void intel_color_init(struct drm_crtc *crtc);
|
||||
int intel_color_check(struct drm_crtc *crtc, struct drm_crtc_state *state);
|
||||
void intel_color_set_csc(struct drm_crtc *crtc);
|
||||
void intel_color_load_luts(struct drm_crtc *crtc);
|
||||
void intel_color_legacy_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
|
||||
u16 *blue, uint32_t start, uint32_t size);
|
||||
|
||||
#endif /* __INTEL_DRV_H__ */
|
||||
|
|
|
|||
|
|
@ -379,6 +379,7 @@ retry:
|
|||
struct drm_connector *connector;
|
||||
struct drm_encoder *encoder;
|
||||
struct drm_fb_helper_crtc *new_crtc;
|
||||
struct intel_crtc *intel_crtc;
|
||||
|
||||
fb_conn = fb_helper->connector_info[i];
|
||||
connector = fb_conn->connector;
|
||||
|
|
@ -420,6 +421,13 @@ retry:
|
|||
|
||||
num_connectors_enabled++;
|
||||
|
||||
intel_crtc = to_intel_crtc(connector->state->crtc);
|
||||
for (j = 0; j < 256; j++) {
|
||||
intel_crtc->lut_r[j] = j;
|
||||
intel_crtc->lut_g[j] = j;
|
||||
intel_crtc->lut_b[j] = j;
|
||||
}
|
||||
|
||||
new_crtc = intel_fb_helper_crtc(fb_helper, connector->state->crtc);
|
||||
|
||||
/*
|
||||
|
|
|
|||
Загрузка…
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